JPH10339884A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the device which has high yield and high reliability by reducing the peeling of a wire, specially, peeling and cracking at a disconnection part of the wire by incorporating high-fusion-point metal in a data line and providing a semiconductor layer below the disconnection part of the data line. SOLUTION: On the surface of a TFT substrate on the side of a liquid crystal layer, gate lines GL which are provided in parallel to one another at intervals and data lines DL which are provided in parallel to one another at intervals while crossing the gate lines GL (insulated by an insulating film) are formed. The data lines DL are formed of a conductive film d1. For this conductive film d1, high-fusion-point metal, e.g. alloy of Cr and Mo is used. This device is provided with an (i) type amorphous Si semiconductor layer As and an (n) type amorphous Si semiconductor layer below the conductive film d1 at each disconnection part on a disconnection line. Consequently, the conductive film d1 is prevented from peeling and cracking.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device, and more particularly to an active matrix type liquid crystal display device using a switching element such as a thin film transistor.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active method has a better contrast than the so-called simple matrix method that employs the time-division driving method, and particularly the color liquid crystal. It is becoming an indispensable technology for display devices. A typical switching element is a thin film transistor (TFT).

Incidentally, an active matrix type liquid crystal display device using thin film transistors is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-309921 or "1.
2.5-inch active matrix color liquid crystal display, "Nikkei Electronics, pp. 193-210, 1986
Known on December 15, published by Nikkei McGraw-Hill.

A liquid crystal display panel of an active matrix type liquid crystal display device (ie, a liquid crystal display element or L
For example, a CD extends on the liquid crystal layer side surface of one of the transparent substrates which is disposed opposite to each other with a liquid crystal layer interposed therebetween, and extends in the x direction and is arranged in the y direction. A plurality of gate lines provided, and a plurality of data lines extending in the y-direction and juxtaposed in the x-direction via the gate line and the insulating film are formed, and in a region surrounded by these lines, , A unit pixel region, and each pixel region includes a thin film transistor and a pixel electrode.

These pixel electrodes are supplied with a video signal voltage from a data line through a thin film transistor which is turned on by the supply of a scanning signal voltage from a gate line,
As a result, an electric field is generated between the pixel electrode and the common pixel electrode formed on the other opposing substrate (in the case of the vertical electric field method), and the electric field causes the liquid crystal layer interposed between the pixel electrode and the common pixel electrode. Is modulated to perform a predetermined display.

The gate lines, data lines, thin film transistors, pixel electrodes, and the like are formed by forming different material layers in a predetermined pattern by a selective etching method using a photolithography technique, and sequentially laminating them. I do.

[0007] Such a liquid crystal display device is described in detail, for example, in JP-A-62-32651.

[0008]

In the manufacture of a substrate on which gate lines, data lines, thin film transistors, etc. are formed (hereinafter referred to as a TFT substrate), the substrate may invade from the outside during the manufacturing process, or may form on the substrate. Due to the generated static electricity, a high voltage is generated between the gate line and the data line, which causes a problem that the threshold voltage of the thin film transistor fluctuates, the thin film transistor is damaged, and the gate line and the data line are short-circuited. In order to avoid this electrostatic destruction, a common short-circuit line for electrically connecting each gate line and each data line at the outer periphery of the TFT substrate is formed after the completion of each layer forming step of the TFT substrate. Thus, when static electricity enters or occurs, the static electricity is dispersed and the above-mentioned electrostatic breakdown is prevented. In addition, in the product of the completed liquid crystal display panel,
It is necessary to release the short circuit between the gate line and the data line due to the short wiring. As described above, the short-circuit wiring is provided on the outer peripheral portion of the substrate, that is, outside the cutting line for finally cutting the TFT substrate. After the TFT substrate is assembled by being overlapped with the opposing substrate at a predetermined interval, the outer peripheral portion of the TFT substrate provided with the short-circuit wiring is cut at the cutting line, and the short-circuit is released. Is done.

However, conventionally, when the TFT substrate is cut and cut at right angles across a plurality of data lines or gate lines connected to the short-circuit wiring, peeling or cracking of the wiring occurs at the substrate cutting portion. There was a problem that was easy to do. In particular, when the wiring is formed of a high melting point metal such as an alloy of Cr (chromium) and Mo (molybdenum), the adhesive strength with the underlying silicon nitride film was low, and peeling and cracking were likely to occur.

[0010] Furthermore, the opposite substrate whose dimensions are smaller than that of the TFT substrate and whose three sides are located inside the TFT substrate is also cut after assembling the two substrates.
There is also a problem that the wiring is apt to peel or crack at a location corresponding to the cut portion.

When the wiring is peeled in this way, the peeled wiring comes into contact with an adjacent wiring to cause a short circuit, which causes a display failure and lowers the production yield. Further, when a crack is generated in the wiring, wiring corrosion is generated from the crack, and the reliability is reduced. Further, a resin applied for the purpose of protecting the cut end of the wiring, an adhesive for fixing the chip in a COG (chip-on-glass) method in which a driving IC chip is directly mounted on a substrate, or an anisotropic conductive film. Due to the shrinkage, there is also a problem that the wiring having a low adhesive strength at the cut portion is damaged, and the reliability is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device which has a high yield and a high reliability by reducing the peeling of the wiring, particularly the peeling and cracking at the cut portion of the wiring.

[0013]

In order to solve the above-mentioned problems, according to the present invention, of a pair of substrates arranged to face each other with a liquid crystal layer interposed therebetween, one of the substrates has x
A plurality of gate lines extending in the direction and juxtaposed in the y direction; a plurality of data lines extending in the y direction and juxtaposed in the x direction via the gate line and an insulating film; A liquid crystal display device, comprising: a liquid crystal display panel provided with a thin film transistor that is turned on by a scanning signal supplied through a line and a pixel electrode that supplies a video signal from the data line through the turned on thin film transistor. Comprises a high melting point metal, and a semiconductor layer is provided at least below the cut portion of the data line.

The data line has a single-layer structure of an alloy of Cr and Mo, a lower layer has a two-layer structure of Cr and an upper layer has Mo,
Cr has a lower layer and an upper layer has a two-layer structure of an alloy of Cr and Mo.
, A single-layer structure of Mo, or a structure having an Al layer on these refractory metal wirings.

Preferably, the width of the semiconductor layer is equal to or larger than the width of the refractory metal wiring.

In the present invention, since the semiconductor layer is provided at least below the cut portion of the data line, the adhesive strength to the lower layer of the data line can be increased.
It is possible to provide a liquid crystal display device with reduced wiring separation and cracks, high yield, and high reliability.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a vertical electric field / COG type active matrix type liquid crystal display device will be described in detail with reference to the drawings. In addition,
In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

Embodiment 1 FIG. 5 is a sectional view of an essential part of a liquid crystal display panel PNL (A in FIG. 4).
It is sectional drawing corresponding to 1-A2 cutting line.

The liquid crystal display panel PNL is a so-called TFT substrate TFTS which is arranged opposite to each other with a predetermined gap therebetween.
The UB and its opposing substrate OPSUB are used as an envelope.
A liquid crystal layer LC is interposed between the pair of substrates.

On the surface of the TFT substrate TFTSUB on the liquid crystal layer LC side, a gate line (scanning signal line) GL, a thin film transistor TFT, a data line (video signal line) DL, a transparent pixel electrode ITO1, etc. are formed. OPS
On the surface of the UB on the liquid crystal layer LC side, a light-shielding film (black matrix) BM, a color filter FIL, a common transparent pixel electrode ITO2, and the like are formed.

Although not shown in the figure, in the unit pixel (in a color display, one pixel is constituted by three adjacent unit pixels), the thin film transistor TFT scans the scanning signal from the gate line GL. And the turned-on thin film transistor TF
The video signal from the data line DL is supplied to the pixel electrode ITO1 via T, and an electric field is generated between the pixel electrode ITO1 and the common pixel electrode ITO2 according to the voltage applied to them.

As a result, the liquid crystal layer LC between the pixel electrode ITO1 and the common pixel electrode ITO2 is modulated, so that its light transmittance changes.

For example, light from a backlight (not shown) arranged outside the TFT substrate TFTSUB is supplied to the liquid crystal layer LC.
And the opposing substrate OPS via the color filter FIL
The light is transmitted to the outside of the UB, that is, to the display observation side.

SUB1 and SUB2 are transparent glass substrates, ORI1 and ORI2 are alignment films, POL1 and POL2.
Is a polarizing plate.

Hereinafter, each of the above-mentioned components will be described in sequence.

<< TFT Substrate TFTSUB >> FIG.
FIG. 1 is a main part plan view showing a plane pattern of a unit pixel and its peripheral region as viewed from the liquid crystal layer LC side of the T substrate TFTSUB.
3 is a cross-sectional view taken along the line A1-A2 in FIG.

In each figure, first, a TFT substrate TFTS
On the surface of the UB on the side of the liquid crystal layer LC, a plurality of gate lines GL provided in parallel and separated from each other, and intersected with these gate lines GL (insulated by the insulating film GI) and separated in parallel. And a plurality of data lines DL provided.

Two gate lines GL adjacent to each other
A pixel region is formed by a region surrounded by two data lines DL which are also adjacent to each other. In each of these pixel regions, a pixel electrode ITO1 is formed over substantially the entire region.

The thin film transistor TFT functioning as a switching element is formed on the gate line GL corresponding to each pixel electrode ITO1, and its source electrode SD1 is connected to the pixel electrode ITO1.

The scanning signal voltage supplied to the gate line GL is applied to the gate electrode of the thin film transistor TFT formed in a part of the gate line GL to turn on the thin film transistor TFT. At this time, the data line DL Is supplied to the source electrode SD.
1 is written to the pixel electrode ITO1.

<< Gate Line GL >> As shown in FIG. 13, the gate line GL is formed of a single conductive film g1. The conductive film g1 has a thickness of 600 to 3000 Å
Cr (chromium) or Mo (molybdenum), or an alloy of these with another high melting point metal is used. In this example,
Cr formed by sputtering with a thickness of about 2000 mm
And Mo alloy films (Cr 50 wt%, Mo 50 wt%) were used.

<< Gate Terminal GTM >> FIG. 6 is a cross-sectional view of the gate terminal GTM along the gate line GL. As shown in the figure, the gate terminal portion GTM includes a conductive film g1 that forms the gate line GL, a gate insulating film GI that covers the conductive film g1, and a protective film having substantially the same planar shape as the gate insulating film GI. It is composed of a film PSV1 and a conductive film d2 made of a transparent conductive film ITO connected to the conductive film g1. The gate terminal GTM is a TFT substrate TF
It functions to electrically and mechanically connect a drive circuit outside the TSUB and the gate line GL. Also,
In the manufacturing process of the TFT substrate TFTSUB, it is also used as an inspection terminal for inspecting disconnection or short circuit of the gate line GL.

<< Data Line DL >> FIG. 2 is a plan view of the data line DL formed on the TFT substrate TFTSUB, the drain terminal DTM, the terminal DFCA for connecting the driving IC to an external driving circuit, and the periphery thereof. is there. FIG.
1 is shown in FIG. 1. FIG.
The TCPT is a terminal for connecting to an output terminal of a flexible printed circuit (FPC) for inputting an external signal.

The data line DL is formed of the conductive film d1. This conductive film d1 is made of a high melting point metal such as Cr
Or an alloy of Mo. In this example, Cr 70 wt
%, Mo 30 wt% alloy was used. In addition, Cr80
wt%, Mo20wt%, or Cr50wt%, M
o50 wt% or the like may be used.

<< Drain Terminal DTM >> FIG. 1 shows a cut portion DCUT of the data line DL connected to the drain terminal DTM, the data line DL in the display area GSO, and the common short wiring DCL1 (see FIG. 3 described later).
FIG. 2 is a cross-sectional view along the wiring direction of FIG.

As shown in FIG.
Is composed of a conductive film d1 forming the data line DL, a protective film PSV1 covering the conductive film d1, and a conductive film d2 formed of an ITO film connected to the conductive film d1. A drive circuit for applying a voltage signal from the outside is connected to the data line DL, and is used as an inspection terminal in the same manner as the gate terminal GTM.

<< Thin Film Transistor TFT >> As shown in FIG. 5, a gate line GL is formed on a transparent glass substrate SUB1.
Is formed, and a gate insulating film GI, a semiconductor layer AS, and the like are formed on a part of the surface thereof, thereby forming a thin film transistor TFT. For example, when a bias voltage is applied on the gate line GL, the thin film transistor TFT has a source electrode SD
When the channel resistance between the 1-drain electrode (data line DL) decreases and the bias voltage is reduced to zero, the channel resistance operates to increase.

A gate insulating film GI made of silicon nitride (Si) is formed on the gate electrode, which is a region of the gate line GL.
Is formed thereon, and an i-type semiconductor layer AS made of amorphous Si to which an impurity is not intentionally added and an n-type semiconductor layer d0 made of amorphous Si to which an impurity is added are formed thereon. Further, a source electrode SD1 and a drain electrode (the data line DL plays a role thereof, and the drain electrode is hereinafter referred to as a data line DL unless otherwise specified) are formed thereon to constitute a thin film transistor TFT.

As the gate insulating film GI, for example, Si nitride formed by a plasma CVD method is selected.
It is formed to a thickness of 00 to 5000 ° (about 3500 ° in this example).

The i-type semiconductor layer AS has a thickness of 500 to 2500 °
(In this example, about 2000 mm).
The n-type semiconductor layer d0 is provided to form an ohmic contact with the i-type semiconductor layer AS, and is formed of an amorphous Si semiconductor layer doped with P (phosphorus).

In the liquid crystal display panel PNL of this embodiment,
For convenience, one is fixedly called a source electrode and the other is fixedly called a drain electrode. The names of the source electrode and the drain electrode are originally determined by the characteristics of the bias between them, but the polarity is inverted during operation, and the source electrode and the drain electrode are switched.

<< Source electrode SD1 >> Source electrode SD1
Is formed on the n-type Si semiconductor layer d0 and the gate insulating film GI, and is constituted by a conductive film d1.

<< Transparent Pixel Electrode ITO1 >> Pixel Electrode ITO
1 is a crystalline indium tin oxide (Indium-Tin-Oxide:
It is formed of a transparent conductive film d2 such as ITO. The transparent conductive film d2 is formed of an ITO sputtering film, and has a thickness of 300 to 3000 ° (1400 in this example).
Å).

<< Retention Capacity Cadd >> As shown in FIG.
The storage capacitor Cadd is formed on the gate line GL on the side opposite to the side on which the thin film transistor TFT is formed, and the insulating film GI and the protective film PSV1 are formed on the gate line GL.
, And a capacitance of a region overlapping with the pixel electrode ITO1 extending across the pixel electrode ITO1. The storage capacitor Cadd has a function of preventing the capacitance of the liquid crystal layer LC from attenuating and preventing a voltage drop when the thin film transistor TFT is turned off.

<< Protective Film PSV1 >> As shown in FIGS. 4 and 5, the thin film transistor TFT of the TFT substrate TFTSUB is used.
The surface on the liquid crystal layer LC side on which the
Except for a region where the gate terminal portion GTM and the drain terminal portion DTM provided in the periphery of the SUB are formed, the protective film PSV
Covered with 1.

The protective film PSV1 is formed mainly for the purpose of protecting the thin film transistor TFT from moisture and the like, and is formed of, for example, a 2000 to 8000 ° thick silicon oxide film or a silicon nitride film by a plasma CVD method. Further, in this example, a short circuit between the data line DL and the pixel electrode ITO1 is prevented. That is, in the manufacturing process, even if the two films are overlapped in a plane due to the processing failure of the pattern of the data line DL or the pixel electrode ITO1, the protection film PS is formed.
Since it is insulated and separated by V1, short-circuit failure can be prevented.

<< Optical Substrate OPSUB >> As shown in FIG. 5, a transparent glass substrate SUB2 is
It is arranged to face the substrate TFTSUB with a gap corresponding to the liquid crystal layer LC. The liquid crystal layer L of the opposing substrate OPSUB
On the surface on the C side, a light-shielding film (black matrix) BM, red, green, and blue color filters FIL and a protective film PSV
2. A common transparent pixel electrode ITO2 and an orientation film ORI2 are sequentially laminated. Also, the opposing substrate OPS
A polarizing plate POL2 is attached on the surface on the opposite side of the UB, and the transmitted light is polarized by the polarizing plate POL1 on the opposite surface of the TFT substrate TFTSUB on which the thin film transistor TFT is not formed. ing.

The light-shielding film BM is formed of a sputtering film of Cr, a black organic film, a graphite film, or the like. The light-shielding film BM also functions as a black matrix that separates light in a frame shape for each pixel electrode ITO1 and improves contrast while shielding light. To fulfill.

<< Method of Manufacturing TFT Substrate TFTSUB >> Next, the TFT substrate TFT of the liquid crystal display panel PNL described above.
The method of manufacturing the SUB will be described with reference to FIGS. FIG. 7 is a flowchart summarizing the flow of the manufacturing process into steps 1 to 5. The sectional structures of steps 1 to 5 in FIG.
It is shown corresponding to FIG. 8 to 13 show the gate line GL and the data line DL of the TFT substrate TFTSUB.
5 is a cross-sectional view (corresponding to FIG. 5 which is a cross-sectional view taken along line A1-A2 of FIG. 4) crossing the pixel electrode ITO1 and further crossing the gate line GL from the intersection. FIG. 13 shows the final cross-sectional structure of step 5 in FIG.

Each of (a) and (b) shown in FIGS.
FIGS. 1 and 6 are cross-sectional views of a data line DL including a data terminal portion DTM and a gate terminal portion GTM in steps 1 to 5 of FIG. 7, respectively.

Hereinafter, each step will be described in order.

Step 1 A transparent glass substrate SUB1 is prepared, and an alloy film of Cr and Mo is formed on one surface thereof by sputtering to form a gate line GL. After a mask film such as a photoresist film having a predetermined pattern is formed on the alloy film by photolithography (hereinafter abbreviated as photo processing; first photo), the alloy film is selectively etched to form a predetermined pattern. The conductive film g1 is formed (see FIGS. 8 and 14B). In this example, wet etching was performed using a ceric ammonium nitrate solution of about 15 wt%.

Step 2 Next, the transparent glass substrate SUB provided on the conductive film g1
1 on the silicon nitride film G by a plasma CVD method, for example.
I, i-type amorphous Si semiconductor layer AS, and n-type amorphous S
An i semiconductor layer d0 is formed sequentially.

Next, after forming a mask film by photo-processing (second photo), an n-type amorphous Si semiconductor layer d0 is formed by using a mixed gas of sulfur hexafluoride (SF ₆ ) and hydrogen chloride (HCl). The i-type amorphous Si semiconductor layer AS is removed by etching (see FIGS. 9, 15A and 15B). In this step, the channel portion of the thin film transistor TFT, the intersection of the gate line GL and the data line DL and the periphery thereof (FIG.
And a cutting portion DC of the data line DL described later.
I-type amorphous S of UT1 and DCUT2 (see FIGS. 1 and 3)
An i semiconductor layer AS and an n-type amorphous Si semiconductor layer d0 are formed. At this time, since the etching is performed for a while after the surface of the Si nitride film GI is exposed so that there is no residue of the i-type amorphous Si semiconductor layer AS in the etching, the surface of the Si nitride film GI is slightly etched. Is done.

Step 3 Next, the source electrode S is formed on the transparent glass substrate SUB1.
In order to form D1 and the data line DL (drain electrode), an alloy film of Cr and Mo is formed by sputtering. In this example, Cr 70 wt%, Mo 30 wt%
(Alternatively, Cr 50 wt%, Mo 50 wt%) alloy film was formed to a thickness of 200 nm. After a mask film is formed on this alloy film by photo processing (third photo), the alloy film is selectively etched to form a predetermined pattern (see FIG. 10). In this step, the conductive film d1 forming the data line DL, the drain terminal DTM, and the source electrode SD1 is processed into a desired shape.

FIG. 3 shows a data line DL and a common short wiring DC on the TFT substrate TFTSUB at the end of this process.
FIG. 2 is a schematic configuration diagram of L1, DCL2, and a drain terminal DTM as viewed from above the film. As shown in the figure, at the time when this step is completed, every other data line DL is connected to the common short-circuit lines DCL1 and DCL2 outside the display area GSO. Thereby, the subsequent TFT substrate TF
In the TSUB manufacturing process and the LCD cell assembling process, it is possible to prevent a short circuit failure, a change in transistor characteristics, and the like induced by static electricity that enters the data line DL due to discharge or charging. That is, by connecting the data line DL to the common short-circuit wirings DCL1 and DCL2 in this step, the data line DL enters the data line DL in a step of forming a protective film PSV2 by a plasma CVD method and an etching step of processing the film, which will be described later. Failure due to static electricity can be prevented. Note that the common short-circuit wiring DC
The data lines DL connected to L1 and DCL2 are cut in the cut portions DCUT1 and DCUT2 by a wire cutting step described later, and are finally processed into electrically independent wires.

Next, using the mask film of the conductive film d1 formed in the above step, the n-type amorphous Si semiconductor layer d0 is
The dry etching is selectively performed with a mixed gas of F ₆ and BCl ₃ (boron trichloride) (FIGS. 11 and 16A).
(B)).

Step 4 Next, a plasma CV is placed on the transparent glass substrate SUB1.
By the method D, a silicon nitride film to be the protection film PSV1 is provided.
The film thickness is about 2000-6000 °. In this example,
3000 °. After that, photo processing (4th photo)
A mask film is formed on the Si nitride film. Thereafter, the Si nitride film is etched using a mixed gas of SF ₆ and oxygen. By this step, the contact hole portion CH connected to the source electrode SD1 and the drain terminal portion D
The protective film PSV1 above the connection between the TM and the gate terminal GTM is removed (see FIGS. 12, 17A and 17B). Further, in the gate terminal portion GTM, the gate insulating film GI of the connection portion is also removed to expose the metal surface of the terminal portion.

Step 5 Next, a conductive film d2 made of an ITO film is provided on the transparent glass substrate SUB1 by sputtering. After forming a mask film by the photo processing (fourth photo), the second conductive film d2 is selectively etched with an HBr (hydrogen bromide) solution to form a pixel electrode ITO1 (FIGS. 13, 1 and 1). 6). At this time, the gate terminal GT
M, drain terminal part DTM, pixel part contact hole C
The exposed metal terminal surface of H is a conductive film d2 (ITO film)
Covered by The ITO film at the terminal portion is electrically connected to an underlying metal film, and functions to transmit a voltage signal from a driving IC connected to the ITO film to the gate line GL and the drain line DL. In addition, it functions to protect the metal film of the terminal portion from chemical reaction such as corrosion and mechanical damage.

Through the above steps, the TFT substrate TFTS
The various film stacking steps of the UB are completed.

<< Cutting Step >> Next, the data line DL (T
The step of cutting the FT substrate (TFTSUB) will be described.
The cutting step is a step of cutting the data line DL connected to the common short-circuit wirings DCL1 and DCL2 (FIG. 3) arranged for the purpose of protection against static electricity, as indicated by the cutting line C shown in FIG.
Cutting is performed along the cutting parts DCUT1 and DCUT2 along L1 and CL2. Note that the cutting process is performed on the TFT substrate TFTSUB.
Is performed from the end of each layer forming step until the driving IC is connected to the terminal portion. In this example, the TFT substrate TFTSU
Immediately before connecting the drive IC directly mounted on B to the terminal portion, the glass substrate SUB1 was mechanically broken. Breaking was performed by applying a load to the back surface of the glass substrate SUB1 by applying a load to the back surface of the glass substrate SUB1 using a glass cutter using diamond. The data line D of each cutting part DCUT1 and DCUT2 on the cutting lines CL1 and CL2 after cutting.
It is desirable that the end of L has a structure free from film peeling and cracking. This is because when peeling occurs, it comes into contact with an adjacent wiring, causing display failure, and when cracking occurs, wiring corrosion occurs, lowering reliability.

In this embodiment, the cutting lines CL1, CL2
Under the conductive film d1 constituting the data line DL in each of the upper cut portions DCUT1 and DCUT2, an i-type amorphous S
By providing the i-semiconductor layer AS and the n-type amorphous Si semiconductor layer d0, the conductive film d1 can be prevented from peeling and cracking. This is because the adhesive strength between the insulating film GI under the conductive film d1 and the amorphous Si layer is higher than that of the insulating film G1.
This is because the bonding strength between I and the Cr—Mo film is larger.
That is, the n-type amorphous Si semiconductor layer d0 and the i-type amorphous S
When the i-semiconductor layer AS is not disposed below the conductive film d1, the conductive film d1 is formed of SF ₆ for patterning the n-type amorphous Si semiconductor layer d0 and the i-type amorphous Si semiconductor layer AS.
Is formed on the Si nitride film GI whose surface is roughened by etching with a mixed gas of hydrogen and hydrogen chloride, so that the adhesive strength is reduced and the film is peeled off. In the structure of the present embodiment, the surface of the lower n-type amorphous Si semiconductor layer d0 in contact with the conductive film d1 is covered with the conductive film d1 which is a mask film when the conductive film d1 is etched. When patterning the film d1, good adhesiveness can be maintained.

Embodiment 2 In this embodiment, a case where a laser beam is used as a method for cutting the data line DL will be described. In the present embodiment, a 1 kHz pulse oscillation YAG3 ⁺ laser by the Q-switch method is condensed to a diameter of about 20 μm and is incident almost perpendicularly from above the film surface. As a laser light source,
Another pulsed laser such as an excimer laser may be used, or a continuous wave light source such as an argon laser may be used. As described above, the present structure is effective even when the mechanical cutting method is not used as in the first embodiment. Cutting part DCUT1 of the data line DL,
The DCUT 2 is heated and melted by the irradiation of the laser beam, but in the case of the present embodiment, the n-type amorphous Si semiconductor layer d0 having a larger light absorption coefficient than the SiN film GI.
Exist around the wiring. Therefore, the efficiency of heating by laser light is improved, and there is also an effect that processing can be performed with a lower-power laser light source. As a result, the cutting unit DCUT
1. Damage generated around the DCUT 2 can be minimized, and a good cut surface without peeling or cracking of the data line DL can be obtained.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various changes can be made without departing from the gist of the present invention. It is. For example, the present invention can be applied to a vertical electric field type or a horizontal electric field type active matrix type liquid crystal display device, a COG (chip-on-glass) type liquid crystal display device, or a simple matrix type liquid crystal display device. Needless to say. In the above embodiment, Cr and Mo are used as the data lines DL.
For example, the lower layer was a two-layer structure of Cr / the upper layer was Mo, the lower layer was a two-layer structure of Cr / the upper layer was an alloy of Cr and Mo, a single layer structure of Cr, a single layer of Mo was used. The present invention is also effective when a high-melting point metal film having another structure such as a structure or a structure having an Al layer on these high-melting point metal wirings (there is no Al film at the terminal connection portion) is included. Also, TF
The opposing substrate OPSUB, whose dimensions are smaller than the T-substrate TFTSUB and whose three sides are located inside the substrate, is also cut after assembling the two substrates. Although there is a problem that the wiring is apt to peel or crack at the place where it occurs, arranging the semiconductor layer under the data line DL at the place is effective in preventing the data line DL at the place from peeling. further,
In the above embodiment, a semiconductor layer is provided below the data line to prevent peeling.However, the number of manufacturing steps can be increased by providing a semiconductor layer below the data line to prevent peeling of the gate line. is there.

[0065]

As described above, according to the present invention,
It is possible to prevent the occurrence of peeling or cracking at the cut portion of the terminal wiring, and to provide a liquid crystal display device with high yield and high reliability.

[Brief description of the drawings]

FIG. 1 shows a data line DL in a drain terminal DTM and a display area GSO, and a common short-circuit wiring DCL1.
(FIG. 3) A cut portion DC of the data line DL connected to the data line DL
FIG. 3 is a cross-sectional view along the wiring direction of the UT1.

FIG. 2 is a plan view of a data line DL formed on a TFT substrate TFTSUB, a drain terminal DTM, a terminal DFCA for connecting a driving IC to an external driving circuit, and a periphery thereof.

FIG. 3 shows a TFT substrate TFT at the end of step 3 in FIG.
The data line DL on the SUB, the common short wiring DCL1,
FIG. 3 is a schematic configuration diagram of DCL2 and a drain terminal DTM as viewed from above the film.

FIG. 4 is a main part plan view showing a plane pattern of a unit pixel and a peripheral area thereof as viewed from the liquid crystal layer LC side of the TFT substrate TFTSUB.

FIG. 5 is a sectional view of a main part of the liquid crystal display panel PNL.

FIG. 6 is a cross-sectional view of a gate terminal portion GTM in a direction along a gate line GL.

FIG. 7 shows a flow of a manufacturing process of the TFT substrate TFTSUB by 1
6 is a flowchart summarizing the steps of steps # 1 to # 5.

FIG. 8 is a final cross-sectional structure diagram of step 1 in FIG. 7 (A1- in FIG. 4);
(Corresponding to a sectional view taken along the line A2).

FIG. 9 is a final cross-sectional structural diagram of step 2 in FIG. 7 (A1- in FIG. 4);
(Corresponding to a sectional view taken along the line A2).

10 is a sectional structural view of a step 3 in FIG. 7 (A1-A in FIG. 4);
(Corresponding to a sectional view taken along line 2).

FIG. 11 is a final cross-sectional structural diagram of step 3 in FIG. 7 (A1 in FIG. 4);
(Corresponding to a sectional view taken along the line A2).

FIG. 12 is a final cross-sectional structure diagram of step 4 in FIG. 7 (A1 in FIG. 4);
(Corresponding to a sectional view taken along the line A2).

FIG. 13 is a final cross-sectional structural diagram of step 5 in FIG. 7 (A1 in FIG. 4);
-A2 section view).

14 is a sectional view of a data terminal portion DTM, a data line DL, and a gate terminal portion GTM in Step 1 of FIG. 7;

15 is a cross-sectional view of a data terminal portion DTM, a data line DL, and a gate terminal portion GTM in Step 2 of FIG.

16 is a sectional view of a data terminal portion DTM, a data line DL, and a gate terminal portion GTM in Step 3 of FIG.

17 is a cross-sectional view of the data terminal portion DTM, the data line DL, and the gate terminal portion GTM in Step 4 of FIG.

[Explanation of symbols]

SUB1: transparent glass substrate, GI: Si nitride film (gate insulating film), AS: i-type amorphous Si semiconductor layer, d0: n-type amorphous Si semiconductor layer, DL: data line, d1: conductive film, PSV1 ... Protective film, ITO1 (d2) ... Transparent conductive film.

Claims (3)

[Claims] 1. A plurality of gate lines extending in the x direction and juxtaposed in the y direction on a surface of one of a pair of substrates opposed to each other with a liquid crystal layer interposed therebetween, on a surface of the one substrate on the liquid crystal layer side. A plurality of data lines extending in the y-direction and juxtaposed in the x-direction via the gate line and the insulating film; a thin film transistor turned on by a scanning signal supplied through the gate line; A liquid crystal display device having a liquid crystal display panel provided with a pixel electrode for supplying a video signal from the data line via a thin film transistor, wherein the data line includes a high melting point metal, and at least a cut portion of the data line is provided. A liquid crystal display device comprising a lower semiconductor layer. 2. The data line according to claim 1, wherein the data line has a single-layer structure of an alloy of Cr and Mo, a lower layer has a two-layer structure of Cr / an upper layer of Mo, a lower layer has a two-layer structure of Cr / an upper layer of an alloy of Cr and Mo, 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device has a single-layer structure, a single-layer structure of Mo, or a structure having an Al layer on these refractory metal wirings. 3. The liquid crystal display device according to claim 1, wherein a width of said semiconductor layer is equal to or greater than a width of said high melting point metal wiring.