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JPH10335511A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH10335511A
JPH10335511A JP13818097A JP13818097A JPH10335511A JP H10335511 A JPH10335511 A JP H10335511A JP 13818097 A JP13818097 A JP 13818097A JP 13818097 A JP13818097 A JP 13818097A JP H10335511 A JPH10335511 A JP H10335511A
Authority
JP
Japan
Prior art keywords
solder
conductor layer
wiring board
semiconductor package
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13818097A
Other languages
Japanese (ja)
Inventor
Yuji Fujita
祐治 藤田
Tokuo Nakajo
徳男 中條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13818097A priority Critical patent/JPH10335511A/en
Publication of JPH10335511A publication Critical patent/JPH10335511A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】 【課題】高周波特性と接続信頼性の両面に優れた半導体
パッケージを提供する 【解決手段】半導体素子を搭載できる配線基板(10)
と、配線基板(10)を取り囲むケース(20)と、高
周波端子(30)とを備えた半導体パッケージにおい
て、配線基板(10)の側面に形成された側面導体層を
配線基板の表面まで延設してなる延設導体層(43)が
形成されており、延設導体層(43)は半田(51)に
よりケース(20)の枠部(20a)と電気的かつ機械
的に接続されている。これにより、半田(51)の表面
積を従来に比べて広くできるので、表面における歪みが
緩和され、半田接合部の信頼性が増す。その結果、グラ
ンド電流の経路の電気的な乱れが小さくなり、グランド
電流に生じるノイズを低減することができる。
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package excellent in both high frequency characteristics and connection reliability. [Solution] Wiring board on which semiconductor element can be mounted (10)
And a case (20) surrounding the wiring board (10) and a high-frequency terminal (30), a side conductor layer formed on the side face of the wiring board (10) is extended to the surface of the wiring board. Is formed, and the extended conductor layer (43) is electrically and mechanically connected to the frame portion (20a) of the case (20) by the solder (51). . As a result, the surface area of the solder (51) can be made larger than before, so that distortion on the surface is reduced and the reliability of the solder joint is increased. As a result, electric disturbance of the path of the ground current is reduced, and noise generated in the ground current can be reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は高周波用半導体パッ
ケージに係り、特に高周波信号特性と接続信頼性の両面
に優れた半導体パッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency semiconductor package, and more particularly to a semiconductor package excellent in both high-frequency signal characteristics and connection reliability.

【0002】[0002]

【従来の技術】まず、従来の半導体パッケージを図4お
よび図5を用いて説明する。図4において、参照符号1
0は配線基板、20は金属ケース、20aは枠部、30
は高周波端子、31は中心導体、40は配線導体、50
は半田である。また、図5は、図4のB−B’線に沿っ
た断面における一部詳細図である。
2. Description of the Related Art First, a conventional semiconductor package will be described with reference to FIGS. In FIG. 4, reference numeral 1
0 is a wiring board, 20 is a metal case, 20a is a frame, 30
Is a high-frequency terminal, 31 is a center conductor, 40 is a wiring conductor, 50
Is solder. FIG. 5 is a partially detailed view of a cross section taken along line BB ′ of FIG.

【0003】図5において、配線導体40は、半田50
を介して中心導体31と電気的に接続されている。ま
た、グランド層である第一の導体層11は側面導体層4
1と電気的に接続されており、側面導体層41は半田5
1を介して金属ケース20の枠部20aと電気的に接続
されている。
In FIG. 5, a wiring conductor 40 includes a solder 50
And is electrically connected to the center conductor 31 via. The first conductor layer 11 serving as a ground layer is a side conductor layer 4.
1 and the side conductor layer 41 is solder 5
1, and is electrically connected to the frame portion 20a of the metal case 20.

【0004】このような従来例では、高周波電流が、配
線導体40および半田50を介して中心導体31へ伝搬
する。同時にグランド電流が、同軸導体33から、金属
ケース20の枠部20a、半田51、側面導体層41を
介して第一の導体層11へ伝搬する。
In such a conventional example, a high-frequency current propagates to the center conductor 31 via the wiring conductor 40 and the solder 50. At the same time, the ground current propagates from the coaxial conductor 33 to the first conductor layer 11 via the frame portion 20a of the metal case 20, the solder 51, and the side conductor layer 41.

【0005】一般に高周波電流とグランド電流の経路が
近接しているほど電気力線、磁力線の空間的な拡がりが
少なくなり、波形の歪みは低減し、外部ノイズによる影
響は少なくなる。本実施例では、側面導体層41を半田
51を用いて金属ケース20の枠部20aと接続するこ
とにより、グランド電流の経路を高周波電流の経路に近
接させているので、信号劣化の少ない、高周波特性に優
れた半導体パッケージを実現できる。
In general, the closer the path of the high-frequency current and the ground current is, the smaller the spatial spread of the lines of electric force and lines of magnetic force is, the less the distortion of the waveform is, and the less the influence of external noise is. In this embodiment, since the side surface conductor layer 41 is connected to the frame portion 20a of the metal case 20 by using the solder 51, the path of the ground current is made close to the path of the high frequency current. A semiconductor package having excellent characteristics can be realized.

【0006】[0006]

【発明が解決しようとする課題】上述した従来例では、
金属ケース20の基台20bと配線基板10の熱膨張係
数の差により、熱歪みが半田51に加わる。その結果図
6に示すように半田51の内部に亀裂Cが生じ、部分的
に電気的な導通が得られなくなる。このため、グランド
電流の経路に乱れが生じ、波形の歪みが増大し、外部ノ
イズの影響も受けやすくなる。
In the above-mentioned conventional example,
Due to the difference in thermal expansion coefficient between the base 20b of the metal case 20 and the wiring board 10, thermal distortion is applied to the solder 51. As a result, as shown in FIG. 6, a crack C is generated inside the solder 51, and electrical conduction cannot be partially obtained. For this reason, disturbance occurs in the path of the ground current, waveform distortion increases, and the circuit is easily affected by external noise.

【0007】本発明の目的は、上記した半田亀裂の発生
や進展を防ぐことで、高周波特性と接続信頼性の両面に
優れた高周波信号用半導体パッケージを提供することに
ある。
An object of the present invention is to provide a high-frequency signal semiconductor package which is excellent in both high-frequency characteristics and connection reliability by preventing the above-mentioned solder cracks from being generated or propagated.

【0008】[0008]

【課題を解決するための手段】本発明に係る半導体パッ
ケージは、半導体素子を搭載できる配線基板と、前記配
線基板を取り囲む枠部および基台からなるケースと、前
記枠部を貫通するように設けられた導電体からなる高周
波端子とを備え、前記配線基板の配線導体と前記高周波
端子とが電気的に接続されており、前記配線基板の側面
に形成された側面導体層と前記枠部とを電気的に接続す
る半導体パッケージにおいて、前記側面導体層は、前記
配線基板の表面まで延設された延設導体層を有してお
り、前記延設導体層は前記枠部と電気的かつ機械的に接
続されていることを特徴としている。
A semiconductor package according to the present invention is provided with a wiring board on which a semiconductor element can be mounted, a case including a frame and a base surrounding the wiring board, and provided so as to penetrate the frame. A high-frequency terminal made of a conductive material provided, wherein the wiring conductor of the wiring board and the high-frequency terminal are electrically connected, and a side conductor layer and a frame formed on a side surface of the wiring board are provided. In the semiconductor package to be electrically connected, the side conductor layer has an extension conductor layer extending to a surface of the wiring board, and the extension conductor layer is electrically and mechanically connected to the frame. It is characterized by being connected to.

【0009】[0009]

【発明の実施の形態】以下、この発明の実施例について
図1乃至図3を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

【0010】図1および図2は本発明に係る半導体パッ
ケージを概略的に示す斜視図および平面図である。ま
た、図3は図2のA−A’線に沿った断面における一部
詳細図である。
FIGS. 1 and 2 are a perspective view and a plan view schematically showing a semiconductor package according to the present invention. FIG. 3 is a partially detailed view of a cross section taken along line AA ′ of FIG.

【0011】本発明に係る半導体パッケージは、側面導
体層をさらに延設した延設導体層を有する点で従来例と
異なる。すなわち、配線基板10の表面において、側面
導体層41を延設した延設導体層43が配線導体40を
挟むように形成されている。延設導体層43は側面導体
層41と同様に半田に濡れやすい金属層からなるので、
図3に示すように半田51が延設導体層43の上面まで
濡れ拡がることができる。
The semiconductor package according to the present invention differs from the conventional example in that it has an extended conductor layer further extending the side conductor layer. That is, on the surface of the wiring substrate 10, the extended conductor layer 43 formed by extending the side conductor layer 41 is formed so as to sandwich the wiring conductor 40. Since the extended conductor layer 43 is made of a metal layer that is easily wetted by solder, like the side conductor layer 41,
As shown in FIG. 3, the solder 51 can spread to the upper surface of the extended conductor layer 43.

【0012】半田51の表面に露出された部分の面積
は、図6に示した従来例に比べて広くなっているので、
半田51の表面に発生する熱歪みは従来例より緩和され
る。また、半田51に亀裂が生じたとしても、側面導体
層41と枠部20aとの間隙まで亀裂が進展しない限
り、グランド電流の経路を電気的に乱すような影響は生
じない。以上の効果により、接続信頼性と高周波特性と
の両面に優れた半導体パッケージが得られる。
The area of the portion exposed on the surface of the solder 51 is larger than that of the conventional example shown in FIG.
Thermal distortion generated on the surface of the solder 51 is lessened than in the conventional example. Even if a crack occurs in the solder 51, as long as the crack does not extend to the gap between the side surface conductor layer 41 and the frame portion 20a, there is no effect that the ground current path is electrically disturbed. By the above effects, a semiconductor package excellent in both connection reliability and high frequency characteristics can be obtained.

【0013】次に本発明の組立手順を説明する。Next, the assembly procedure of the present invention will be described.

【0014】まず、研削加工または精密鋳造などの方法
により枠部20aおよび基台20bを有する金属ケース
20を形成する。このとき、高周波端子30を取り付け
るための貫通孔も枠部20aに形成しておく。配線基板
10として、熱膨張係数の小さいセラミック基板などを
用いる場合は、金属ケース20の材料として熱膨張係数
の比較的小さいコバールを用いれば、半田に加わる熱歪
みが低減し、接続信頼性を高めることができる。次に、
半田への濡れ性を確保するために、金属ケース20の表
面にニッケルまたは金などのメッキ層を形成しておく
(図示せず)。
First, a metal case 20 having a frame portion 20a and a base 20b is formed by a method such as grinding or precision casting. At this time, a through hole for attaching the high-frequency terminal 30 is also formed in the frame portion 20a. When a ceramic substrate or the like having a small thermal expansion coefficient is used as the wiring board 10, if Kovar having a relatively small thermal expansion coefficient is used as the material of the metal case 20, thermal distortion applied to the solder is reduced, and connection reliability is improved. be able to. next,
In order to ensure the wettability to the solder, a plating layer of nickel or gold is formed on the surface of the metal case 20 (not shown).

【0015】配線基板10の底面導体層42、側面導体
層41、配線導体40および延設導体層43に対して
も、半田への濡れ性を確保するためにニッケルまたは金
などのメッキ層を形成しておく。
A plating layer of nickel or gold is formed on the bottom conductor layer 42, the side conductor layer 41, the wiring conductor 40, and the extension conductor layer 43 of the wiring board 10 in order to ensure wettability to solder. Keep it.

【0016】あらがじめ金属ケースの基台20bの上面
にクリーム半田を供給しておき、前記配線基板10を金
属ケースの枠部20aの中に搭載する。延設導体層43
の上面にもクリーム半田を供給し、全体を加熱して半田
を溶融し、冷却して半田を凝固させた後、クリーム半田
から流出したフラックスなどを洗浄する。ここで、延設
導体層43の上面に供給される半田量が足りずに充分な
半田フィレットが形成されない場合は、再度クリーム半
田を延設導体層43の上面に供給し、半田の溶融および
凝固を行なう。
The solder paste is supplied to the upper surface of the base 20b of the metal case in advance, and the wiring board 10 is mounted in the frame portion 20a of the metal case. Extension conductor layer 43
Cream solder is also supplied to the upper surface, and the whole is heated to melt the solder, and cooled to solidify the solder, and then the flux or the like flowing out of the cream solder is washed. Here, if the amount of solder supplied to the upper surface of the extended conductor layer 43 is insufficient and a sufficient solder fillet is not formed, cream solder is supplied again to the upper surface of the extended conductor layer 43 to melt and solidify the solder. Perform

【0017】枠部20aに設けられた貫通孔に高周波端
子30を取り付ける。本実施例ではスパークプラグタイ
プの高周波端子を用い、ネジのはめ合いにより枠部20
aと密着させた。同様な高周波端子として、同軸導体3
3のフランジ部分を枠部20aにネジを用いて取り付け
るタイプを使用してもよい。最後に、中心導体31と配
線導体40を半田50により接合して本発明の組立を完
了する。
A high-frequency terminal 30 is mounted in a through hole provided in the frame portion 20a. In this embodiment, a spark plug type high-frequency terminal is used, and the frame portion 20 is fitted by screw fitting.
a. As a similar high-frequency terminal, a coaxial conductor 3
A type in which the flange portion of No. 3 is attached to the frame portion 20a using screws may be used. Finally, the center conductor 31 and the wiring conductor 40 are joined by the solder 50 to complete the assembly of the present invention.

【0018】以上、本発明の好適な実施例について説明
したが、本発明は前記実施例に限定されることはなく、
以下のような種々の設計変更を成し得る。本実施例で
は、配線導体40の直下にグランド層である第一の導体
層11を設けることで、マイクロストリップ線路を形成
した。ここで、配線導体40の直上にもグランド層を設
ければ、配線構造をストリップ線路に変更できる。ま
た、配線導体40と同じ平面内において延設導体層43
に接続されたグランド層を設ければ、配線構造をコプレ
ーナ線路に変更できる。
Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiment.
Various design changes can be made as follows. In the present embodiment, the microstrip line is formed by providing the first conductor layer 11 which is the ground layer immediately below the wiring conductor 40. Here, if a ground layer is also provided immediately above the wiring conductor 40, the wiring structure can be changed to a strip line. In the same plane as the wiring conductor 40, the extension conductor layer 43
The wiring structure can be changed to a coplanar line by providing a ground layer connected to.

【0019】[0019]

【発明の効果】本発明によれば、延設導体層の上面まで
半田が濡れ拡がるので、半田の表面積は従来に比べて広
くなる。このため、半田の表面において歪みが緩和さ
れ、亀裂の発生や進展を防ぐことができる。その結果、
グランド電流の経路である半田接合部の電気的な乱れが
小さくなり、グランド電流に生じるノイズが低減でき
る。
According to the present invention, since the solder spreads to the upper surface of the extended conductor layer, the surface area of the solder becomes wider than before. For this reason, the strain is alleviated on the surface of the solder, and the generation and propagation of cracks can be prevented. as a result,
Electrical disturbance of the solder joint, which is a path of the ground current, is reduced, and noise generated in the ground current can be reduced.

【0020】従って、接続信頼性と高周波特性との両面
に優れた半導体パッケージを実現することができる。
Therefore, a semiconductor package excellent in both connection reliability and high frequency characteristics can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体パッケージの一実施例を概
略的に示す斜視図である。
FIG. 1 is a perspective view schematically showing one embodiment of a semiconductor package according to the present invention.

【図2】本発明に係る半導体パッケージの一実施例を概
略的に示す平面図である。
FIG. 2 is a plan view schematically showing one embodiment of a semiconductor package according to the present invention.

【図3】本発明に係る半導体パッケージの一実施例の一
部詳細を示す断面図である。
FIG. 3 is a sectional view showing a part of a semiconductor package according to an embodiment of the present invention;

【図4】従来例の半導体パッケージの一実施例を概略的
に示す斜視図である。
FIG. 4 is a perspective view schematically showing one embodiment of a conventional semiconductor package.

【図5】従来例の半導体パッケージの一実施例の一部詳
細を示す断面図である。
FIG. 5 is a cross-sectional view showing a part of a conventional semiconductor package in detail.

【図6】従来例の半導体パッケージにおいて亀裂が進展
する様子を概略的に示す断面図である。
FIG. 6 is a cross-sectional view schematically showing a state where a crack develops in a conventional semiconductor package.

【符号の説明】[Explanation of symbols]

10…配線基板、11…第一の導体層、12…第二の導
体層、20…金属ケース、20a…枠部、20b…基
台、30…高周波端子、31…中心導体、32…誘電
体、33…同軸導体、40…配線導体、41…側面導体
層、42…底面導体層、43…延設導体層、50,51
…半田。
DESCRIPTION OF SYMBOLS 10 ... Wiring board, 11 ... First conductor layer, 12 ... Second conductor layer, 20 ... Metal case, 20a ... Frame part, 20b ... Base, 30 ... High frequency terminal, 31 ... Central conductor, 32 ... Dielectric Reference numerals 33, coaxial conductor, 40 wiring conductor, 41 side conductor layer, 42 bottom conductor layer, 43 extended conductor layer, 50, 51
…solder.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体素子を搭載できる配線基板と、前記
配線基板を取り囲む枠部および基台からなるケースと、
前記枠部を貫通するように設けられた導電体からなる高
周波端子とを備え、前記配線基板の配線導体と前記高周
波端子とが電気的に接続されており、前記配線基板の側
面に形成された側面導体層と前記枠部とを電気的に接続
する半導体パッケージにおいて、 前記側面導体層は、前記配線基板の表面まで延設された
延設導体層を有しており、前記延設導体層は前記枠部と
電気的かつ機械的に接続されていることを特徴とする半
導体パッケージ。
A case comprising a wiring board on which a semiconductor element can be mounted, a frame surrounding the wiring board, and a base;
A high-frequency terminal made of a conductor provided so as to penetrate the frame portion, wherein a wiring conductor of the wiring board and the high-frequency terminal are electrically connected to each other and formed on a side surface of the wiring board. In a semiconductor package for electrically connecting a side conductor layer and the frame portion, the side conductor layer has an extension conductor layer extending to a surface of the wiring board, and the extension conductor layer is A semiconductor package electrically and mechanically connected to the frame.
JP13818097A 1997-05-28 1997-05-28 Semiconductor package Pending JPH10335511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13818097A JPH10335511A (en) 1997-05-28 1997-05-28 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13818097A JPH10335511A (en) 1997-05-28 1997-05-28 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH10335511A true JPH10335511A (en) 1998-12-18

Family

ID=15215929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13818097A Pending JPH10335511A (en) 1997-05-28 1997-05-28 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH10335511A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012151232A (en) * 2011-01-18 2012-08-09 Kyocera Corp Package for housing electronic component, and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012151232A (en) * 2011-01-18 2012-08-09 Kyocera Corp Package for housing electronic component, and electronic device

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