JPH10334699A - Semiconductor memory device capable of multiple word line selection - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a semiconductor memory device capable of shortening a test time of a memory cell. A semiconductor memory device capable of performing a test operation sequentially selects a plurality of word drivers that keep a word line active until reset when selected, and a plurality of word drivers during a test operation. A control circuit for simultaneously activating word lines corresponding to the selected word driver is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a memory cell test function.

[0002]

2. Description of the Related Art In a semiconductor memory device such as a DRAM,
An inspection is performed by the manufacturer prior to product shipment to check whether the memory cell operates properly for data storage. In a test called a disturb test, a certain word line is activated and information "0" or "1" is written to a memory cell. Next, the word line is deactivated, and activation / deactivation of a nearby word line is repeated. Thereafter, the word line is raised again to check whether the data of the memory cell stored first is correctly read. By this test, it is possible to inspect whether or not the data of the memory cell on a certain word line is affected by driving the surrounding word lines.

[0003]

In a conventional DRAM, one row address latch circuit for latching a row address is provided for each bank. Therefore, when a bank is activated, only one row address can be accessed in that bank. As described above, in the conventional DRAM, the number of word lines that can be activated at one time is one. When performing the disturb test, each word line is sequentially selected one by one and activated. It is necessary to perform activation / deactivation.

[0004] With the development of integrated circuit technology, the capacity of DRAMs has been increasing, and the number of word lines inside the DRAM has also increased. In such a large-capacity DRAM, the time required for testing a one-chip DRAM becomes enormous, and a technique for reducing the testing time is desired. Accordingly, it is an object of the present invention to provide a semiconductor memory device capable of shortening a memory cell inspection time.

[0005]

According to the first aspect of the present invention, a semiconductor memory device capable of performing a test operation includes a plurality of word drivers for keeping a word line active until a reset is performed when selected. A control circuit is provided which sequentially selects one or more of the plurality of word drivers during a test operation and simultaneously activates word lines corresponding to the selected word drivers.

In the above invention, once a plurality of word drivers are selected, the active state of the word lines is maintained until they are reset. Therefore, by sequentially selecting one or more word drivers, multiple selection of word lines is performed.・ Activation can be realized. This makes it possible to significantly reduce the inspection time of the memory cells as compared with the case where only one word line can be activated.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, when each of the plurality of word drivers is selected, the selected state is latched to activate the word line. And a signal input terminal for resetting the latch circuit. In the above invention, since each of the plurality of word drivers includes a resettable latch, the active state can be maintained by causing the latch to latch the selected state.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, the control circuit sends a timing pulse for instructing a timing of activating the word line to the plurality of word drivers. Each of the plurality of word drivers further includes a decoding unit that causes the latch to latch the selected state when a signal indicating a corresponding row address and the timing pulse are input.

In the above invention, one of the plurality of word drivers is selected by a signal designating a row address, and the selected state is latched by a timing pulse.
According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the control circuit receives a timing signal indicating a timing for activating the word line, and outputs the timing signal as the timing pulse. Word line multiple selection avoidance circuit, the word line multiple selection avoidance circuit outputs all the timing signals as the timing pulses during the test operation, and only the first timing signal during normal operation other than the test operation. Is output as the timing pulse, and the timing pulse is not output even if the timing signal is input until the timing signal is reset thereafter.

In the above invention, a word line multiple selection avoiding circuit is provided which permits multiple selection of word lines during a test operation and prevents multiple selection of word lines during a normal operation. In normal operation, control can be performed such that only one word line can be activated. According to a fifth aspect of the present invention, in the semiconductor memory device according to the second aspect, the signal input terminal receives a reset signal when a precharge command is input to the semiconductor memory device. .

In the above invention, one or more word lines that are simultaneously activated can be deactivated by inputting a precharge command. According to a sixth aspect of the present invention, in the semiconductor memory device according to the first aspect, the plurality of word drivers include at least one redundant word driver, and when a row address of a defective memory cell is specified, A redundant word driver is selected.

In the above-mentioned invention, the memory cell for redundancy can be inspected by using the redundant word driver even during the test operation. According to a seventh aspect of the present invention, a semiconductor memory device capable of performing a test operation includes a plurality of word lines and a word line control circuit for simultaneously activating one or more of the plurality of word lines during the test operation. It is characterized by the following.

In the above invention, multiple selection of word lines is performed.
By realizing the activation, it becomes possible to significantly reduce the inspection time of the memory cell as compared with the case where only one word line can be activated. In the semiconductor memory device according to the present invention, the word line control circuit may include a plurality of word drivers for keeping a word line active until it is reset when selected. A control circuit that sequentially selects one or more of the plurality of word drivers during the test operation and simultaneously activates word lines corresponding to the selected word drivers.

In the above invention, since a plurality of word drivers, once selected, maintain the active state of the word lines until reset, the word lines are multi-selected by sequentially selecting one or more word drivers.・ Activation can be realized. This makes it possible to significantly reduce the inspection time of the memory cells as compared with the case where only one word line can be activated.

According to a ninth aspect of the present invention, a method for testing a memory cell in a semiconductor memory device comprises providing a latch for holding a selected state for each word driver for activating a word line, and providing at least one word. A latch of a driver is set to selectively activate at least one word line, data is written to a memory cell corresponding to the at least one word line, and a latch of the at least one word driver is reset to reset the at least one word line. Deactivate the lines, set the latches of one or more word drivers to simultaneously activate one or more word lines near the at least one word line, and activate the one or more word lines And the steps of reading out data from the memory cell by selectively activating the at least one word line again. It is characterized in.

In the above-mentioned invention, the word line is multi-selected.
Since the test is performed after activation, the test time of the memory cell can be significantly reduced as compared with the case where only one word line can be activated. According to a tenth aspect of the present invention, a method of testing a memory cell in a semiconductor memory device includes selectively activating at least one word line, writing data to a memory cell corresponding to the at least one word line, One or more word lines near the at least one word line are simultaneously activated, the activation and deactivation of the one or more word lines are repeated, and the at least one word line is selectively activated again. And reading data from the memory cell.

In the above-mentioned invention, the word line is multi-selected.
Since the test is performed after activation, the test time of the memory cell can be significantly reduced as compared with the case where only one word line can be activated.

[0018]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a DRAM according to the present invention.
FIG. 1 includes an address buffer 11, a command buffer 12, and a command decoder 1.
3, includes a row control unit 14, a word decoder 15, a memory cell circuit 16, a column decoder 17, and a column control unit 18. FIG. 1 shows only a command signal path and an address signal path for explaining the word line control according to the present invention, and the input / output paths of data signals are omitted.

In the DRAM 10 of FIG. 1, a word line control unit 20 including a row control unit 14 and a word decoder 15 is different from a conventional DRAM. D of the present invention
In the RAM 10, the word line control unit 20 is configured so that a plurality of word lines can be simultaneously selected and activated at the time of memory cell inspection. The detailed configuration of the word line control unit 20 will be described later.

In the DRAM 10 shown in FIG. 1, an address signal input to an address buffer 11 is supplied to a row control unit 14 for controlling row address access and a column control unit 18 for controlling column address access. Is done. The command signal input to the command buffer 12 is decoded by the command decoder 13 and controls the row control unit 14 and the column control unit 18 according to the contents of the command.

The row control unit 14 controls the word decoder 15 to selectively activate a word line. As a result, the memory cell of the selectively activated word line in the memory cell circuit 16 is selected, and an access relating to a row address can be performed. The column control unit 18 controls the column decoder 17 to select a column selection line. As a result, it is possible to select a column address in a direction orthogonal to the selected row address and access the column address. By specifying the row address and the column address in this manner, it is possible to access a memory cell at a predetermined position among the memory cells arranged in a matrix in the memory cell circuit 16.

Row control unit 14, word decoder 1
5, the memory cell circuit 16, the column decoder 17, and the column control unit 18 are provided for each of the plurality of banks 20. In a conventional DRAM, the row control unit of each bank has one row address latch for latching a row address, and only one word line can be selected in each bank.

In the present invention, the word decoder 15
Each word line is provided with a latch indicating whether the word line is selected or not. Under the control of the row control unit 14, a plurality of word lines can be selectively activated at the time of memory cell inspection. FIG. 2 is a block diagram showing a part of the word line control unit 20 of FIG. The word line control unit 20 of FIG. 1 is the same as that of the prior art except for the configuration shown in FIG. 2, and FIG. 2 shows only a portion relating to the present invention.

The word line control unit 20 shown in FIG. 2 includes a timing control unit 31, a redundancy selection unit 32, a redundancy word driver 33, and a plurality of word drivers 34. The timing control unit 31 receives a bank address decode signal, a timing signal, and a test signal. These signals are the same as those used in the prior art, and the bank address decode signal becomes HIGH when the bank is selected. The test signal is
When a test command is input to the DRAM 10 of FIG.
It goes HIGH to indicate a memory cell test. The timing signal is a signal for instructing the timing for activating the word line. The timing control unit 31
When the bank is selected, a timing signal indicating the timing for activating the word line is sent to the redundancy selection unit 3.
Feed to 2.

The redundancy selection unit 32 supplies the timing pulse from the timing control unit 31 to the redundancy word driver 33 when the redundancy selection signal is HIGH, and the timing control unit 3 when the redundancy selection signal is LOW.
The timing pulse from the plurality of word drivers 34
To supply. The redundant word driver 33 is a word driver for accessing a substitute memory cell (redundant memory cell) for a defective memory cell. When an attempt is made to access a defective memory cell, the redundancy selection unit 32 switches the access destination to the redundancy memory cell of the redundancy word driver 33 by the same redundancy selection signal as in the prior art.

Each of the redundant word driver 33 and the plurality of word drivers 34 has a 1-bit latch, and when the row address is selected, the output word line is kept active until reset. The redundant word driver 33 activates a word line when a timing pulse is supplied when the redundant selection signal is HIGH. The word driver 34 activates a word line when a timing pulse is supplied when the row address decode signal RAD is HIGH. The row address decode signal RAD is a signal indicating the decoded row address, and only one corresponding to the selected row address becomes HIGH.

FIG. 3 is a circuit diagram showing a circuit configuration of the timing control unit 31 and the redundancy selection unit 32.
The timing control unit 31 includes NAND circuits 41 to 43, a delay element 44, an OR circuit 45, and an inverter 4.
6 inclusive. When the HIGH pulse of the timing signal arrives while the bank address decode signal and the test signal are HIGH, the output of the NAND circuit 41 becomes LOW. Accordingly, a HIGH pulse is supplied to the redundant selection unit 32 via the inverter 46.

The reset signal RST is normally HIGH, and when the output of the NAND circuit 41 becomes LOW,
The latch composed of NAND circuits 42 and 43 is HI
Latch the GH output. The HIGH output signal of the latch is
Delayed by the delay element 44,
It is supplied to the OR circuit 45 as a W signal. Therefore, in a case where the test signal is LOW and the normal operation is not performed at the time of the memory cell inspection, if the timing signal is inputted once, the OR circuit 4
5 becomes LOW, so that the subsequent HIGH pulse of the timing signal does not pass through the NAND circuit 41. This can prevent one or more word lines from being selected simultaneously during normal operation. That is, multiple selection of word lines can be avoided.

During a normal operation, the reset signal RST is LOW.
, The latch constituted by the NAND circuits 42 and 43 latches the LOW output. Therefore, inverter 47
Input to the OR circuit 45 becomes HIGH, and the
The circuit 41 passes the HIGH pulse of the next timing signal. During the test operation, since the test signal is HIGH, the function of the feedback loop for preventing the selection of one or more word lines is invalidated, and the NAND circuit 41 can pass all HIGH pulses of the timing signal.

The redundancy selection unit 32 includes an AND circuit 5
1, a NOR circuit 52 and an inverter 53 are included. When the redundancy selection signal is HIGH, the output of the NOR circuit 52 is always LOW, and the output of the AND circuit 51 is a HIGH pulse supplied from the timing control unit 31. Conversely, when the selection signal is LOW, the AND circuit 51
Is always LOW, and the output of the NOR circuit 52 is HIGH which is supplied from the timing control unit 31.
It becomes a pulse. The output of the AND circuit 51 is supplied to the redundant word driver 33, and the output of the NOR circuit 52 is supplied to the word driver.

FIG. 4 is a circuit diagram showing a circuit configuration of the redundant word driver 33 and the word driver 34. The word driver 34 (or redundant word driver 33) of FIG.
Is a decoding unit 61, a latch 62, a reset NMOS
It includes a transistor 63 and inverters 64 and 65. The decoding unit 61 outputs a row address decode signal RA
When D and the timing signal become HIGH, the input of the latch 62 is made LOW. The latch 62
The HIGH output is latched by the W input. HI of latch 62
The GH output is supplied to inverters 64 and 65 for driving word lines.
Is supplied to the word line.

The decoding section 61 includes NMOS transistors 71 and 72. The latch 62 includes PMOS transistors 73 and 74 and NMOS transistors 75 and 76. The above operation can be realized by these transistors. In the word driver shown in FIG. 4, once selected, the reset signal WRST becomes HI.
Until GH is reset, a HIGH-level potential is continuously output to the word line. This makes it possible to simultaneously activate a plurality of word lines during a memory cell test. Note that the reset signal WRST may be a signal that becomes HIGH in synchronization with the precharge operation.

FIG. 5 is a timing chart showing the operation of simultaneously activating a plurality of word lines. After a test command TEST is input to the DRAM 10 of FIG. 1, an activation command ACTV for activating a word line
Is input in succession. Every time each activation command ACTV is input, a HIGH pulse of a timing signal is input to the timing control unit 31 of FIG. 2 in synchronization with the clock signal CLK. Also, in synchronization with the activation command ACTV, the row address R
A1 to RA5 are input.

The HIGH pulse input to the timing control unit 31 is supplied to a redundant word driver 33 or a plurality of word drivers 34. As a result, five word drivers corresponding to the row addresses RA1 to RA5 are sequentially selected, and the output word line WL1 is output.
To WL5 are successively set to HIGH. The HIGH-level word lines WL1 to WL5 are reset by the precharge command PRE.

As described above, a plurality of word lines can be simultaneously activated during a test operation. FIG. 6 is a diagram illustrating a disturbance test when a plurality of word lines are activated at the same time. FIG. 6 is a diagram showing a configuration around a word line in the memory cell circuit 16 of FIG. As shown in FIG. 6, word lines WL1 to WLn
Are connected to the gate input of the cell gate transistor 81. When one of the word lines WL1 to WLn is selectively activated, the cell gate transistor 81 connected to the selected word line is turned on. When the cell gate transistor 81 is turned on, data stored in the memory cell 82 as a capacitor is read out to the bit line BL. The opposite is true for a write operation.

In the present invention, a disturb test can be performed on a plurality of word lines at the time of memory cell inspection. Although a predetermined number of word lines can be inspected, for example, it is assumed that word lines are inspected every two lines for the sake of explanation. In this case, for example, the word line WL2 among the word lines WL1 to WLn is activated by the word driver 34 in FIG. The data is supplied to the bit line BL, and the data is written to the memory cell 82 corresponding to the activated word line. When the data writing is completed, the word line WL2 is deactivated. A series of activation / deactivation operations are sequentially performed on even-numbered word lines WL4,.

Next, the odd-numbered word lines WL1, WL3,... Are simultaneously activated, and
Repeat deactivation several times. After this operation, the even-numbered word lines WL2, WL4,... Are sequentially activated / deactivated one by one, and the data of the memory cell 82 corresponding to each word line is read out and written first. Check if the data is read correctly. As a result, it is possible to simultaneously execute the disturbance inspection on a plurality of word lines.

In the present invention, when activating a plurality of word lines, the rising of each word line is not actually simultaneous, but each word line is sequentially raised as shown in FIG. Become. Therefore, in order to simultaneously activate m word lines, a total of m cycles are required when the word lines are activated every cycle as shown in FIG. However, if only one word line can be activated, as in the prior art, it takes one cycle or more from the activation of one word line to the activation of the next word line. Therefore, by performing multiple word line selection as in the present invention, the inspection time can be greatly reduced.

FIG. 7 shows each bank 2 of the DRAM 10 of FIG.
1 is a block diagram showing a part of a word line control unit 20 when a row address is divided into blocks and word line selection is controlled for each block. 7, the same elements as those of FIG. 2 are referred to by the same numerals, and a description thereof will be omitted. 7, a redundancy selection unit 32A is provided instead of the redundancy selection unit 32 shown in FIG. 2, and a block selection unit 35 is further added.

The block selection unit 35 receives a block address decode signal which becomes HIGH when the block is selected, and a timing pulse from the timing control unit 31. Timing pulse is HIG
When it becomes H, the block selection unit 35 latches the block address decode signal. Therefore, when the block is selected and the timing pulse becomes HIGH, the block selection unit 35 outputs HIGH.

The redundancy selection unit 32A supplies an output only when the output from the block selection unit 35 is HIGH. The redundancy selection unit 32A outputs the redundancy selection signal H
In the case of IGH, the timing pulse from the timing control unit 31 is supplied to the redundant word driver 33, and when the redundant selection signal is LOW, the timing control unit 31
Are supplied to the plurality of word drivers 34. The output from the block selection unit 35 is LO
In the case of W, these outputs are not supplied.

The block selection unit 35 is a latch circuit which can be realized with a simple configuration, and includes a redundancy selection unit 32A.
Is a logic circuit that can be realized with a simple configuration, and a detailed description of the configuration will be omitted. As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be modified and changed within the scope of the claims.

[0043]

According to the first aspect of the present invention, once a plurality of word drivers are selected, the active state of the word lines is maintained until reset, so that one or more word drivers are sequentially selected. Multiple selection and activation of word lines can be realized. This makes it possible to significantly reduce the inspection time of the memory cells as compared with the case where only one word line can be activated.

According to the second aspect of the present invention, since each of the plurality of word drivers includes a resettable latch, an active state can be maintained by causing the latch to latch a selected state. According to the third aspect of the present invention, one of the plurality of word drivers is selected by a signal designating a row address, and the selected state is latched by a timing pulse.

According to the fourth aspect of the present invention, there is provided a word line multiple selection avoiding circuit which permits the multiple selection of the word lines during the test operation and prevents the multiple selection of the word lines during the normal operation. Although possible, control can be performed such that only one word line can be activated during normal operation. According to the fifth aspect of the present invention, one or more simultaneously activated word lines can be deactivated by inputting a precharge command.

According to the sixth aspect of the present invention, the memory cells for redundancy can be tested using the redundant word driver even during the test operation. In the invention of claim 7,
By implementing multiple selection and activation of word lines, compared to the case where only one word line could be activated at a time,
Inspection time of a memory cell can be significantly reduced.

According to the eighth aspect of the present invention, once a plurality of word drivers are selected, the active state of the word lines is maintained until the word lines are reset. Can be selected and activated. This makes it possible to significantly reduce the inspection time of the memory cells as compared with the case where only one word line can be activated.

According to the ninth aspect of the present invention, the inspection is performed with multiple selection and activation of the word lines, so that the inspection time of the memory cells can be reduced as compared with the case where only one word line can be activated. Can be greatly reduced. According to the tenth aspect of the present invention, the inspection is performed with multiple selection and activation of the word lines, so that the inspection time of the memory cells is significantly reduced as compared with the case where only one word line can be activated. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a DRAM according to the present invention.

FIG. 2 is a block diagram showing a part of the word line control unit of FIG.

FIG. 3 is a circuit diagram showing a circuit configuration of a timing control unit and a redundancy selection unit.

FIG. 4 is a circuit diagram showing a circuit configuration of a redundant word driver and a word driver.

FIG. 5 is a timing chart showing an operation of simultaneously activating a plurality of word lines.

FIG. 6 is a diagram illustrating a disturb test when a plurality of word lines are activated simultaneously.

7 is a block diagram showing a part of a word line control unit when a row address is divided into blocks in each bank of the DRAM of FIG. 1 and word line selection is controlled for each block.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Address buffer 12 Command buffer 13 Command decoder 14 Row control unit 15 Word decoder 16 Memory cell circuit 17 Column decoder 18 Column control unit 20 Word line control unit 21 Bank 31 Timing control unit 32, 32A Redundancy selection unit 33 Redundant word driver 34 words Driver 35 Block selection unit 61 Decoding unit 62 Latch

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/66 G11C 11/34 371A

Claims (10)

[Claims] 1. A semiconductor memory device capable of performing a test operation, comprising: a plurality of word drivers for keeping a word line active until reset when selected; and at least one of the plurality of word drivers during the test operation. A semiconductor memory device including a control circuit for sequentially selecting and simultaneously activating word lines corresponding to a selected word driver. 2. A method according to claim 1, wherein each of said plurality of word drivers includes a latch circuit for latching a selected state and activating said word line when selected, and a signal input terminal for resetting said latch circuit. The semiconductor memory device according to claim 1. 3. The control circuit supplies a timing pulse for instructing a timing for activating the word line to the plurality of word drivers, and each of the plurality of word drivers supplies a signal for instructing a corresponding row address. 3. The semiconductor memory device according to claim 2, further comprising a decoding unit that causes said latch to latch said selected state when said timing pulse is input. 4. The word line multiple selection avoidance circuit, wherein the control circuit includes a resettable word line multiple selection avoidance circuit that receives a timing signal instructing a timing for activating the word line and outputs the timing signal as the timing pulse. Outputs all the timing signals as the timing pulse during the test operation, outputs only the first timing signal as the timing pulse during normal operation other than the test operation, and thereafter outputs the timing signal until reset. 4. The semiconductor memory device according to claim 3, wherein said timing pulse is not output even if it is input. 5. The semiconductor memory device according to claim 2, wherein said signal input terminal receives a reset signal when a precharge command is input to said semiconductor memory device. 6. The semiconductor device according to claim 1, wherein said plurality of word drivers include at least one redundant word driver, and select the redundant word driver when a row address of a defective memory cell is designated. Storage device. 7. A semiconductor memory device capable of performing a test operation, comprising: a plurality of word lines; and a word line control circuit for simultaneously activating one or more of the plurality of word lines during the test operation. Semiconductor storage device. 8. The word line control circuit, comprising: a plurality of word drivers for keeping a word line active until reset when selected; and one or more of the plurality of word drivers sequentially selected during the test operation. 8. The semiconductor memory device according to claim 7, further comprising a control circuit for simultaneously activating word lines corresponding to the selected word driver. 9. A method for testing a memory cell in a semiconductor memory device, comprising: providing a latch for holding a selected state for each word driver for activating a word line; and setting a latch of at least one word driver. Selectively activating at least one word line, writing data to a memory cell corresponding to the at least one word line, resetting a latch of the at least one word driver to deactivate the at least one word line, The latches of one or more word drivers are set to simultaneously activate one or more word lines near the at least one word line, and the activation and deactivation of the one or more word lines is repeated. A step of selectively activating the at least one word line again to read data from the memory cell. how to. 10. A method for testing a memory cell in a semiconductor memory device, comprising: selectively activating at least one word line; writing data to a memory cell corresponding to the at least one word line; One or more word lines in the vicinity of one word line are simultaneously activated, the activation and deactivation of the one or more word lines are repeated, and the at least one word line is selectively activated again, and the memory is activated. A method comprising reading data from a cell.