JPH10327023A - CMOS analog amplifier circuit with refresh function - Google Patents

Abstract

(57) [Abstract] [Problem] No external refresh voltage is required,
Provided is a CMOS analog amplifier circuit with a refresh function that can execute refresh satisfactorily regardless of a bias potential at an output terminal of an amplifier stage. SOLUTION: A first switch SWA receiving an input signal is provided.
And an input capacitor Ci that receives the output of the first switch at one end.
n and a second switch SW connected in parallel to the input capacitance.
RS, an input terminal connected to the other end of the input capacitor, amplifying stages 11, 12, and 13 for amplifying and logically inverting and outputting an input signal received via the input capacitor, and outputting the output of the amplifying stage to the amplifying stage. It has a feedback capacitor Cf that feeds back to the input, and a third switch SWRT connected in parallel with the feedback capacitor, and turns off the first switch and turns on the second and third switches during refreshing. Thereby, the accumulation of the charge at the bias point 10 at the input terminal of the amplification stage can be made zero.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-speed CMOS analog amplifier circuit used for an analog integrated circuit,
In particular, the present invention relates to a CMOS analog amplifier circuit having a refresh function in which an amplification stage is constituted by an odd number of CMOS inverters and a DC bias of the amplification stage can be periodically and forcibly reset.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional example of a low power consumption type CMOS analog amplifier circuit which compensates for linear characteristics of input and output, and FIG. 5 is a circuit diagram showing each CMOS inverter of FIG. 4 in detail. It is. This CMOS analog amplifier circuit 200
Of three CMOS inverters 11, 12, 1
3 are connected in series. The signal input terminal 21 receiving the analog input signal Ain has an input capacitance Cin
, And the other end of the input capacitor Cin is connected to the input terminal of the first-stage CMOS inverter 11 at the bias point 10. The output terminal of the last-stage CMOS inverter 13 is connected to the signal output terminal 23 and to the input terminal of the first-stage CMOS inverter 11 via a feedback capacitor Cf. This CMOS analog amplifier circuit 2
The amplification factor of 00 is determined by the ratio of Cin to Cf, but in this example, the description will be made on the assumption that Cin: Cf = 1: 1.

In addition, CMOS inverters 11, 12, 1
Each of the three is composed of a P-type MOS transistor and an N-type MOS transistor, as shown in FIG.
To obtain the maximum dynamic range, the power supply voltage Vd
When d is applied, the DC output voltage becomes the power supply voltage Vdd
, That is, Vdd / 2. Therefore, the CMOS analog amplifier circuit 2 shown in FIG.
At 00, when the initial charge of the bias point 10 is zero and the power supply voltage Vdd is applied, the bias point 10
Becomes Vdd / 2. This allows the input of the amplifier stage to vary from 0 volts to Vdd volts (the output is from Vdd volts to 0 volts), so that the CMOS analog amplifier circuit 200 can obtain the maximum dynamic range.

The input terminal of the CMOS inverter at the bias point 10 is connected only to the other parts via the capacitors Cin and Cf, and has a high DC impedance. If a charge is applied or the charge is accumulated due to a long operation, the charge is not released, and when the power supply voltage Vdd is applied to the CMOS analog amplifier circuit 200, the bias point 10 deviates from Vdd / 2. It will be. Due to this shift, the range of the effective input voltage to the amplifier stage is narrower than the range from 0 volts to Vdd volts, and the CMOS analog amplifier circuit 200 cannot operate with the maximum dynamic range.

In order to solve this problem, the voltage of the bias point 10 can be periodically reset to Vdd / 2 (hereinafter, referred to as refresh) with the refresh function shown in FIG. This is a CMOS analog amplifier circuit 201. The CMOS analog amplifier circuit 201 with the refresh function is the same as the CMOS analog amplifier circuit 2 shown in FIG.
A first switch SWA (for example, a semiconductor switch) is provided between the signal input terminal 21 and the input capacitor Cin.
A refresh voltage terminal 22 for applying a refresh voltage Vref of dd / 2 volts is connected to one end of an input capacitor Cin via a second switch SWV, and a third switch SWR is connected in parallel with the feedback capacitor Cf. ing.

Next, the CMOS with the refresh function will be described.
The refresh operation of the analog amplifier circuit 201 will be described. When refreshing, C with refresh function
When the power supply voltage Vdd is supplied to the MOS analog amplifier circuit 201, the switch SWA is turned off, and the switch SWA is turned off.
R and SWV are turned on, and the refresh voltage terminal 22
To Vdd / 2. By this application, the bias point 1
Since the accumulation of the charge of 0 becomes zero, the switch SW
If R and SWV are set to OFF and the switch SWA is set to ON, the bias point 10 is set to Vdd / 2 volts, and the normal operation can be performed again.

[0007]

The CMOS analog amplifying circuit 201 with a refresh function shown in FIG. 6 has a considerable improvement over the CMOS analog amplifying circuit 200 shown in FIG. May vary due to fluctuations in the device process or the like. In this case, even if the circuit configuration shown in FIG. 6 is adopted, there is a problem that the charge accumulation at the bias point 10 cannot be made completely zero. Was. Further, providing the refresh voltage terminal 22 has a problem that, when a circuit is formed as an LSI, wiring routing is increased, and it is necessary to externally apply the refresh voltage Vref.

In view of the above-mentioned problems, the present invention does not require a refresh voltage to be applied from the outside, and a refresh function capable of executing a refresh operation well even if the potential at the output terminal of the amplifying stage changes due to a change in a device process or the like. It is an object of the present invention to provide a CMOS analog amplifier circuit provided with.

[0009]

According to a first aspect of the present invention, there is provided a first switch for receiving an input signal, an input capacitor for receiving an output of the first switch at one end, and
A second switch connected in parallel to the input capacitance, an amplification stage having an input terminal connected to the other end of the input capacitance, amplifying an input signal received via the input capacitance, logically inverting the output signal, and outputting the inverted signal; And a third switch connected in parallel with the feedback capacitor.

According to such a configuration, the CMOS analog amplifier circuit with the refresh function turns on the first switch and turns off the second and third switches during the amplifying operation. , First
Is turned off and the second and third switches are turned on so that the charge accumulation at the input terminal of the amplifying stage is appropriately reduced to zero, and the amplifying stage of the CMOS analog amplifying circuit with the refresh function during the amplifying operation. To prevent the fluctuation of the bias.

In a second aspect of the present invention, the amplification stage comprises an odd-numbered stage CMOS inverter circuit, and the odd-numbered stage C
One end of a balanced impedance composed of a pair of impedances is connected to the output of the CMOS inverter after the first stage and before the last stage of the MOS inverter, and the other end of one impedance is connected to a high-potential power supply terminal, and the other end is connected to the other impedance. The other end is connected to a low-potential power supply end.

In a third aspect of the present invention, the amplifying stage comprises an odd-numbered CMOS inverter circuit, and the odd-numbered C
The output of the last stage is negatively fed back to the input of the CMOS inverter after the first stage and before the last stage of the MOS inverter through a series circuit of a resistor and a capacitor to increase the phase margin.

According to a fourth aspect of the present invention, the first switch is turned on and the second and third switches are turned off during the amplification operation, and the first switch is turned off and the second and third switches are turned on during the refreshing operation. The automatic refreshing can be performed by adding a control means for turning on.

Further, in the fifth invention, the chip size can be reduced by integrally forming the entire structure as an integrated circuit.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing an example of a CMOS analog amplifier circuit with a refresh function according to the present invention. CMO with refresh function of Figure 1
In the S analog amplifier circuit 101, the CMOS of FIG.
The configuration is such that the second switch SWV of the analog amplifier circuit 201 is removed, and the second switch SWRS is connected in parallel to the input capacitance Cin.

That is, the CMOS analog amplifier circuit 10
One amplification stage has three CMOS inverters 11, 12,.
13 are connected in series, and the analog input signal A
signal input terminal 21 receiving the first switch SW
A is connected to one end of the input capacitor Cin via A, and the other end of the input capacitor Cin
It is connected to the input terminal of the inverter 11. Input capacitance C
The second switch SWRS is connected in parallel to in. The output terminal of the last-stage CMOS inverter 13 is connected to the signal output terminal 23 and to the input terminal of the first-stage CMOS inverter 11 via a feedback capacitor Cf. The feedback capacitance Cf has a third switch SWR.
T are connected in parallel.

During normal operation of the CMOS analog amplifier circuit 101 with refresh function, the first switch SW
A is on, and the second and third switches SWRS and SWRT are used in an off state. At the time of refreshing, the switch SWA is turned off while the power supply voltage Vdd is supplied to the CMOS analog amplifier circuit with refresh function 101.
Switches SWRS and SWRT are set to ON. Therefore, at the time of refreshing, the potentials at both ends of the input capacitor Cin and the feedback capacitor Cf become the same as the potential at the output terminal of the amplifier stage, the charge accumulation at the bias point 10 becomes zero, and the device is refreshed. Therefore, the switch SWR
If S and SWRT are set to OFF and the switch SWA is set to ON, the normal operation in which the bias point 10 is set to the output terminal bias voltage (normally Vdd / 2 volts) can be resumed.

As is clear from the above description, the CMOS analog amplifier circuit 101 having a refresh function shown in FIG.
Is externally applied to the refresh voltage Vre like the CMOS analog amplifier circuit 201 having the refresh function in FIG.
There is no need to apply f, and wiring can be easily routed. In addition, even if the potential of the output terminal deviates from Vdd / 2, the charge at the bias point 10 can be made completely zero,
Consequently, the CMOS analog amplifier circuit 101 can operate with the maximum dynamic range.

Embodiment 2 FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The CMOS analog amplifier circuit 102 with a refresh function shown in FIG.
The power supply terminal Vdd (high potential) and the power supply terminal Vss (low potential) are connected to the output terminal of the MOS inverter 12 respectively.
1 is a circuit obtained by adding a balanced impedance, which is a series circuit of a resistor R and a capacitor C, connected to the circuit of FIG. This balanced impedance is provided to suppress the gain of the CMOS inverter 12 and suppress high-frequency components, but does not increase power consumption because no DC current flows. Even in the case of such a circuit, accumulation of charge at the bias point 10 poses a problem, so that the configuration shown in FIG. 2 by applying the present invention is effective. The operation in this case is the same as that of the circuit of FIG.

Embodiment 3 FIG. 3 is a circuit diagram showing a third embodiment of the present invention. The CMOS analog amplifier circuit 103 with a refresh function shown in FIG. 3 is a CMOS inverter 1 of the circuit shown in FIG.
3 is connected between the input and output. This series circuit
A negative feedback circuit for the CMOS inverter 13 suppresses the gain of the CMOS inverter 13 and also suppresses the gain of the entire circuit. Even in the case of such a circuit, accumulation of the charge at the bias point 10 becomes a problem, so that applying the refresh method of the present invention is effective. In the above description of the circuit example, three CMOS inverters are used as the amplification stages. However, any number of odd-numbered stages may be used. Further, these circuits are preferably integrated as an integrated circuit (for example, an LSI).

[0021]

As described in detail above, the CMOS analog amplifier circuit with refresh function according to the first invention has a first switch for receiving an input signal and an input capacitor for receiving an output of the first switch at one end. A second switch connected in parallel with the input capacitor, an input stage connected to the other end of the input capacitor, an amplification stage for amplifying an input signal received via the input capacitor, logically inverting the input signal, and outputting the inverted signal; It has a feedback capacitor that feeds back the output of the amplifier stage to the input of the amplifier stage, and a third switch connected in parallel with the feedback capacitor.
The first switch is turned on and the second and third switches are turned off. At the time of refreshing, the first switch is turned off, and the second and third switches are turned on, so that the refresh voltage is externally applied. It is not necessary to apply the voltage from the terminal, the wiring is simplified, and even if the potential of the output terminal of the amplifier stage changes due to a variation in device process or the like, the charge accumulation at the input terminal of the amplifier stage can be made zero. Therefore, there is an effect that the refresh operation can be performed well and the amplification operation can be performed with the maximum dynamic range.

Further, in the CMOS analog amplifier with refresh function according to the second aspect of the present invention, since the amplifying stage is constituted by an odd number of CMOS inverter circuits, a multistage amplifier can be constituted by a simple circuit. It is easy to apply negative feedback, and one end of a balanced impedance composed of a pair of impedances is connected to the output of the CMOS inverter after the first stage and before the last stage of the odd-numbered stage CMOS inverter, The other end is connected to the high-potential power supply end, and the other end of the other impedance is connected to the low-potential power supply end, and performs stable amplification with the maximum dynamic range in coordination with the gain adjustment by the balanced impedance. There is an effect that can be.

Further, in the CMOS analog amplifier with refresh function according to the third invention, the amplifying stage is constituted by an odd-numbered CMOS inverter circuit, and the odd-numbered CMOS inverter is arranged after the first stage and after the last stage. Since the output of the last stage is negatively fed back to the input of the previous CMOS inverter through a series circuit of a resistor and a capacitor, the maximum dynamic range is obtained in cooperation with the stabilization of the negative feedback of the last stage. There is an effect that the amplification operation can be executed stably.

Further, the CMOS analog amplifier circuit with refresh function according to the fourth aspect of the present invention provides
The first switch is turned on, the second and third switches are turned off, and at the time of refreshing, the first switch is turned off,
Since the control means for turning on the second and third switches is added, it is possible to automatically perform refresh.

The CMOS analog amplifier circuit with refresh function according to the fifth aspect of the present invention can be easily handled by integrally forming the whole as an integrated circuit, and the chip size can be set to a small size in advance.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a CMOS analog amplifier circuit with a refresh function according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a power-saving CMOS that compensates for linear characteristics of input and output.
FIG. 9 is a circuit diagram illustrating a conventional example of an analog amplifier circuit.

FIG. 5 is a circuit diagram showing each CMOS inverter of FIG. 4 in detail.

FIG. 6 is a circuit diagram showing a conventional example of a CMOS analog amplifier circuit with a refresh function.

[Explanation of symbols]

Reference Signs List 10 bias point 11, 12, 13 CMOS inverter 21 signal input terminal 23 signal output terminal 101, 102, 103 CM with refresh function
OS analog amplifier circuit Cin input capacitance Cf feedback capacitance SWA first switch SWRS second switch SWRT third switch

Continuing on the front page (72) Inventor Hiroshi Higuchi 64 Naganonuma, Tenno-cho, Tenno-cho, Minamiakita-gun, Akita Prefecture Inside Akita Electronics Co., Ltd. (72) Inventor Kotobuki Kokuryo 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Takayamanai Co., Ltd.

Claims (5)

[Claims] A first switch for receiving an input signal; an input capacitor for receiving an output of the first switch at one end; a second switch connected in parallel to the input capacitor; An amplification stage connected to the other end of the capacitance, for amplifying and logically inverting and outputting an input signal received via the input capacitance, and a feedback capacitance for returning an output of the amplification stage to an input of the amplification stage; A CMOS analog amplifier circuit with a refresh function, comprising: a third switch connected in parallel to a feedback capacitor. 2. A refresh function-equipped C according to claim 1,
In the MOS analog amplifier circuit, the amplification stage is constituted by an odd-numbered stage CMOS inverter circuit, and a balanced impedance including a pair of impedances is provided to an output of the CMOS inverter after the first stage and before the last stage among the odd-stage CMOS inverters. The other end of one impedance is connected to a high-potential power supply terminal, and the other end of the other impedance is connected to a low-potential power supply terminal. 3. The refresh function-equipped C according to claim 1,
In the MOS analog amplifying circuit, the amplifying stage is constituted by an odd-numbered stage CMOS inverter circuit, and an output of a last-stage CMOS inverter is provided in response to an input of a CMOS inverter after the first stage and before the last stage among the odd-numbered CMOS inverters. A CMOS analog amplifier circuit with a refresh function that provides negative feedback through a series circuit of a resistor and a capacitor. 4. The CMOS analog amplifier circuit with a refresh function according to claim 1, wherein said first switch is turned on and said second switch is turned on during an amplification operation.
A CMOS analog amplifier circuit with a refresh function, further comprising control means for turning off the third switch and turning off the first switch and turning on the second and third switches at the time of refreshing. 5. The CMOS analog amplifier with refresh function according to claim 1, wherein the whole of the CMOS analog amplifier with refresh function is integrally formed as an integrated circuit.