JPH10326892A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen an alignment margin between contact holes and element isolation regions and to enhance the degree of integration of a circuit by a method wherein gate electrodes consisting of the same material and a dummy gate are arranged on the element isolation insulating films, and an insulating film consisting of a material different from that for an interlayer insulating film is formed on the side surfaces of those gate electrodes and the dummy gate. SOLUTION: A semiconductor device is provided with normal gate electrodes 4A, wiring layers 4B formed using a gate layer, and a dummy gate 4C which does not function either as the electrodes 4A or the wring layers 4B. That is, the gate 4C is provided in such a way as to cover each one part of element isolation insulating films 2, which are respectively provided on the outside of each end part of diffused layers 5 of the region, where the gate wiring layers 4B covering the outside of each end part of these diffused layers 5 at the places of contact holes 7 and each end part of the layers 5 do not exist. Moreover, an insulating film 6, consisting of a silicon nitride film of a material different from that for an interlayer insulating film 8, is formed on the side surfaces of the electrodes 4A and the gate 4C. As a result, an alignment margin between the holes 7 and the element isolation regions 2 can be reduced, and the degree of integration of a circuit can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art The device dimensions of integrated circuits have been miniaturized by reducing the minimum resolution of lithography. However, there has been a tendency that the improvement in alignment accuracy of lithography cannot keep up with the reduction of the minimum resolution. is there. For this reason,
There is a general problem that a distance margin (alignment margin) for alignment needs to be relatively large with respect to the resolution size, and the element size cannot be reduced in proportion to the resolution size. . For example, MIS (Metal Insulator Se
A semiconductor (FET) (Field Effect Transistor) has achieved high performance by reducing the area of the source / drain region by miniaturizing the gate length. However, the contact hole and the end of the diffusion layer, or the contact hole. The distance from the gate must be increased by the amount of misalignment expected to occur, and the area of the source / drain region is not reduced so as to be proportional to the gate length. For this reason, there are problems that the improvement in the degree of integration is limited and the parasitic capacitance of the source / drain is not reduced.

In order to cope with the above problem, a self-aligned contact formation technique, that is, a contact hole is formed in a conductor portion (substrate or gate) other than a desired diffusion layer even if displacement occurs.
Techniques that can prevent the contact with the substrate have been conventionally proposed.

FIGS. 3 and 4 are views for explaining the self-aligned contact formation technique as described above, and the technique will be described below with reference to FIGS. 3 and 4. FIG.

In a self-aligned contact, an insulating film for protecting the upper and side surfaces of the gate (gate side wall 1 in FIG. 4)
06 (silicon nitride film) and the protective insulating film 110 (silicon nitride film) or the gate side wall 106 ′ (silicon oxide film) and the protective insulating film 110 ′ (silicon oxide film) in FIG. This is realized by preventing the wiring that fills the contact hole 107 from remaining in contact with a part other than the desired diffusion layer 105 even if it is etched when the contact hole 107 is opened.

FIG. 3 shows a first conventional example for leaving the above-mentioned insulating film, for example, Japanese Patent Laid-Open No. 60-19457.
FIG. 2 is a diagram for explaining a method of utilizing a step disclosed in page 0 of Japanese Patent Publication No. 372 and FIG. 1. In the method shown in FIG. 3, not only the gate electrode layer 104 but also the element isolation insulating film 111 is formed so as to protrude above the semiconductor substrate 101, and a relatively thin interlayer insulating film 108 is formed thereon so as not to flatten a step. '.

FIG. 3A shows a state immediately after the interlayer insulating film 108 'is deposited. From this state, using the resist or the like as a mask, the contact hole 1 is formed by the thickness of the interlayer insulating film 108 '.
FIG. 3B shows a state after the etching for opening 07 is performed. The contact hole 107 is the gate electrode 10
4 and the diffusion layer 105 are exposed by etching only for the thickness of the element isolation insulating film 108 '. However, at this time, the protective insulating film 110 ′, the gate side wall 106 ′, and the element isolation insulating film 111 in the portion overlapping with the contact hole 107 are not yet eroded, so that the contact hole 107 is opened only on the desired diffusion layer 105. You.

Next, a method according to a second conventional example for leaving an insulating film will be described with reference to FIG.

The method according to the second prior art uses the gate side wall 1.
06, protective insulating film 110, and element isolation insulating film 111
Is made of a material different from the interlayer insulating film 108 (usually a silicon oxide film), for example, a silicon nitride film, and the opening of the contact hole 107 is performed under the condition that the former etching rate is faster than the latter, and the etching selectivity is utilized. How to The insulating film to be left is etched, but is not removed due to the low etching rate, and finally remains.
In this case, a flat and thick interlayer film 108 can be provided as shown in FIG.

[0010]

By using the conventional self-aligned contact method described above, it is possible to reduce the alignment margin, but the number of processes is increased. In order to reduce the alignment margin with respect to the gate, it is necessary to cover the upper part of the gate with a protective insulating film. Therefore, an extra lithography step is required to form a contact with the gate electrode, and the number of manufacturing steps increases. .

Further, in a dual gate system using an n ⁺ -type gate for an n-type FET and a p ⁺ -type gate for a p-type FET, the doping of the polysilicon gate is realized by ion implantation simultaneously with the doping between the source and the drain. However, it is desirable to reduce the number of steps. However, when the above-described protective film is formed, the penetration of the ion-implanted particles into the gate electrode is prevented, so that it is difficult to realize the polysilicon gate doping by ion implantation simultaneously with the source-drain doping. There is a problem.

In order to reduce the alignment margin for element isolation, it is necessary to protrude the element isolation insulating film upward or to form the element isolation insulating film using a material different from usual (such as a silicon nitride film). However, the LOCOS method or the trench isolation method in which an oxide film is buried cannot be used for such a formation, and it is necessary to develop a new element isolation method. Further, there is a problem that the presence of the step makes it difficult to perform lithography in a subsequent gate electrode forming step.

The above-described problems occur not only in the MIS type FET but also in a semiconductor device configured by a similar method.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned various problems of the prior art, and a contact and an element required to prevent a short circuit by a conventionally used process. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can reduce a margin for alignment between separation and separation, thereby improving the degree of circuit integration and reducing the diffusion layer area.

[0015]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises an element isolation insulating film, a gate electrode, a diffusion layer, an interlayer insulating film covering these elements, A semiconductor device having a contact hole that is opened to reach the diffusion layer, the semiconductor device having a dummy gate formed on the element isolation insulating film and formed of the same material as a gate electrode; Is characterized in that an insulating film of a material different from that of the interlayer insulating film is formed on the side surface of the substrate.

In this case, the dummy gate is a portion where the contact hole and the end of the diffusion layer are close to each other, and a region where the wiring layer covering the outside of the diffusion layer does not exist is provided on the element isolation provided outside the diffusion layer. The insulating film that covers at least a part of the insulating film and that is formed on a side surface thereof may be provided at a position overlapping with an end of the diffusion layer.

Further, the dummy gate may be formed such that its end coincides with the end of the element isolation film.

In any of the above cases, the insulating film formed on the side surfaces of the gate electrode and the dummy gate may be a silicon nitride film, and the interlayer insulating film may be a silicon oxide film.

According to the method of manufacturing a semiconductor device of the present invention, there are provided an element isolation insulating film, a gate electrode, a diffusion layer, an interlayer insulating film covering these, a contact hole opened in the interlayer insulating film and reaching the diffusion layer. And a step of forming a dummy gate disposed on the element isolation insulating film and formed of the same material as the gate electrode at the same time as the gate electrode.

In this case, a step of depositing an insulating film with a first material, a step of anisotropically etching back the insulating film, a step of depositing an interlayer insulating film with a second material, 1
Forming a contact hole under an etching condition in which the etching rate of the material is lower than the etching rate of the second material.

In the semiconductor device of the present invention configured as described above, the element isolation insulating film is not etched away by the insulating film formed on the side surface of the dummy gate, and no short circuit occurs. .

Also, by forming at the above-mentioned position,
The required alignment margin is also small. This is because, in the manufacture of a semiconductor device, first, an element isolation insulating film is formed, and then a gate insulating film and a gate electrode are formed in accordance with the element isolation insulating film. Form contact holes. Therefore, the misalignment amount △ between the element isolation insulating film and the contact hole is
Using the misregistration amount Δ1 between the element isolation insulating film 2 and the gate electrode 4 and the misalignment amount Δ2 between the gate electrode 4 and the contact hole 7, Δ = | △ 1 + △ 2 | It is expressed as

Assuming that the width of the insulating film (side wall) formed on the side surface of the gate electrode is M1 and the margin of alignment between the gate electrode and the contact hole is M2, | △ 1 | <M1 and | △ 2 | < No short circuit occurs at M2.

In the present invention, since the element isolation insulating film is not removed by etching, it is only necessary to independently suppress the positional deviation for one process to a predetermined value M1 or less and M2 or less, respectively. Margin M for positioning the sum of
As compared with the conventional method that needs to be suppressed to the following, a defect due to misalignment is less likely to occur.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a MIS type F manufactured according to the present invention.
FIG. 4 is a diagram illustrating a configuration of an embodiment of an ET, and illustrates contact holes 7;
FIG. 4 is a view showing a structure immediately after opening a hole. FIG. 2 is a diagram showing a conventional structure as a comparative example, and FIGS.
(A) is a top view when there is no misalignment, (B) is a cross-sectional view when there is no misalignment, and (C) is a cross-sectional view when there is misalignment. Here, the MIS is formed by the gate electrode 4A and the diffusion layer 5.
A type FET is configured.

In this embodiment shown in FIG. 1, a dummy gate 4C which does not function as any of them is provided in addition to the normal gate electrode 4A and the wiring 4B using the gate layer. Even if the dummy gate 4C is electrically isolated,
Although any potential may be applied, in order to apply a potential to the dummy gate 4C, it is necessary to connect the dummy gate 4C to a wiring for supplying a potential, and an extra area for arranging the wiring and the contact hole is required. Is required. Therefore, it is preferable to make the dummy gate 4C electrically isolated, since it is easy to realize.

The dummy gate 4C is a place where the contact hole 7 and the end of the diffusion layer 5 are close to each other and there is a risk of contact due to displacement, and the gate wiring layer 4B covering the outside of the end of the diffusion layer 5 is In a non-existent region, the diffusion layer 5 is provided so as to cover at least a part of the element isolation insulating film 2 provided outside the end of the diffusion layer 5. At this time, the position is determined so that the gate side wall 6 of the dummy gate 4C overlaps with the end of the diffusion layer 5. The most desirable arrangement for maximizing the effect of the present invention is to make the end of the dummy gate 4C coincide with the element isolation end 9 as shown in FIG. Further, a silicon nitride film is used as a material of the side wall 6 of the gate, and a silicon oxide film is used as a material of the interlayer film 8. By selecting the material in this manner, it is possible to prevent the gate side wall 6 from being removed at the time of etching when opening the contact hole 7.

When the gate wiring layer 4B is present, the gate wiring 4B is arranged such that the positional relationship between the end of the diffusion layer 5 and the gate wiring layer 4B is the same as when the dummy gate 4C is arranged. Adjust the width and position of. As a result, the gate wiring layer 4B also becomes a dummy gate 4C described below.
It has the same effect as the function.

In the embodiment of the present invention configured as described above, a defect due to misalignment is unlikely to occur. This will be described with reference to FIGS. 1B and 1C and FIGS. 2B and 2C. The gate electrode 4 in the following description is the same as the gate electrode 4 described above.
A, a wiring 4B and a dummy gate 4C.

Usually, in the manufacture of a MIS type FET,
First, the element isolation insulating film 2 is formed, and then the gate electrode 4 is formed in alignment with the pattern of the element isolation insulating film 2, and then the contact hole 7 is formed in alignment with the gate electrode 4. . Therefore, the misregistration amount △ between the element isolation insulating film 2 and the contact hole 7 is determined by the misalignment amount △ 1 between the element isolation insulating film 2 and the gate electrode 4, and the gate electrode 4 and the contact hole 7. Δ = | △ 1 + △ 2 | is expressed by using the positional deviation amount △ 2 between

In the case of the comparative example shown in FIG. 2, assuming that the alignment margin between the element isolation end 9 and the contact hole 7 is M, the condition under which a short circuit does not occur is Δ = | △ 1 + △ 2 | <M. On the other hand, in the present embodiment shown in FIG. 1, the width of the gate side wall 6 is M1, the gate electrode 4 is
| △ 1 | <M1, and | △ 2 | <M2, where M2 is the alignment margin with respect to. In a fine MIS type FET using a size of 0.25 μm or less, typically, M, M1, and M2 are the same size, that is, 0.05 to 0.2 μm. In the conventional method, it is necessary to suppress the sum of the two positional deviations to be equal to or less than the alignment margin M, but according to the present embodiment, it is only necessary to independently suppress the positional deviation for one time to the predetermined values M1 and M2 or less. In this embodiment, a defect due to misalignment is less likely to occur. This is illustrated in FIG.
This will be described in more detail with reference to FIG.

FIGS. 1 (C) and 2 (C) show an example of a situation where a position shift occurs between the embodiment according to the present invention and the comparative example. Both are plotted on the assumption that the same positional deviation has occurred. Considering the position of the gate as a reference, the element isolation insulating film 2 moves to the left and the contact 7 moves to the right.
The two components are displaced in a direction approaching each other, and therefore, the positions of the element isolation insulating film 2 and the contact holes 7 overlap each other. It is stochastic whether the orientations of the two displacements are the same or opposite, but FIG.
The situation shown in FIG. 2C and FIG. 2C is the worst case in which a short circuit between the diffusion layer 5 and the semiconductor substrate 1 is assumed. At this time, in the comparative example shown in FIG. 2C, the contact hole 7A is in contact with the element isolation insulating film 2, and a short-circuit failure portion 20 is formed during etching for forming the contact hole, and the contact hole 7A is Is short-circuited.

On the other hand, in the case of this embodiment shown in FIG. 1C, the contact hole 7A and the element isolation insulating film 2 overlap with each other due to displacement, but the etching for forming the contact hole by the gate side wall 6A is not performed. Since this is prevented, the element isolation insulating film 2 is not etched. Thus, in the comparative example, even in a situation where a failure due to a short circuit occurs, the failure does not occur in the case of the present embodiment.
FIG. 2 shows a case where an oxide film having no etching selectivity is used as the gate side wall 6A. However, even if this is changed to a material (such as a silicon nitride film) having a selectivity with respect to contact etching, the result is still lower. The same is true.

Further, by aligning both the gate electrode 4 and the contact hole 7 with respect to the element isolation insulating film 2, contact between the element isolation insulating film 2 and the contact hole 7 can be suppressed. However, in this case, there is a new problem that the displacement between the gate electrode 4 and the contact hole 7 becomes large. In the present invention, it is sufficient that the contact hole 7 is positioned with respect to the gate electrode 4 as in the normal case, and the possibility of contact between the gate electrode 4 and the contact hole 7 does not increase as compared with the conventional case.

Next, a method of manufacturing a semiconductor device according to the present invention will be described. Until immediately before the gate electrode 4 is formed, a normal MI
This is similar to the manufacture of the S-type FET. Next, the gate electrode layer is processed so as to have a pattern including the dummy gate 4C in addition to the normal gate electrode 4A and the wiring 4B. Here, it is not necessary to form an insulating film on the gate electrode layer pattern required in the conventional self-aligned contact process.
This step can be realized by simply adding the data of the dummy gate 4C to the mask pattern data for lithography,
No new processes need to be added.

After forming the pattern of the gate electrode layer, a silicon nitride film is deposited on the entire surface of the substrate by the CVD method, and subsequently, the silicon nitride film is etched back by anisotropic dry etching except for the side wall portions. As a result, the side wall 6 made of the silicon nitride film is formed on the side surface of the gate electrode layer pattern. Subsequently, a diffusion layer 5 serving as a source / drain region is formed by ion implantation, an interlayer insulating film 8 made of a silicon oxide film is deposited, and a contact hole 7 is opened. In the etching for opening the contact hole 7,
The etching is performed under the condition that the etching rate of the silicon oxide film is sufficiently higher than that of the silicon nitride film. Finally, a metal wiring is formed to complete the MIS FET.

As described above, the semiconductor device according to the present invention can be manufactured without additional steps as compared with the related art. Here, the single drain structure in which the source / drain region is formed by one ion implantation has been described as an example, but the source / drain is formed in two stages by performing ion implantation even before the gate sidewall 6 is formed. , A so-called LDD structure.

In the above description, a silicon nitride film is assumed as the side wall 6 of the gate and a silicon oxide film is assumed as the interlayer insulating film 8. However, if the latter is a combination of materials capable of sufficiently increasing the etching rate as compared with the former, other materials may be used. Combinations may be used. Further, a thin insulating film (such as a silicon oxide film) having no etching selectivity may be interposed between the gate electrode 4 and the gate side wall 6 for the purpose of improving adhesiveness or relieving mechanical stress. .

[0040]

According to the present invention, the positional deviation | △ 1 | between the element isolation insulating film and the gate electrode and the positional deviation | △ 2 | between the gate electrode and the contact hole are independently determined. It is only necessary to keep it below the required value.
Compared with the conventional structure in which 1 + △ 2 | is problematic, it is possible to reduce the margin for positioning between the end of the diffusion layer and the contact hole. This increases the degree of integration, MIS
It is possible to reduce the diffusion layer capacitance of the type FET.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a configuration of an embodiment of a MIS type FET manufactured according to the present invention, in which FIG. 1A is a top view when there is no misalignment, and FIG. FIG. 7C is a cross-sectional view when there is misalignment.

FIG. 2 is a diagram showing a conventional structure as a comparative example, in which (A) is a top view when there is no misalignment,
(B) is a cross-sectional view when there is no misalignment, and (C) is a cross-sectional view when there is misalignment.

FIG. 3 is a diagram for explaining a self-aligned contact formation technique.

FIG. 4 is a diagram for explaining a self-aligned contact formation technique.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 element isolation insulating film 3 gate insulating film 4 gate electrode layer 4A gate electrode 4B wiring by gate electrode layer 4C dummy gate 5 diffusion layer 6 gate side wall (silicon nitride film) 6 'gate side wall (silicon oxide film) 7 contact Hole 7A Contact hole overlapping element isolation 8 Interlayer insulation film 9 Element isolation end 10 Protective insulation film (silicon nitride film) 10 'Protective insulation film (silicon oxide film) 11 Element isolation insulation film 20 Short-circuit defect

Claims (6)

[Claims] 1. A semiconductor device having an element isolation insulating film, a gate electrode, a diffusion layer, an interlayer insulating film covering them, and a contact hole opened in the interlayer insulating film and reaching the diffusion layer, A dummy gate is formed on the element isolation insulating film and formed of the same material as the gate electrode, and an insulating film of a material different from the interlayer insulating film is formed on side surfaces of the gate electrode and the dummy gate. A semiconductor device characterized in that: 2. The semiconductor device according to claim 1, wherein the dummy gate is located at a position where the contact hole and the end of the diffusion layer are close to each other, and where the wiring layer covering the outside of the diffusion layer does not exist. A semiconductor device which covers at least a part of an element isolation insulating film provided outside the semiconductor device, and an insulating film formed on a side surface thereof is provided at a position overlapping with an end of the diffusion layer. 3. The semiconductor device according to claim 2, wherein the dummy gate is formed such that an end thereof coincides with an end of the element isolation film. 4. The semiconductor device according to claim 1, wherein the insulating film formed on the side surfaces of the gate electrode and the dummy gate is a silicon nitride film, and the interlayer insulating film is a silicon oxide film. A semiconductor device, characterized in that: 5. Manufacturing of a semiconductor device having an element isolation insulating film, a gate electrode, a diffusion layer, an interlayer insulating film covering them, and a contact hole opened in the interlayer insulating film and reaching the diffusion layer. A method of manufacturing a semiconductor device, comprising: forming a dummy gate, which is formed on the element isolation insulating film and is made of the same material as a gate electrode, simultaneously with the gate electrode. 6. The method for manufacturing a semiconductor device according to claim 5, wherein: a step of depositing an insulating film with a first material; a step of anisotropically etching back the insulating film; 2. A method of manufacturing a semiconductor device, comprising: a step of depositing a second material; and a step of opening a contact hole under an etching condition in which an etching rate of the first material is lower than an etching rate of the second material. .