JPH10322604A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To vary the end of accumulation time by starting accumulation in synchronizing with a trigger signal from the outside and accumulating charge only in a period which is set by a shutter speed setting signal. SOLUTION: When the trigger signal is applied from an input terminal 4 at a restart reset mode, a vertical synchronizing signal is generated by a sync generator 5 in synchronizing with the signal. When the trigger signals are supplied to the sinc generator 5 and a timing circuit 6 from the input terminal 4 at a real shutter mode, a narrow shutter pulse is generated from the timing circuit 6 for CCD 1 in synchronizing with the trigger signal. Thus, the end of accumulation time is changed by delaying the vertical synchronizing signal for prescribed time at the real shutter mode. Thus, an electronic shutter which starts exposure when the trigger signal is inputted and changes shutter speed with the change of the end of exposure time is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CCD (charge c)
oupled device) to obtain an electronic shutter with a long exposure by varying the effective accumulation time of a solid-state imaging device, such as an image processing device that is not assumed to be viewed by humans. And a solid-state imaging device such as a CCD camera.

[0002]

2. Description of the Related Art Hitherto, Japanese Patent Application No. 61-252375 has been proposed as a solid-state imaging device capable of electrically controlling an exposure time without using a mechanical shutter.

An electronic shutter using such a solid-state image pickup device changes the time during which electric charges are accumulated in a sensor of a solid-state image pickup device (hereinafter referred to as CCD). Is transferred from the sensor to the vertical register. In other words, the time from when the shutter pulse stops until the next sensor gate pulse enters is the shutter exposure time, and this exposure time is changed.

FIG. 7 shows a timing chart of the above relationship. The sensor gate pulse shown in FIG. 7C is output in synchronization with the vertical synchronizing signal (VD) shown in FIG. 7A. The accumulated electric charge is transferred from the sensor to the vertical register by receiving the sensor gate pulse. The shutter pulse in FIGS. 7D and 7E is input for each horizontal synchronization signal (HD) in FIG. 7B.
Discarded in the OFD (overflow drain) of the CD.

[0005] During the accumulation time, the generation of the shutter pulse is stopped. Therefore, 1/1500 second is 1/1
The generation of the shutter pulse stops longer than 000 seconds.

Here, in FIG. 7, 1/500 second and 1
Looking at the shutter speed of / 1000 seconds, it can be seen that the end of the accumulation time is constant and the shutter speed is changed by changing the start timing of the accumulation time.

The exposure time of a CCD camera or the like is usually 1/30 sec for frame accumulation and 1/6 for field accumulation.
0 sec, 1/100 to 1 as an electronic shutter
/ 10000 sec, which are based on the television standard (EIA).

[0008]

In the case of the conventional solid-state imaging device as described above, the end of the accumulation time is fixed and the time of the start of the accumulation is changed. At the beginning, there is a problem that the subject does not exist, which is not preferable. In a still camera or the like, the shutter speed is determined by changing the end of exposure, and from such a point, the accumulation time of the shutter is determined. It's more natural to change the time to finish,
This is particularly desired in machine vision.

In a machine vision or the like, since the system may be rearranged, the accumulation start time is fixed, that is, the time from the start of the trigger signal supply to the end of the accumulation time. That is, it is convenient if the effective accumulation time can be externally controlled.

As a method of changing the end of the storage time, it is conceivable to use a frame interline transfer type CCD which is intermediate between the interline transfer type and the frame transfer type. Has the disadvantage of being expensive.

Further, in machine vision or the like, 1/30 sec.
There is often a requirement that a long exposure of c or more is required, but there is a problem that such a requirement cannot be met because there is no exposure longer than 1/30 sec at a conventional shutter speed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has an interline transfer capable of keeping the start of the accumulation time constant, changing the end of the accumulation time to change the shutter speed, and performing long-time exposure. An object of the present invention is to provide a CCD camera which can be applied to any system such as a system or a frame transfer system.

[0013]

According to the present invention, there is provided a solid-state imaging device comprising: a solid-state imaging device; trigger input means for externally inputting a trigger signal having a predetermined pulse width; The solid-state imaging device starts accumulating the effective charge of the imaging device, ends the accumulation of the effective charge of the solid-state imaging device at a timing based on the trailing end of the pulse of the trigger signal, and sets the pulse width of the trigger signal to the effective accumulation period. And a driving means for driving the solid-state imaging device.

According to the present invention, the accumulation of electric charge is started in synchronization with an external trigger signal, and the electric charge is accumulated only for a period set by the shutter speed setting signal. Thus, the end of the accumulation time (exposure time) can be changed according to the shutter speed, and the effective accumulation period can be controlled by the pulse width of the trigger signal supplied from outside the CCD camera. Therefore, in a machine vision or the like, the user of the CCD camera can easily control the effective accumulation time only by setting the pulse width of the external trigger signal. Further, it is possible to obtain a CCD camera (solid-state imaging device) capable of performing long-time exposure with a shutter time of 1/30 sec or more.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a system diagram showing the overall configuration of the present invention.

In FIG. 1, 1 is a solid-state image sensor such as a CCD, 2 is a processor for processing an image signal from the CCD 1, 3 is an output terminal, 4 is an input terminal to which a trigger signal is applied, 5 is a sink generator, 6 is a timing circuit.

The sync generator 5 generates a composite synchronization signal to the processor 2 and generates a vertical synchronization signal and a horizontal synchronization signal to the timing circuit 6. Timing circuit 6
Generates a clamp pulse and a sampling pulse for the processor 2, and generates a drive pulse, a sensor gate pulse, and a shutter pulse for the CCD 6.

In the present invention, as will be described later in detail, when a trigger signal is input, a restart reset mode in which a vertical synchronizing signal VD is generated in synchronization with the trigger signal, and the start of an exposure time (accumulation time) is fixed and ended. Can be selected between a real shutter mode in which the exposure time can be varied and a long exposure mode in which long exposure can be performed.

In the restart reset mode, the input terminal 4
2A, a vertical synchronizing signal (VD) as shown in FIG. 2B is generated by the sync generator 5 in synchronization with the application of the trigger signal as shown in FIG.

In the real shutter mode, when a trigger signal as shown in FIG. 3A is supplied from the input terminal 4 to the sync generator 5 and the timing circuit 6, the timing circuit 6 applies a signal to the CCD 1 as shown in FIGS. An extremely narrow shutter pulse is generated in synchronization with the trigger signal.

This narrow shutter pulse indicates the start of the accumulation time (exposure time). In addition, sync generator 5
After a predetermined time delay from the trigger signal,
As shown in E, a vertical synchronization signal (VD) is generated for the timing circuit 6.

Then, a sensor gate pulse as shown in FIGS. 3C and 3F is generated from the timing circuit 6 to the CCD 1 in synchronization with the vertical synchronizing signal. The generation of this sensor gate pulse indicates the end of the accumulation time (exposure time).

In the above-described restart reset mode, when a trigger signal is input, a vertical synchronizing signal is immediately generated in synchronization with the trigger signal. In the real shutter mode, however, the vertical synchronizing signal is delayed by a predetermined time so that the accumulation time (exposure time) is increased. The end of time) is changing. This enables an electronic shutter that starts exposure after a trigger signal is input and changes the shutter speed according to a change in the end of the exposure time.

In the long exposure mode, a vertical synchronizing signal is generated in synchronization with the falling and rising of the trigger signal as shown in FIG. Is masked as shown in FIG. 4B. As a result, the exposure time is substantially the time from the fall of the trigger signal to the rise of the trigger signal, so that long-time exposure is possible.

FIG. 5 shows an example of a specific circuit configuration of the sync generator 5. In FIG. 5, reference numeral 10 denotes 14.31818 MHz (4
f _SC ) is an input terminal to which a clock signal is supplied, and 11 is a counter which counts 455 clock signals from the input terminal 10 and outputs the counted signal.
A double H-rate signal (2f _H ) of 31.47 kHz is obtained.

When the counter 11 counts 455, it is reset by the output signal. Reference numeral 12 denotes a １ ／ frequency divider, which divides the output of the counter 11 by 、 and outputs an H rate of 15.73 kHz to its output side.
Obtain a signal of z (f _H ).

The signal obtained in this manner is supplied to a waveform shaping circuit 13 where the signal is shaped, and is output to an output terminal 14 as a horizontal synchronizing signal. Its H rate is about 6.7μ
sec.

Reference numeral 15 denotes an output signal from the counter 11
A counter that counts five and obtains a substantially vertical synchronizing signal interlaced at its output. The V rate has a pulse width of about 572 μsec. In addition,
When the counter 15 counts 525, the counter 15 is reset by the output signal.

Reference numeral 18 denotes an input terminal to which a trigger signal is applied. The input terminal 18 is connected to a contact a of a switch circuit 20 via a differentiating circuit 19 which generates a differential pulse at the falling and rising of the trigger signal. Direct switch circuit 2 with
It is connected to a contact b of the switch circuit 20 via a variable delay circuit 21 whose delay amount is determined by a shutter speed setting signal. Switch circuit 2
A common terminal (output terminal) of 0 is connected to one input terminal of the AND circuits 22 and 23.

The input terminal 18 is connected to a contact a of a switch circuit 25 via an inverter circuit 24, and the contacts b and c of the switch circuit 25 are commonly connected and grounded.
The common terminal (output terminal) of the switch circuit 25 is the OR circuit 2
6 and one input terminal of the OR circuit 26 and the other input terminal of the AND circuit 22 are connected to the output side of the counter 15.

The output terminal of the OR circuit 26 is an AND circuit 2
3 is connected to the other input terminal, and the output terminal of the AND circuit 23 is connected to the output terminal 17 via the waveform shaping circuit 16.

The switch circuits 20 and 25 are switched by a mode switching signal.
Side, the contact b side in the restart reset mode, and the contact c side in the real shutter mode.

In the restart reset mode, the common terminal of the switch circuit 25 is grounded via the contact b, and the common terminal of the switch circuit 20 is connected to the contact b. When a trigger signal (FIG. 2A) is supplied from the input terminal 18,
This trigger signal passes through the contact b side of the switch circuit 20, and
The waveform is shaped by the waveform shaping circuit 16 through the AND circuit 23 and output as a vertical synchronization signal as shown in FIG. 2B.

The trigger signal passes through the contact b of the switch circuit 20 and resets the counter 15 as a reset signal via the AND circuit 22. The counter 15 starts counting the output signal of the counter 11 again from the time of resetting, and generates an output at the time of counting 525, and outputs the output through the OR circuit 26 and the AND circuit 23.
6 and a desired vertical synchronization signal is sequentially extracted at predetermined intervals from the vertical synchronization signal generated at the output terminal 17 as a vertical synchronization signal.

In the real shutter mode, the common terminal of the switch circuit 25 is also grounded via the contact c, and
The common terminal of the switch circuit 20 is connected to the contact c.
When a trigger signal (FIG. 3A) is applied from the input terminal 18, the trigger signal is supplied to the variable delay circuit 21, where it is delayed by a predetermined amount according to the shutter speed, and thereafter passes through the AND circuit 23 as described above. The signal is taken out to the output terminal 17 as a vertical synchronizing signal and supplied to the counter 15 as a reset signal via the AND circuit 22 to be reset.

FIGS. 3B and 3E each show a shutter speed of 1/2.
At 50 seconds and 1/500 seconds, the vertical synchronization signal is output after being delayed from the trigger signal. This shows that the start of the accumulation time is constant and the end can be varied.

In the long exposure mode, the common terminals of the switch circuits 20 and 25 are connected to the contact a. When a trigger signal (FIG. 4A) is applied from the input terminal 18,
This trigger signal is supplied to a differentiating circuit 19, where a differentiated pulse (not shown) is generated in synchronization with the falling and rising of the trigger signal. It is shaped and output as a vertical synchronization signal as shown in FIG. 4B.

The trigger signal from the input terminal 18 is inverted by the inverter circuit 24, and the contact a of the switch circuit 25
It is supplied to one input terminal of the OR circuit 26 through the side.

At this time, since the level of one input terminal of the OR circuit 26 is at the high level (H), the output signal from the counter 15 supplied to the other input terminal of the OR circuit 26 is invalidated, and substantially. Is masked.

This state is shown by a broken line in FIG. 4B. As a result, in the case of the real shutter mode, etc., the exposure time (accumulation time) was 1/60 second at maximum for one field.
A longer exposure time is possible.

FIG. 6 shows an example of a configuration of a method of generating a shutter pulse in the timing circuit 6. Reference numeral 30 denotes an input terminal to which a trigger signal (FIG. 3A) is supplied.
This trigger signal is supplied to a differentiating circuit 31, which forms a shutter pulse of 1 μsec narrower than that, for example, as shown in FIG. 3H.

The accumulation, that is, the exposure start, is performed from (the falling edge of) the shutter pulse. Thus, the differentiation circuit 31
Is supplied to one input side of the adder circuit 32.

Reference numeral 33 denotes an input terminal to which a vertical synchronizing signal (VD) is supplied. The vertical synchronizing signal supplied to this input terminal 33 is supplied to the inverter circuit 3 via a switch 34.
5 is supplied to the adder circuit 32 as a normal shutter pulse synchronized with the vertical synchronizing signal, and a shutter pulse as shown in FIGS.

This shutter pulse is supplied to the N-type silicon substrate of the CCD 1 (FIG. 1) through the contact b side of the switch 36, and the charge of the sensor is discarded to the OFD.

At this time, it is not possible to generate a shutter pulse in synchronization with the vertical synchronizing signal generated by delaying the trigger signal by a predetermined time, so that a variable delay circuit 37 is provided. To generate a delay signal having a predetermined width, supply the delay signal as an off signal to the switch 34, and set the switch 34 to an off state so as not to pass a vertical synchronization signal generated with a predetermined time delay from the trigger signal. I do.

The shutter speed setting signal is supplied to the variable delay circuit 37 so that the delay signal (off signal) formed by the variable delay circuit 37 also varies according to the shutter speed.

Reference numeral 38 denotes a conventional shutter IC which varies the start of the accumulation time and keeps the end constant, and its output is a switch 36.
Is supplied to the N-type silicon substrate of the CCD through the contact a.

As described above, in the real shutter mode, the accumulation time is determined by the narrow shutter pulse, the end of the accumulation time is determined by the vertical synchronization signal, and the vertical synchronization signal can be changed according to the shutter speed. As a result, the end of the accumulation time can be changed according to the shutter speed.

[0049]

As described above, according to the present invention, accumulation is started in synchronization with an external trigger signal, and electric charges are accumulated only for a period set by the shutter speed setting signal. Exposure time) can be varied, and the effective accumulation period can be controlled by the pulse width of a trigger signal supplied from outside the CCD camera. Therefore,
In machine vision, etc., the CCD camera user can easily control the effective accumulation time only by setting the pulse width of the external trigger signal. Thus, it is possible to realize a CCD camera capable of performing long-time exposure suitable for, for example, the present invention.

[Brief description of the drawings]

FIG. 1 is a system diagram showing a configuration of the present invention.

FIG. 2 is a timing chart of a restart reset used for describing the present invention.

FIG. 3 is a timing chart of a real shutter used for describing the present invention.

FIG. 4 is a timing chart of long-time exposure for explaining the present invention.

FIG. 5 is a system diagram showing a configuration of a main part of a sync generator used in the present invention.

FIG. 6 is a system diagram showing a configuration of a main part of a timing circuit used in the present invention.

FIG. 7 is a timing chart for explaining a conventional electric shutter.

[Explanation of symbols]

1 ‥‥ CCD, 5 ‥‥ sync generator, 6 ‥‥ timing circuit

Claims (1)

[Claims] 1. A solid-state imaging device, a trigger input means for externally inputting a trigger signal having a predetermined pulse width, and starting accumulation of effective charges of the solid-state imaging device at a timing based on a front end of a pulse of the trigger signal. A solid-state imaging device that terminates the accumulation of effective charges in the solid-state imaging device at a timing based on the trailing end of the pulse of the trigger signal, and drives the solid-state imaging device so that the pulse width of the trigger signal becomes an effective accumulation period. A solid-state imaging device comprising a driving unit.