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JPH10315124A - Polishing method and polishing apparatus - Google Patents

Polishing method and polishing apparatus

Info

Publication number
JPH10315124A
JPH10315124A JP12669797A JP12669797A JPH10315124A JP H10315124 A JPH10315124 A JP H10315124A JP 12669797 A JP12669797 A JP 12669797A JP 12669797 A JP12669797 A JP 12669797A JP H10315124 A JPH10315124 A JP H10315124A
Authority
JP
Japan
Prior art keywords
polishing
sliding resistance
efficiency
wafer
polishing efficiency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12669797A
Other languages
Japanese (ja)
Inventor
Hiroyuki Kojima
弘之 小島
Tetsuo Okawa
哲男 大川
Hidemi Sato
秀己 佐藤
Nobuo Kayaba
信雄 萱場
Takashi Nishiguchi
隆 西口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12669797A priority Critical patent/JPH10315124A/en
Publication of JPH10315124A publication Critical patent/JPH10315124A/en
Pending legal-status Critical Current

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  • Grinding-Machine Dressing And Accessory Apparatuses (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

(57)【要約】 【課題】LSIウエハのCMPで、研磨能率ならびに研磨量を
その場で検出できる手段を提供する。 【解決手段】研磨パッド5の表面と、半導体基板の間に
働く摺動抵抗8を検知するようにした。さらに摺動抵抗8
と研磨能率の関係をあらかじめ測定しておくことで、研
磨能率のその場検出を可能とした。
(57) [Summary] [PROBLEMS] To provide a means capable of detecting a polishing efficiency and a polishing amount on the spot by CMP of an LSI wafer. A sliding resistance acting between a surface of a polishing pad and a semiconductor substrate is detected. Further sliding resistance 8
By measuring the relationship between the polishing efficiency and the polishing efficiency in advance, the in-situ detection of the polishing efficiency was made possible.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は研磨装置およびに研
磨方法に関する。
[0001] The present invention relates to a polishing apparatus and a polishing method.

【0002】[0002]

【従来の技術】高密度半導体集積回路素子の形成プロセ
スの過程で絶縁膜や金属膜のパターン形成等によってLS
Iウエハ表面は複雑な凹凸が生じる。この凹凸を持ったL
SIウエハ表面上に引き続きパターン形成を行うと、リソ
グラフィプロセスにおける焦点深度の余裕が無いために
パターン転写での解像度が不足したり、凹凸の段差部に
おける金属配線膜の欠損が生じるなど、高密度半導体集
積回路の作成上の障害となる場合があった。この問題を
解消するためLSIウエハ表面を研磨パッドを貼り付けた
研磨定盤に押し付けながら摺動し、凹凸を研磨により平
坦化するCMP法が採用されている。
2. Description of the Related Art In a process of forming a high-density semiconductor integrated circuit device, an LS is formed by forming a pattern of an insulating film or a metal film.
I wafer surface has complicated irregularities. L with this unevenness
If pattern formation is continued on the surface of the SI wafer, high resolution semiconductors such as insufficient resolution in pattern transfer due to lack of depth of focus in the lithography process and loss of metal wiring film at uneven steps In some cases, this was an obstacle to the production of integrated circuits. In order to solve this problem, a CMP method is employed in which the surface of the LSI wafer is slid while being pressed against a polishing platen to which a polishing pad is attached, and the unevenness is flattened by polishing.

【0003】従来、CMP法における研磨量の管理は、単
位時間あたりの研磨量、すなわち研磨能率をあらかじめ
実験的に測定しておき、所望の研磨量を測定した研磨能
率で除して必要な研磨時間を決定することで行ってい
た。ところが研磨能率は研磨速度や研磨荷重といった研
磨条件を一定に保っていても、研磨の進行に伴って研磨
パッド表面が摩耗するために大きく変動する。このため
従来のCMP法では所定の研磨回数毎にダミー基板により
研磨能率を測定し、研磨時間の補正を行う必要がある。
また、表面が摩滅した研磨パッドは修復のためダイアモ
ンド砥石などを用いたドレシングを行う必要があるが、
その都度、研磨能率の測定校正を行っている。このよう
に従来の研磨量管理はきわめて煩雑であり、これを回避
するための技術開発が望まれていた。
Conventionally, the polishing amount in the CMP method is controlled by measuring the polishing amount per unit time, that is, the polishing efficiency in advance, and dividing the desired polishing amount by the measured polishing efficiency. I was going to decide on the time. However, even if the polishing conditions such as the polishing rate and the polishing load are kept constant, the polishing efficiency fluctuates greatly because the polishing pad surface is worn with the progress of polishing. For this reason, in the conventional CMP method, it is necessary to measure the polishing efficiency with a dummy substrate every predetermined number of times of polishing and to correct the polishing time.
Also, the polishing pad whose surface has been worn needs to be dressed using a diamond whetstone etc. for repair,
Each time, measurement and calibration of polishing efficiency are performed. As described above, the conventional control of the polishing amount is extremely complicated, and there has been a demand for technical development for avoiding this.

【0004】[0004]

【発明が解決しようとする課題】研磨パッド表面と半導
体基板表面間の摺動抵抗の検出による、研磨能率のその
場検出の手段を提供する。
SUMMARY OF THE INVENTION The present invention provides a means for in-situ detection of polishing efficiency by detecting a sliding resistance between a polishing pad surface and a semiconductor substrate surface.

【0005】[0005]

【課題を解決するための手段】研磨パッド表面と、半導
体基板の間に働く摺動抵抗を検知するようにした。さら
に摺動抵抗と研磨能率の関係をあらかじめ測定しておく
ことで、研磨能率のその場検出を可能とした。
The sliding resistance acting between the polishing pad surface and the semiconductor substrate is detected. Further, by measuring the relationship between the sliding resistance and the polishing efficiency in advance, the in-situ detection of the polishing efficiency was made possible.

【0006】LSIウエハの研磨で、ウエハに与えられた
総仕事量Wはウエハ、研磨パッド間の摺動抵抗を摺動距
離で積分したものとなり、摺動抵抗をF、摺動距離をx
とすれば、(W=∫F(x)dx)で表される。ウエハ表面の除去
に要する仕事量は、この総仕事量Wの一部であり、残り
の仕事量は摺動に伴う摩擦熱などに変化する。従って、
総仕事量のうち、ウエハ表面の除去に使われる仕事量の
割合がほぼ一定の範囲では総仕事量とウエハ表面の除去
量、すなわち研磨量は比例し、比例計数をk、研磨量をv
とすれば(v= k∫F(x)dx)となる。ここで摺動距離xは研
磨速度uの時間積分(x=∫u(t)dt)であるから、これを(v=
k∫F(x)dx)に代入して両辺の時間微分を取ると(dv/dt=
kF(t)u(t))なる関係が得られる。研磨速度(u(t))が時間
によらず一定であれば、摺動抵抗Fと研磨量の時間微分
(dv/dt) 、すなわち研磨能率が比例することがわかる。
実用的には研磨条件の影響を受けるために必ずしも摺動
抵抗と研磨能率は比例しないと考えられるが、任意の研
磨条件の下における摺動抵抗と研磨能率の関係をあらか
じめ測定し、これを用いることで研磨中の摺動抵抗Fか
ら研磨能率(dv/dt)を把握できる。
In the polishing of an LSI wafer, the total work W given to the wafer is obtained by integrating the sliding resistance between the wafer and the polishing pad by the sliding distance. The sliding resistance is F, and the sliding distance is x.
Then, it is represented by (W = ∫F (x) dx). The work required to remove the wafer surface is a part of the total work W, and the remaining work changes into frictional heat due to sliding. Therefore,
In the range where the ratio of the work used for removing the wafer surface in the total work is almost constant, the total work and the removal amount of the wafer surface, that is, the polishing amount are proportional, and the proportional coefficient is k and the polishing amount is v.
Then (v = k∫F (x) dx). Here, since the sliding distance x is a time integral of the polishing rate u (x = ∫u (t) dt), this is expressed as (v =
k∫F (x) dx) and taking the time derivative of both sides gives (dv / dt =
kF (t) u (t)) is obtained. If the polishing rate (u (t)) is constant regardless of time, the sliding resistance F and the time differential of the polishing amount
(dv / dt), that is, the polishing efficiency is proportional.
In practice, it is considered that the sliding resistance and the polishing efficiency are not necessarily proportional to the influence of the polishing conditions, but the relationship between the sliding resistance and the polishing efficiency under any polishing conditions is measured in advance, and this is used. Thus, the polishing efficiency (dv / dt) can be grasped from the sliding resistance F during polishing.

【0007】[0007]

【発明の実施の形態】以下、添付の図面を参照しなが
ら、本発明の一実施例について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.

【0008】図1は本発明の摺動抵抗検出方法の概略図
である。研磨荷重2を印加してウエハ6を研磨する際、研
磨パッド5、ウエハ6間に発生する摺動抵抗8はチャック
7、主軸3、軸受4を介して荷重変換器1によって摺動抵抗
信号9に変換される。研磨パッド半径上のウエハの位置
によって研磨中の摺動抵抗の方向は異なるため、荷重変
換器1は主軸と直交する平面内で直交する二分力を測定
し、この二分力の合力を摺動抵抗信号9とする。
FIG. 1 is a schematic diagram of a sliding resistance detecting method according to the present invention. When the polishing load 2 is applied to polish the wafer 6, the sliding resistance 8 generated between the polishing pad 5 and the wafer 6 is determined by a chuck.
7, is converted into a sliding resistance signal 9 by the load converter 1 via the main shaft 3 and the bearing 4. Since the direction of the sliding resistance during polishing varies depending on the position of the wafer on the polishing pad radius, the load converter 1 measures a two-component force orthogonal to a plane perpendicular to the main axis, and determines the resultant force of the two components as the sliding resistance. Signal 9 is assumed.

【0009】図2は本発明の研磨装置のブロック図であ
る。研磨中に荷重変換器1からの摺動抵抗信号9はA/D変
換器20によりA/D変換後、パーソナルコンピュータ18に
入力され、予め測定しておいた摺動抵抗と研磨能率の参
照データ21より後述の方法で研磨能率に変換される。こ
の研磨能率を研磨時間で積算してゆくことで研磨量を算
出する。算出された研磨量は表示器19に表示し、所望の
研磨量に達した場合は定盤駆動モータコントローラ17に
停止信号を送り、定盤駆動モータ11を自動的に停止させ
る。さらに、研磨中の研磨能率の監視を随時行い、研磨
能率が所定の値より低下した場合、パーソナルコンピュ
ータ18から空気流路切り替えバルブ14を切り替える信号
を送り、エアコンプレッサ15からの圧縮空気をエアシリ
ンダ12に送り、ダイアモンド砥石16を研磨定盤10に貼付
された研磨パッド5に押しつけドレシングを行う機能を
備える。なお、押しつけ圧力は圧力レギュレータ13で任
意の値に調整でき、ダイアモンド砥石は図示されていな
いモータにより任意の回転数で自転できるようになって
いる。また、研磨試料には直径150mmのSiウエハ表面に
液状ガラスを回転塗布した後、熱処理を行い約2μmの厚
さのSi酸化膜を形成したものを用いた。
FIG. 2 is a block diagram of a polishing apparatus according to the present invention. During the polishing, the sliding resistance signal 9 from the load converter 1 is A / D converted by the A / D converter 20 and then input to the personal computer 18, and reference data of the sliding resistance and the polishing efficiency measured in advance. From 21 is converted to polishing efficiency by the method described below. The polishing amount is calculated by integrating the polishing efficiency with the polishing time. The calculated polishing amount is displayed on the display 19, and when the desired polishing amount is reached, a stop signal is sent to the platen drive motor controller 17 to automatically stop the platen drive motor 11. Further, monitoring of the polishing efficiency during polishing is performed as needed, and when the polishing efficiency falls below a predetermined value, a signal for switching the air flow path switching valve 14 is sent from the personal computer 18 to compress the compressed air from the air compressor 15 into the air cylinder. 12 and has a function of performing dressing by pressing a diamond grindstone 16 against a polishing pad 5 attached to a polishing platen 10. The pressing pressure can be adjusted to an arbitrary value by the pressure regulator 13, and the diamond grindstone can be rotated at an arbitrary rotation speed by a motor (not shown). A polishing sample was prepared by spin-coating liquid glass on the surface of a Si wafer having a diameter of 150 mm, and then performing a heat treatment to form a Si oxide film having a thickness of about 2 μm.

【0010】図3はSiウエハをSiO2砥粒濃度3%の水溶液
を圧縮弾性率100Mpa、厚さ1mmの発泡ポリウレタンを表
面に貼付した研磨定盤上に100ml/minの割合で供給して
研磨を行った場合の摺動抵抗および研磨能率のウエハ研
磨枚数に伴う変化を表したものである。このときの研磨
定盤へのSiウエハの押しつけ圧力は500g/cm2、Siウエハ
中心位置での研磨定盤の摺動速度は300mm/sである。ま
た、Siウエハは20r/minで自転させた。同図よりウエハ
の研磨枚数が増加するに従って、摺動抵抗,研磨能率と
も減少することがわかる。なお、研磨能率の測定は研磨
前にSiウエハ上のSi酸化膜膜厚を(米)Nanometrix社製の
薄膜厚さ計Nanospec4100を用いて測定し、研磨後に再度
Si酸化膜膜厚の測定を行い、研磨前後の膜厚の差を研磨
時間で除して求めた。
FIG. 3 shows polishing of an Si wafer by supplying an aqueous solution having a SiO 2 abrasive concentration of 3% at a rate of 100 ml / min onto a polishing platen having a compression elastic modulus of 100 MPa and a foamed polyurethane having a thickness of 1 mm adhered to the surface. And the change in the sliding resistance and polishing efficiency with the number of polished wafers in the case of performing the above. At this time, the pressure for pressing the Si wafer against the polishing platen is 500 g / cm 2 , and the sliding speed of the polishing platen at the center position of the Si wafer is 300 mm / s. The Si wafer was rotated at 20 r / min. It can be seen from the figure that as the number of polished wafers increases, both the sliding resistance and the polishing efficiency decrease. The polishing efficiency was measured by measuring the thickness of the Si oxide film on the Si wafer before polishing using a thin spectrometer Nanospec4100 manufactured by Nanometrix (USA), and again after polishing.
The thickness of the Si oxide film was measured, and the difference in film thickness before and after polishing was divided by the polishing time.

【0011】図4は図3の結果から摺動抵抗と研磨能率
の相関を示した。このデータから研磨能率を摺動抵抗の
多項式として近似を行い、その場検出された摺動抵抗よ
りパーソナルコンピュータを用い実時間で研磨能率を算
出し、さらにパーソナルコンピュータ上で研磨能率の時
間積分を行い研磨量を算出する。
FIG. 4 shows the correlation between the sliding resistance and the polishing efficiency from the results of FIG. From this data, the polishing efficiency is approximated as a sliding resistance polynomial, the polishing efficiency is calculated in real time using a personal computer from the sliding resistance detected on the spot, and the polishing efficiency is integrated over time on a personal computer. Calculate the polishing amount.

【0012】以上の結果を用いて、研磨量1μmを目標と
し、研磨パッドのドレシングを行わず、ウエハを25枚連
続して研磨を行った。各ウエハは研磨開始後、表示器に
表示された研磨量が1μmになった時点で研磨を終了し
た。その結果、従来の研磨方法では研磨量に約±0.15μ
mのばらつきが生じるのに対して、本研磨装置を用いた
研磨加工では研磨量のばらつきが約±0.03μmに抑制さ
れることが確認された(図5参照)。
Using the above results, 25 wafers were continuously polished with a polishing amount of 1 μm as a target, without dressing the polishing pad. Each wafer was polished when the polishing amount indicated on the display became 1 μm after the start of polishing. As a result, the polishing amount is about ± 0.15μ
It was confirmed that the variation in the polishing amount was suppressed to about ± 0.03 μm in the polishing processing using the present polishing apparatus, while the variation in m was caused (see FIG. 5).

【0013】次に、研磨能率が所定の値より低下した場
合に研磨パッドのドレシングを自動的に行うシーケンス
を実行し、従来方法との比較を行った。従来方法はSiウ
エハ10枚を研磨する毎にダミーウエハによる研磨能率の
実測を行い、研磨時間の補正ならびに研磨能率が所定の
値より低下していた場合には研磨パッドのドレシングを
行うようにした。研磨量の目標値は1μmとし、ウエハ10
0枚を連続して研磨した。その結果、従来の研磨加工法
では研磨量におよそ±0.15μmのばらつきが生じるのに
対し、本発明では研磨量のばらつきが約±0.03μmに抑
制されることが確認された(図6参照)。また、このと
きのSiウエハ100枚を研磨するための所要時間は従来の
方法を利用した研磨加工では約1400分であったのに対
し、本研磨装置を利用した研磨加工ではその1/3の500mi
nであり、ウエハ製造効率の向上が確認された。
Next, a sequence for automatically dressing the polishing pad when the polishing efficiency falls below a predetermined value was executed, and a comparison was made with the conventional method. In the conventional method, the polishing efficiency was actually measured by a dummy wafer every time 10 Si wafers were polished, and the polishing time was corrected and the polishing pad was dressed when the polishing efficiency was lower than a predetermined value. The target value of the polishing amount is 1 μm, and the wafer 10
0 sheets were continuously polished. As a result, it was confirmed that the variation in the polishing amount was about ± 0.15 μm in the conventional polishing method, whereas the variation in the polishing amount was suppressed to about ± 0.03 μm in the present invention (see FIG. 6). . In addition, the required time for polishing 100 Si wafers at this time was about 1400 minutes in the polishing processing using the conventional method, whereas the polishing processing using the present polishing apparatus was one third of that time. 500mi
n, indicating an improvement in wafer manufacturing efficiency.

【0014】[0014]

【発明の効果】本発明により得られる最大の効果はCMP
で問題となる研磨量の管理が従来以上に簡便に行えるこ
とにある。また、付加的に得られる効果としては、その
管理の自動化が可能な点にあり、製造工程の大幅な簡略
化ができる。
The greatest effect obtained by the present invention is CMP.
The problem is that the polishing amount, which is a problem, can be more easily controlled than before. An additional effect is that the management can be automated, and the manufacturing process can be greatly simplified.

【図面の簡単な説明】[Brief description of the drawings]

【図1】摺動抵抗検出方法の説明図。FIG. 1 is an explanatory diagram of a sliding resistance detection method.

【図2】研磨装置のブロック図。FIG. 2 is a block diagram of a polishing apparatus.

【図3】ウエハ研磨枚数と摺動抵抗および研磨能率の相
関の特性図。
FIG. 3 is a characteristic diagram showing the correlation between the number of polished wafers, sliding resistance, and polishing efficiency.

【図4】摺動抵抗と研磨能率の相関の特性図。FIG. 4 is a characteristic diagram showing a correlation between sliding resistance and polishing efficiency.

【図5】ウエハ研磨枚数に伴う研磨量の変動についての
本発明と従来法の比較の説明図。
FIG. 5 is an explanatory diagram of a comparison between the present invention and a conventional method regarding a change in a polishing amount according to the number of polished wafers.

【図6】ウエハ研磨枚数に伴う研磨量の変動についての
本発明と従来法の比較の説明図。
FIG. 6 is an explanatory diagram of a comparison between the present invention and a conventional method regarding a change in a polishing amount according to the number of polished wafers.

【符号の説明】[Explanation of symbols]

1…荷重変換器、2…研磨荷重、3…主軸、4…軸受、
5…研磨パッド、6…ウエハ、7…チャック、8…摺動
抵抗、9…摺動抵抗信号。
1 ... Load converter, 2 ... Polishing load, 3 ... Spindle, 4 ... Bearing,
5 polishing pad, 6 wafer, 7 chuck, 8 sliding resistance, 9 sliding resistance signal.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 萱場 信雄 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 (72)発明者 西口 隆 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Nobuo Kayaba 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Technology Laboratory (72) Inventor Takashi Nishiguchi 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Production Technology Laboratory

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】微細回路パターンを形成した半導体基板の
表面を加圧ヘッドを介して研磨定盤に貼付された研磨パ
ッドに押し付け、前記微細回路パターンの形成に伴って
生じた凹凸を平坦に研磨する研磨装置に於いて、前記半
導体基板の表面と前記研磨パッド間に生じる摺動抵抗を
検出する機能を有することを特徴とする研磨装置。
1. A semiconductor substrate on which a fine circuit pattern is formed is pressed against a polishing pad attached to a polishing platen via a pressure head, and the unevenness caused by the formation of the fine circuit pattern is polished flat. A polishing apparatus having a function of detecting a sliding resistance generated between the surface of the semiconductor substrate and the polishing pad.
【請求項2】請求項1に於いて、前記摺動抵抗の変化と
研磨時間とから研磨の進行状況の監視を行う研磨方法。
2. The polishing method according to claim 1, wherein the progress of polishing is monitored from the change in the sliding resistance and the polishing time.
【請求項3】請求項2に記載の研磨方法を動作シーケン
スに組み込んだ研磨装置。
3. A polishing apparatus incorporating the polishing method according to claim 2 in an operation sequence.
【請求項4】請求項1に於いて、前記摺動抵抗から前記
研磨パッド表面の摩滅状態を判定して前記研磨パッド表
面の修復を行う研磨方法。
4. The polishing method according to claim 1, wherein the polishing pad surface is repaired by determining a worn state of the polishing pad surface from the sliding resistance.
【請求項5】請求項4の前記研磨方法を動作シーケンス
に組み込んだ研磨装置。
5. A polishing apparatus incorporating the polishing method according to claim 4 in an operation sequence.
JP12669797A 1997-05-16 1997-05-16 Polishing method and polishing apparatus Pending JPH10315124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12669797A JPH10315124A (en) 1997-05-16 1997-05-16 Polishing method and polishing apparatus

Publications (1)

Publication Number Publication Date
JPH10315124A true JPH10315124A (en) 1998-12-02

Family

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Family Applications (1)

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Country Status (1)

Country Link
JP (1) JPH10315124A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093080A (en) * 1998-05-19 2000-07-25 Nec Corporation Polishing apparatus and method
US6191038B1 (en) 1997-09-02 2001-02-20 Matsushita Electronics Corporation Apparatus and method for chemical/mechanical polishing
US6231425B1 (en) 1998-08-18 2001-05-15 Nec Corporation Polishing apparatus and method
US6531399B2 (en) 2000-10-26 2003-03-11 Hitachi, Ltd. Polishing method
EP1222056A4 (en) * 1999-08-31 2005-01-05 Micron Technology Inc Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
CN104858786A (en) * 2010-09-09 2015-08-26 株式会社荏原制作所 Polishing Apparatus
JP2016129931A (en) * 2012-08-28 2016-07-21 株式会社荏原製作所 Dressing process monitoring method and polishing apparatus

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191038B1 (en) 1997-09-02 2001-02-20 Matsushita Electronics Corporation Apparatus and method for chemical/mechanical polishing
US6416617B2 (en) 1997-09-02 2002-07-09 Matsushita Electronics Corporation Apparatus and method for chemical/mechanical polishing
US6093080A (en) * 1998-05-19 2000-07-25 Nec Corporation Polishing apparatus and method
US6231425B1 (en) 1998-08-18 2001-05-15 Nec Corporation Polishing apparatus and method
US7172491B2 (en) 1999-08-31 2007-02-06 Micron Technology, Inc. Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
EP1222056A4 (en) * 1999-08-31 2005-01-05 Micron Technology Inc Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
US6969297B2 (en) 1999-08-31 2005-11-29 Micron Technology, Inc. Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
US7229336B2 (en) 1999-08-31 2007-06-12 Micron Technology, Inc. Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
US6648728B2 (en) * 2000-10-26 2003-11-18 Hitachi, Ltd. Polishing system
SG106633A1 (en) * 2000-10-26 2004-10-29 Hitachi Ltd Polishing system
US6531399B2 (en) 2000-10-26 2003-03-11 Hitachi, Ltd. Polishing method
CN104858786A (en) * 2010-09-09 2015-08-26 株式会社荏原制作所 Polishing Apparatus
JP2016129931A (en) * 2012-08-28 2016-07-21 株式会社荏原製作所 Dressing process monitoring method and polishing apparatus

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