JPH10312639A - Method of manufacturing optical disk, optical disk and optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure a frame synchronization even in a case of preformatting only with a modulation signal satisfying a modulation specification by detecting pre-formatted address data and detecting a timing of frame synchronization based on a result of a comparison between 1st and 2nd data columns reproduced and generated from pre-formatted data. SOLUTION: When an optical disk 2 is manufactured by exposing an original disk by a mastering device 1, a driving circuit 5 drives an optical system of an optical head 4 according to wobble signal WB successively creating address data blocks in synchronism with the rotation of the original disk 2, by means of a wobble data WD signal creation and generation circuits 6, 7, and meanders a focus position of a laser beam. In such a case, the WB signal generation circuit 7 generates the WD signal by using only modulation signal accordance with the modulation specification by phase-modulation, and thereby enables to detect correct phase information at a timing corresponding to WD bit boundary from any signal position.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an optical disk, an optical disk and an optical disk apparatus, for example, by meandering a groove formed by a guide groove of a laser beam.
An optical disc on which serial data such as position information is recorded,
The present invention can be applied to an optical disk device or the like that reproduces this optical disk. According to the present invention, first and second data strings are obtained from a serial data string obtained by reproducing preformatted data, and based on a result of comparison between the first and second data strings, a pre-recorded data is recorded on an optical disc. By detecting formatted address data and detecting the timing of frame synchronization, frame synchronization can be reliably performed even when preformatting is performed only with a modulation signal that satisfies the modulation rule.

[0002]

2. Description of the Related Art Conventionally, in an optical disc, position information, time information, and the like (hereinafter, referred to as ID data) of a laser beam irradiation position are detected by meandering of a groove serving as a guide groove of a laser beam.

That is, in the manufacturing process of this type of optical disk, a laser beam is irradiated on the disk master while rotating the disk master at a predetermined rotation speed, and the irradiation position of the laser beam is sequentially shifted to the outer peripheral side of the disk master. Let it. Thus, in this manufacturing process, the disk master is sequentially exposed to a laser beam to form tracks spirally from the inner circumference to the outer circumference of the disk master.

In the manufacturing process of an optical disk, a stamper is created from the master disk, and an optical disk is created from the stamper through processes such as development and electroforming. As a result, the optical disk has spiral grooves formed from the inner peripheral side toward the outer peripheral side in response to the irradiation of the laser beam on the master disk.

[0005] When the master disc is exposed in this manner, in the manufacturing process of the optical disc, as shown in FIG.
A reference signal synchronized with a predetermined carrier signal is frequency-divided to generate a clock CK (FIG. 12B). Further, the first reference signal synchronized with the clock CK and the second reference signal which is a 1/2 frequency-divided signal of the clock CK are respectively
The D data D1 (FIG. 12A) is arranged in accordance with the logical level, whereby the ID data D1 is bi-phase mark modulated (FIGS. 12A, 12B and 12C). Further, after a channel signal ch is generated by inserting a synchronization pattern into the serial data string generated by bi-phase mark modulation in this way, the carrier signal used for generating the clock CK is frequency-modulated by the channel signal ch. To generate a modulated signal (hereinafter referred to as a wobble signal) WB. In the optical disc manufacturing process, the irradiation position of the laser beam is displaced in the radial direction of the master disc so as to follow the signal level of the wobble signal WB.

Thus, as shown in FIG. 13, this type of optical disk is formed so that the groove is meandering according to the synchronization pattern and the ID data. The spindle motor is controlled so that the frequency becomes a predetermined frequency, and is driven to rotate at a predetermined rotation speed. Further, the recording / reproducing position can be confirmed by detecting the ID data based on the meandering, and the clocks for various processing references can be generated based on the meandering (FIGS. 13A to 13A). (C)).

[0007]

However, the conventional optical disk has a drawback that it is difficult to generate a highly accurate clock from an area where ID data is recorded.

That is, a half cycle of the clock CK is set to ch
In this type of optical disk, if the frequency of the carrier signal is n [Hz / ch], n + d [Hz / ch] for logic 1 of the channel signal ch and n + d [Hz / ch] for logic 0 of the channel signal ch Is assigned nd [Hz / ch], and the wobble signal WB is generated.

Here, in order to simplify the description, n = 4,
Assuming that d = 1/16, the time point t0 at the start of the synchronization pattern
When the wobble signal WB crosses at 0 in FIG.
2), DSV (Digital Sum Va)
lue) is set to a value of 0, so that the wobble signal WB can cross zero even at the end point t1 of the synchronization pattern.

However, at the subsequent time t2 of the rising edge of the clock CK, the timing of the 0 cross of the wobble signal WB is kept at 2π / 16 by maintaining the frequency n + d [Hz / ch] for one cycle of the clock CK.
It will change by the period.

At time t3, at which the clock CK rises, and at times t4 and t5, the frequency n + d [Hz] is a half cycle of the clock CK.
/ Ch], the signal is held at the frequency n−d [Hz / ch] for the next 周期 cycle, so that the timing of the 0 cross of the wobble signal WB is 2π / ch.
It is kept as changed for 16 cycles.

On the other hand, at the time t6 of the subsequent rising of the clock CK, the frequency is maintained at the frequency nd [Hz / ch] for one cycle of the clock CK, so that the phase change between the times t1 and t2 is obtained. The minute is canceled and the wobble signal WB crosses zero.

From these facts, in the wobble signal WB for meandering the groove, 0 is applied to the clock CK.
Even if the timing of the cross changes and the wobble signal WB is reproduced simply by detecting the meandering of the groove, it becomes difficult to generate a clock with higher accuracy than the reproduced wobble signal WB.

Incidentally, the timing at which the wobble signal WB correctly crosses 0 is detected, and the timing
A method of generating a high-accuracy clock by locking the LL circuit is also conceivable. However, at the timing when the wobble signal WB crosses 0 correctly, it is practically difficult to realize it because the wobble signal WB changes according to the content of the ID data. .

As one method of solving such a defect, the wobble signal WB is set to 0 at each bit center by focusing on the change of the channel signal ch from the modulation rule of the ID data.
By giving a phase offset by a predetermined amount so as to cross each other, a method is conceivable in which correct phase information can be detected at the center of each bit of the ID data.

That is, in the channel signal ch,
Since the data always inverts at the bit boundary of the ID data, for example, the phase change Δ1 from the bit center at the time t11 to the subsequent bit boundary is canceled by the phase change Δ2 from the bit boundary to the subsequent bit at the time t12. Will be. As a result, the wobble signal WB can be generated by giving a predetermined amount of phase offset to the ID data portion and making a zero cross at the center of each bit by a continuous signal waveform.

However, since the synchronization pattern is set to a logical pattern that does not comply with the modulation rule so that the timing of frame synchronization can be reliably detected, it may not be possible to give a phase offset in this way. , The continuous wobble signal WB cannot be generated. In other words, when the time axis is reversed with the time point t1 of the end of the synchronization pattern interposed therebetween, the time point t corresponding to the following bit center is obtained.
In the period up to a, the wobble signal WB can be correctly crossed by zero because the polarity is inverted with the time point t1 corresponding to the bit boundary interposed therebetween as in the case of the ID data portion.

However, the time t corresponding to the following bit center
Until b, the logic 0 continues, and in this case, the wobble signal WB does not cross zero correctly at the timing corresponding to the bit center. From these facts, there is a problem that even if it is possible to correctly detect the phase information for the ID data portion and generate a highly accurate clock, it is not possible to detect the correct phase information for the synchronization pattern portion.

On the other hand, as shown in FIG. 14, the ID data D1 (FIG. 14 (A)) is phase-modulated to generate a channel signal ch (FIG. 14 (B)), which is frequency-modulated to wobble. A signal may be generated. In this case, the channel data ch is inverted at the bit centers t1, t2, t3,... It is considered that the wobble signal WB is set to cross 0 at the bit boundary of D1, and correct phase information can be detected from this bit boundary.

However, also in this case, since the synchronization pattern is set to a logical pattern that does not follow the modulation rule so that the timing of frame synchronization can be detected reliably, the synchronization pattern is set at the bit boundary of the ID data D1. At the corresponding time point ta, the wobble signal WB cannot be correctly crossed to zero.

From these facts, it can be considered that if the frame synchronization can be reliably performed without using the synchronization pattern, it is possible to detect more phase information than the groove and generate a clock with high accuracy. .

The present invention has been made in view of the above points, and is intended to propose a method of manufacturing an optical disk, an optical disk, and an optical disk apparatus capable of reliably performing frame synchronization without using a synchronization pattern. is there.

[0023]

In order to solve this problem, the present invention is applied to an optical disk or a method for manufacturing an optical disk, and forms serial data by at least address data consisting of position information or time information. The serial data is modulated by switching between the first reference clock and the second reference clock according to the modulation rule, and the modulation result is frequency-modulated to generate a modulated signal.
Further, the modulated signal is pre-formatted on an optical disk, and at this time, the modulated signal is generated only with a modulated signal according to the above-described modulation rule.

At this time, a bit inversion bit is set.

Further, the present invention is applied to an optical disk apparatus for accessing such an optical disk, and a modulated signal obtained from the optical disk is demodulated to obtain a data string of a demodulation result. , The timing corresponding to the bit center of the serial data recorded on the optical disk or the timing corresponding to the boundary between bits is detected, and a clock is generated from the modulated signal based on the detected timing. I do. At this time, first and second data strings are generated from the data string of the demodulation result with reference to the timing detected earlier, and the first and second data strings are sequentially updated with the data string of the demodulation result. , By sequentially obtaining the result of comparison between the first and second data strings, the timing at which the address data assigned to the previous serial data is reproduced is detected.

According to a predetermined modulation rule, the modulation result generated by switching the first and second reference clocks is frequency-modulated to generate a modulated signal. Thus, a modulated signal can be reproduced to generate a clock. At this time, if this modulated signal is generated only with a modulation signal in accordance with the above-described modulation rule, a modulated signal including a large amount of edge information necessary for generating a clock can be generated. At this time, if at least serial data is formed by address data consisting of position information or time information,
Even if the modulated signal is generated only by the modulation signal according to the modulation rule, the timing of the frame synchronization can be detected based on the address data.

At this time, if the bit inversion bit is set, the bit synchronization can be detected based on the bit inversion bit.

Thus, a clock can be generated from a modulated signal by applying the present invention to an optical disk device. At this time, the timing corresponding to the bit center of the serial data or the timing corresponding to the boundary between the bits is detected from the data sequence of the demodulation result obtained by demodulating the modulated signal, and the demodulation is performed based on the detected timing. By generating a clock from a signal, it is possible to selectively detect phase information from locations where high-accuracy phase information can be detected and generate a high-accuracy clock. Also, from the data string of the demodulation result based on the detected timing,
By generating the first and second data strings, sequentially updating the first and second data strings with the data string of the demodulation result, and sequentially obtaining the comparison result between the first and second data strings. The timing at which the address data is reproduced can be detected by comparing the successively reproduced address data.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a block diagram showing a mastering device according to the embodiment of the present invention. In the manufacturing process of the optical disc according to this embodiment, the master disc 2 is exposed by the mastering device 1, and the master disc 2 is exposed.
More optical disks are manufactured.

Here, in the mastering apparatus 1, the master disc 2 is formed by applying a resist on a surface of a glass substrate, for example, and is rotated at a predetermined rotation speed by a spindle motor 3.

The optical head 4 irradiates a laser beam L to the disk master 2 while being sequentially displaced from the inner circumference to the outer circumference of the disk master 2 in synchronization with the rotation of the disk master 2 by a predetermined thread mechanism. I do. As a result, the optical head 4 generates a spiral track from the inner circumference to the outer circumference of the master disc 2. Further, the optical head 4 is configured such that the optical system is movable in the radial direction of the master disc 2, and the drive circuit 5 drives the optical system of the optical head 4 according to the wobble signal WB. Thereby, in the mastering device 1, the irradiation position of the laser beam L is meandered according to the wobble signal WB.

The wobble data generation circuit 6 generates wobble data W whose value sequentially changes according to the displacement of the optical head 4.
Generate and output D. That is, the wobble data generation circuit 6 receives a timing signal (comprising an FG signal or the like) synchronized with the rotation of the disk master 2 from the spindle motor 3, and counts this timing signal by a predetermined counter. As a result, the wobble data generation circuit 6 determines the sync number sync no and the sync number sy whose values sequentially and cyclically change in a cycle of 1/16 rotation of the disk master 2.
The track number tr whose value changes each time the irradiation position of the laser beam L is displaced by one track corresponding to the change of nc no
Generate ack no.

Thus, the wobble data generation circuit 6
Generates address data with a sync number sync no and a track number track no. Here, the wobble data generation circuit 6 generates, for example, a sync number sync no and a track number track no using 4 bits and 20 bits, respectively.

Further, the wobble data generating circuit 6 executes the following arithmetic processing using the information word M (x) based on the sync number sync no and the track number track no,
Error detection code R (X) (CRCC: Cyclic Redundancy
Check Code).

[0036]

(Equation 1)

Further, the wobble data generation circuit 6 inverts all bits of the error detection code R (X) to generate an error detection code XCRCC. As a result, the wobble data generation circuit 6 sets the sync number sync no and the track number tr
Even when all the logic levels of ack no are logic 0, the error detection code XCRCC is generated so that the corresponding error detection code XCRCC becomes logic 1 data. Where G
(X) is a generator polynomial.

Further, the wobble data generation circuit 6 adds a reserve bit rev to these sync number sync no, track number track no, and error detection code XCRCC, and generates an address data block in the format shown in FIG. Are sequentially generated. Thus, the wobble data generation circuit 6 sets the sync number sync no and the track number track
Even if the logic levels of no are all logic 0, by generating the error detection code XCRCC so that the corresponding error detection code XCRCC becomes data of logic 1, the bit must always be generated in one address data block. This address data block is generated so that an inversion point occurs.

At this time, the wobble data generation circuit 6
If the logical levels of the sync number sync no and the track number track no are all logical 1, the reserved bit rev is 1
One is set to a theoretical value of 0, and in this case also, this address data block is generated so that a bit inversion point always occurs in one address data block. Thus, the wobble data generation circuit 6 generates the address data block so that, when the data of the address data block is phase-modulated, one channel having the same logical level always occurs. In this embodiment, an address data block is generated by allocating 16 bits and 8 bits to the error detection code XCRCC and the reserved bit rev, respectively.

The wobble data generating circuit 6 sequentially generates address data blocks in synchronization with the rotation of the disk master 2, and converts the generated address data blocks into serial data synchronized with the rotation of the disk master 2. And serially outputs the serial data to the wobble signal generation circuit 7 as wobble data WD.

The wobble signal generation circuit 7 generates a wobble signal WB from the wobble data WD and the like. In the wobble signal generation circuit 7, the generation circuit 7A
A reference signal having a frequency of 115.2 [kHz] is generated. In the mastering device 1, the spindle motor 3 is spindle-controlled using the reference signal, thereby generating a wobble signal WB synchronized with the rotation of the master disc 2.

The frequency dividing circuit 7B uses the frequency 115.2
The [kHz] reference signal is frequency-divided by 1/8 and the frequency is 14.4.
A [kHz] reference clock is generated. Phase modulation circuit 7
C is a first reference clock synchronized with the phase of the reference clock having a frequency of 14.4 [kHz] in accordance with the logic level of the wobble data WD, and has a 180-degree phase with respect to the first reference clock. Different second reference clocks are sequentially selected. Thereby, the phase modulation circuit 7C performs phase modulation on the wobble data WD to generate a channel signal ch.

The frequency dividing circuit 7D has a frequency of 115.2 [kHz].
z] is divided by な る, and the frequency is set to 47.6 times the frequency of the phase modulation clock.
A reference clock for frequency modulation of [kHz] is generated. The frequency modulation circuit 7E frequency-modulates the channel signal ch using the frequency modulation reference clock having a frequency of 57.6 [kHz] as a carrier signal, and outputs the modulated signal as a wobble signal WB. Thereby, the wobble signal generation circuit 7 generates the wobble signal WB using only the modulation signal according to the modulation rule by the phase modulation.

At this time, the frequency modulation circuit 7E converts the logical 1 and logical 0 channels of the channel signal ch into the frequencies 4 + ／ [Hz / ch] and 4-1 / 4 [H], respectively.
z / ch] to generate a frequency modulation signal. At this time, at timings t1, t2, t3,... Corresponding to the bit boundaries of the wobble data WD (FIG.
(C)), a frequency-modulated signal is generated so that the wobble signal WB crosses the 0 level, and a frequency-modulated signal is generated such that the signal level changes smoothly between the front and rear channels.

That is, in the wobble signal generating circuit 7, as shown in FIG. 3 and FIG. 4, each channel is controlled by using a frequency modulation reference clock whose frequency is set to four times that of the phase modulation clock. Is the frequency 4 + ／
By setting to [Hz / ch] or 4-1 / 4 [Hz / ch], the frequency modulation signal is changed so that the wobble signal WB crosses the 0 level at the timing ts corresponding to the bit boundary of the wobble data WD. If you generate
At the timing corresponding to the bit center of the wobble data WD, the signal level of the wobble signal WB rises to the maximum amplitude on the positive side or the negative side. Therefore, by switching the polarity as needed to generate the wobble signal WB, the signal level of the wobble signal WB can be smoothly changed.

Thus, wobble signal generation circuit 7 generates wobble signal WB such that the signal level smoothly changes and crosses zero at timing ts corresponding to each bit boundary of wobble data WD.

Thus, the wobble signal generation circuit 7
Generates the wobble signal WB using only the modulation signal according to the modulation rule by the phase modulation, so that the wobble data W can be output from any part of the wobble signal WB.
The wobble signal WB is generated so that the timing corresponding to the bit boundary of D can be detected, and the correct phase information can be detected from these timings.

In this embodiment, the disk master 2
After developing a groove shape corresponding to the laser beam irradiation position on the surface of the disk master 2, the disk master 2 is electroformed to form a stamper. Further, a disk substrate is formed by the stamper, and a phase change film, a protective film and the like are sequentially formed on the disk substrate to manufacture an optical disk. This allows the optical disk to:
Laser beam irradiation is used to locally change the crystal structure of the phase change film so that desired data can be recorded. In addition, data recorded by detecting the change in the amount of return light by irradiating the laser beam Is formed so that it can be reproduced.

Thus, in this optical disk, the wobble signal W is set so that the signal level crosses zero at the timing corresponding to the bit boundary of the wobble data.
B is generated, and the groove is formed to meander by the wobble signal WB, so that the center of the groove crosses the track center at a timing corresponding to the bit boundary of the wobble data.

FIG. 5 is a block diagram showing an optical disk apparatus for accessing the optical disk manufactured as described above. In the optical disk device 10, a spindle motor 11 is driven by a clock C detected from the optical disk 12.
The optical disk 12 is rotationally driven so that K has a predetermined frequency.

The sled motor 14 moves the optical head 16 in the radial direction of the optical disk 12 under the control of the system control circuit 15, so that the optical disk device 10 can seek.

The optical head 16 irradiates the optical disk 12 with the laser beam L, and receives the laser beam L from the return light.
A push-pull signal PP whose signal level changes according to the displacement of the groove with respect to the laser beam irradiation position, and a focus error signal whose signal level changes according to the focus error amount are generated. At the time of reproduction, a reproduction signal RF whose signal level changes according to the amount of return light is generated. On the other hand, during recording, the light amount of the laser beam is intermittently started at a timing based on the clock CK,
Thereby, desired data is recorded.

The recording / reproducing circuit 17 reproduces the user data DU recorded on the optical disk 12 by processing the reproduced signal RF obtained from the optical head at the time of reproduction, and outputs it to an external device. At this time, the recording / reproducing circuit 17 outputs address data extracted from the reproduced signal RF to the address reading circuit 18.

The address reading circuit 18 analyzes the address data and detects the sector address SAD of the reproduced data. On the contrary, the address reading circuit 18
Under the control of the system control circuit 15, a sector address corresponding to the laser beam irradiation position is generated, and address data is generated from the sector address to generate the recording / reproducing circuit 1.
7 is output. At the time of recording, the recording / reproducing circuit 17 performs data processing on the user data DU input from the external device in a format suitable for recording on the optical disc 12, and inserts address data into a data string resulting from the data processing. Further, the optical head 16 is driven by the channel data generated in this manner to intermittently raise the light amount of the laser beam L, thereby recording the user data DU on the optical disc 12.

The system control circuit 15 is composed of a computer for controlling the operation of the entire optical disc apparatus 10. The system control circuit 15 controls the operation of the thread motor 14 and the like based on the sync number sync no and the track number track no obtained from the wobble signal processing circuit 13. By controlling the operation and switching the overall operation mode, the overall operation is controlled according to the laser beam irradiation position and further by control from an external device.

The wobble signal processing circuit 13 extracts a wobble signal WB from the push-pull signal PP and processes the wobble signal WB to detect a sync number sync no and a track number track no. At this time, the wobble signal processing circuit 13 detects a bit boundary of the wobble data WD, and outputs a gate signal GT centered on the bit boundary to the clock generation circuit 19.

The clock generation circuit 19 extracts the wobble signal WB from the push-pull signal PP and processes the wobble signal WB based on the gate signal GT output from the wobble signal processing circuit 13 to generate the clock CK. I do. In this embodiment, the optical disk device 10 generates a tracking error signal from the push-pull signal PP and controls the optical head 16 for tracking.

FIG. 6 shows the wobble signal processing circuit 13.
FIG. Wobble signal processing circuit 13
Inputs a push-pull signal PP to a band-pass filter (BPF) 23 via an amplifier circuit 22 having a predetermined gain.
Here, the band-pass filter 23 converts the push-pull signal PP from the frequency n + d [Hz / ch] to nd [Hz /
ch], thereby extracting a wobble signal WB (FIG. 7C) as shown in FIG. In this way, the wobble signal WB is band-limited by the band-pass filter 23, so that the jitter is alleviated as compared with the wobble signal WB generated when the master disc is created.

The phase comparison circuit (PC) 24 is constituted by an exclusive OR circuit, and compares the phase of the reference signal SWB output from the voltage control type oscillation circuit (VCO) 25 with the wobble signal WB. Output the result. The low-pass filter (LPF) 26 limits the band of the phase comparison result and outputs the low-frequency component to the voltage-controlled oscillation circuit 25. The voltage-controlled oscillation circuit 25 uses the output signal of the low-pass filter 26 to generate a reference signal SWB.
Variable. As a result, the phase comparison circuit 24, the voltage-controlled oscillation circuit 25, and the low-pass filter 26
An L circuit is configured to generate a reference signal SWB (FIG. 7D) synchronized in phase with the wobble signal WB.

The low-pass filter (LPF) 27 limits the band of the phase comparison result output from the phase comparison circuit 24 and outputs its low-frequency component. Comparison circuit (COM) 2
8 compares the output signal of the low-pass filter 27 with a predetermined reference level to generate a channel signal Sch whose signal level changes in accordance with an increase or decrease in the phase of the wobble signal WB (FIG. 7 (E)).

Here, the signal level of the channel signal Sch changes in accordance with the increase or decrease of the phase of the wobble signal WB, so that the signal level changes in accordance with the channel signal ch generated during the exposure of the master disc 2. Will do. However, this channel signal Sch
Is the wobble signal WB by the band-pass filter 23.
Is limited, and the PL
It is difficult to reproduce the timing of the edge of the channel signal ch correctly by obtaining the phase comparison result of the PLL circuit through the band limitation by the low-pass filter 27. The edge is reproduced with a change from the timing of the channel signal ch. However, at the timing corresponding to the bit boundary of the wobble data WD, correct phase information is detected (FIGS. 7A, 7B, and 7E).

The exclusive OR circuit 30 inputs the channel signal Sch directly to one input terminal and also inputs the channel signal Sch to another input terminal via a delay circuit 29, and outputs an exclusive OR signal of these two inputs. As a result, an edge detection signal SE (FIG. 7F) whose signal level rises at the timing of each edge of the channel signal Sch is output. Thereby, the exclusive OR circuit 30 detects the edge information of the channel signal Sch. Of the edge information detected here, the edge information corresponding to the bit boundary of the wobble data has the correct phase information.

The mono-multi vibrator (MM) 31
The edge detection signal SE1 (FIG. 7) in which the signal level rises for a predetermined period triggered by the edge detection signal SE.
(G)) is output.

The phase comparison circuit (PC) 32 compares the phase of the edge detection signal SE1 of the mono-multivibrator 31 with the oscillation output of the voltage-controlled oscillation circuit (VCO) 33, and outputs the phase comparison result. The low-pass filter (LPF) 34 outputs the result of the phase comparison in a band-limited manner.
The oscillation output CKE (FIG. 7 (H)) is output so as to be phase-synchronized with the edge detection signal SE1 with reference to the output signal of No. 4. Thereby, the phase comparison circuit 32, the voltage control type oscillation circuit 33, and the low pass filter 34 constitute a PLL circuit,
A clock CKE of the channel signal Sch including a large amount of jitter is generated based on the edge detection signal SE1.

As shown in FIG. 8, a flip-flop (F
F) 36 is a channel signal S generated by performing bi-phase mark modulation at the time of groove formation by sequentially taking in the channel signal Sch output from the comparison circuit 28 based on the falling timing of the clock CKE.
The logical level of the channel is reproduced (FIGS. 8A, 8B, and 8C).

The subsequent flip-flop (FF) 37 sequentially takes in the output data D3 of the flip-flop 36 on the basis of the falling timing of the clock CKE, and thereby outputs the output data D3 of the flip-flop 36 to the clock CKE. Output data D4 delayed by one cycle is generated (FIG. 8D).

The arithmetic circuit 38 compares the output data D3 and D4 of the two flip-flops 36 and 37 to detect a case where the same logic level is continuous in the channel signal Sch. That is, when the wobble data is phase-modulated when a groove is created, if the same logical level continues in the channel signal Sch, it is assumed that the boundary of the continuous channel corresponds to the bit boundary of the wobble data WD. Can be determined. Accordingly, the arithmetic circuit 38 detects the timing corresponding to the bit boundary of the wobble data WD on the basis of the continuation of the same logic level in the channel signal ch, that is, on the basis of the bit inversion of the wobble data.

As a result, the arithmetic circuit 38 outputs a reset signal RST to the counter (CNT) 39 at the detected timing (FIG. 8 (E)). Further, arithmetic circuit 3
8 is the output data D3 of the flip-flops 36 and 37
And D4 to perform a decoding process of the wobble data, and outputs a processing result DEC.

Here, the counter 39 is constituted by a binary counter which counts the falling of the clock CKE, is reset by a reset signal RST output from the arithmetic circuit 38, and raises the logic level of the output data EN ( FIG. 8 (F)). The counter 39 outputs the output data EN as an enable signal of the flip-flop 40 and outputs the output data EN to the clock generation circuit 19 as a gate signal GT (FIG. 8H).

The flip-flop 40 sequentially latches and outputs the output data DEC of the arithmetic circuit 38 at the rising timing of the clock CKE during the period in which the enable signal EN rises. As a result, the flip-flop 40 sequentially latches the decoding result DEC of the arithmetic circuit 38 at the correct timing and decodes the wobble data WD that is bit-synchronized (FIG. 8 (G)).

In this embodiment, the wobble signal WD is generated in the wobble signal processing circuit 13 by generating the wobble data WD so that the bit inversion is surely generated in the address data block. At least once for the data block, the channel signal ch in which the same logical level continues can be demodulated, whereby the wobble data WD that is bit-synchronized can be reliably demodulated.

FIG. 9 is a block diagram showing the wobble signal processing circuit 13 following FIG. In the wobble signal processing circuit 13, the shift register 45 has a 52-bit length obtained by adding the bit length of the sync number sync no to the block length of the address data block, and operates based on the enable signal EN and the clock CKE. As a result, as shown in FIG. 10, the sequentially demodulated wobble data WD is sequentially captured (FIG. 10).
(A)), and holds the latest 52-bit wobble data WD (FIG. 10B). Furthermore, the shift register 45
Outputs the held 52-bit wobble data WD by bit parallel.

The operation circuit 46 is provided with the shift register 45
It receives upper 4 bits and lower 4 bits of data from the output 52-bit parallel data, increments the lower 4 bits of data by 1 and compares it with the upper 4 bits of data. In this embodiment, the entire address data block is formed with a length of 52 bits, and the leading 4 bits have a sync number sync n
is assigned, and the sync number sync no is sequentially incremented, so that the arithmetic circuit 46 indicates that the sync number sync no appears in the upper 4 bits, and that the sync number is correctly updated from the immediately preceding sync number. Detect if it is.

When detecting the sync number sync no in this way, the arithmetic circuit 46 detects the sync number detection signal SY O
The signal level of K rises (FIG. 10C).

The dividing circuit 47 receives lower-order 48-bit data corresponding to one address data block from the 52-bit parallel data output from the shift register 45, and generates a generator polynomial G (X ) Divides the bit data corresponding to the sync number sync no, the track number track no, and the error detection code XCRCC, thereby executing the error detection processing. At this time, the division circuit 47 processes the bit corresponding to the error detection code XCRCC by inverting the logic level.

The comparison circuit (COM) 48 determines whether or not the division result of the division circuit 47 is a value 0. When the division result of the value 0 is obtained, the address data block detection signal CR
The signal level of COK rises (FIG. 10D).

Thus, the dividing circuit 47 and the comparing circuit 48
Detects the timing at which one address data block appears in the lower 48 bits of the 52-bit parallel data held in the shift register 45. In this case, if the address data block is detected at the correct timing in the continuous wobble data WD, this timing coincides with the timing of detecting the sync number sync no in the arithmetic circuit 46.

The NAND circuit 49 outputs the sync number detection signal S
Y OK and address data block detection signal CRC
When both the OK signal levels rise, a reset signal is output to the counter 50.

The counter 50 is constituted by a ring counter of a maximum value 47 for sequentially counting the clock CKE when the logic level of the enable signal EN is rising, and the count value is reset by a reset signal output from the NAND circuit 49. I do. Thus, the counter 5
0 indicates that the count value is circulated in units of one address data block in synchronization with the wobble data WD based on the sync number detection signal SY OK and the address data block detection signal CRC OK, and the count value is synchronized with the frame synchronization timing. Clear to value 0.

Further, the counter 50 operates the latch circuits 51 and 52 at a predetermined timing based on the count value.
Output a latch signal.

The latch circuit 51 inputs continuous 4-bit parallel data among the 52-bit parallel data output from the shift register 45. Further, the latch circuit 51 latches the parallel data based on the latch signal output from the counter 50, thereby detecting and outputting the sync number sync no.

Similarly, the latch circuit 52 inputs continuous 20-bit parallel data among the 52-bit parallel data output from the shift register 45. Further, the latch circuit 51 latches the parallel data based on the latch signal output from the counter 50, thereby detecting and outputting the track number track no.

FIG. 11 is a block diagram showing the clock generation circuit 19. This clock generation circuit 19 is connected to a band-pass filter (BP) through an amplification circuit 60 having a predetermined gain.
F) The push-pull signal PP is input to 61. Here, the band-pass filter 61 limits the push-pull signal PP by a band of frequencies n + d [Hz / ch] to nd [Hz / ch], thereby extracting the wobble signal WB.

The comparison circuit (COM) 62 binarizes the wobble signal WB based on a reference level of 0 level and outputs a binarized signal. The gate circuit 63 selects and outputs a binarized signal based on the gate signal GT, thereby extracting and outputting edge information at a timing corresponding to a bit boundary of the wobble data WD from the binarized signal. . As a result, the gate circuit 63 selects only correct phase information.

The phase comparison circuit (PC) 64 is constituted by an exclusive OR circuit, compares the frequency of the frequency-divided clock output from the frequency division circuit 65 with the output signal of the gate circuit 63, and compares the comparison result. Output. A low-pass filter (LPF) 66 limits the band of the phase comparison result, and converts the low-frequency component into a voltage-controlled oscillation circuit (VCO) 6.
7 is output. The voltage-controlled oscillation circuit 67 generates a clock CK by varying the frequency in accordance with the output signal of the low-pass filter 66, and the voltage dividing circuit 65 generates the clock CK.
Is divided by 1/4 and a divided clock is output.

Thus, the phase comparison circuit 64 and the frequency dividing circuit 6
5, low-pass filter 66, voltage-controlled oscillation circuit 67
Constitutes a PLL circuit and generates a clock CK which is phase-synchronized with the wobble signal WB. Then this PL
The L circuit generates the clock CK using only the correct edge information output from the gate circuit 63, thereby generating a clock CK with extremely high precision as compared with the related art.

In the above configuration, the mastering device 1
In FIG. 2 (FIG. 2), when a track is formed by irradiating the laser beam L spirally from the inner peripheral side to the outer peripheral side of the disk master 2, the laser is generated by the wobble signal WB generated by the wobble signal generation circuit 7. The beam irradiation position is displaced in the radial direction of the disk master 2, whereby the groove is formed to meander according to the wobble data.

At this time, in the mastering device 1, the track number track no whose value is sequentially incremented for each rotation of the disk master 2, and the sync number sync whose value is sequentially and cyclically incremented for each 1/16 rotation of the disk master 2.
No is generated, and an error detection code CRC in which the track number track no and the sync number sync no are set in the information word M (x) is generated (Equation (1)). Further, an error detection code XCRCC obtained by inverting all the bits of the error detection code CRC is generated, and these sync numbers sync no,
Reserved bits are allocated to the track number track no and the error detection code XCRCC to form an address data block (FIG. 1). Further, at this time, in the mastering device 1, the logical level of the reserved bit is set so that bit inversion always occurs once in one address data block.

In the mastering apparatus 1, the master disc 2
This address data block is sequentially generated in synchronism with the rotation of, and this address data block is input to the wobble signal generation circuit 7 as wobble data WD by a serial data string.

Here, the wobble data WD undergoes phase modulation in the phase modulation circuit 7C, and the wobble data W
A first reference signal whose frequency is set to be twice as high as the frequency of the clock CK of D;
The second reference signal that differs by 80 degrees is modulated into a channel signal ch that is sequentially switched according to the logical level of the wobble data WD.

Since the channel signal ch is obtained by phase modulation, the channel signal ch is generated so that the logical level of the channel before and after the bit center is inverted. When the wobble data WD is bit-inverted, the same logical level continues before and after the bit inversion. In this embodiment, the wobble data is generated such that the bit is inverted at least once in one address data block, so that the channel signal ch is located at the bit boundary of the wobble data WD for one address data block. At the corresponding timing, the same logic level is always generated at least once so as to be continuous.

The channel signal ch thus generated is subjected to frequency modulation in the frequency modulation circuit 7E, and a wobble signal WB, which is a modulated signal, is generated. As a result, in the mastering device 1, the wobble signal WB is generated only by the modulation signal according to the phase modulation rule.

At this time, the wobble signal WB has a frequency of 4 + 1/4 [Hz / ch] and 4-1 / 4 [H] for the logical 1 and 0 channels of the channel signal ch, respectively.
z / ch] is assigned and generated so as to cross zero at a timing corresponding to the bit boundary of the wobble data WD (FIGS. 3 and 4).

At this time, since the logical level of the channel signal ch is inverted with respect to the bit center, the frequency of one channel is further reduced to １ ／ [Hz / c].
h], the polarity of the modulated signal is inverted in each channel as needed, and the wobble signal WB always crosses zero at the timing corresponding to each bit boundary of the wobble data WD. And the signal level changes smoothly.

Thus, in the optical disk manufacturing process according to this embodiment, an optical disk is created from the master disk 2 by the mastering device 1 through a predetermined process, and in this optical disk, a wobble data bit boundary is formed. At the corresponding timing, the center of the groove is formed so as to cross the track center.

In this optical disc, in an optical disc apparatus, processing such as spindle control (in the case of CLV control) is performed based on the meandering of the groove generated as described above, and the wobble signal processing circuit 13 performs frame synchronization. Is detected (FIG. 5).

That is, the wobble signal processing circuit 13
(FIGS. 6 and 7), the wobble signal WB is extracted via the bandpass filter 23 from the push-pull signal PP whose signal level changes according to the laser beam irradiation position on the groove. The following phase comparison circuit 24, voltage control type oscillation circuit 25, low-pass filter 26
A reference signal SWB synchronized with the wobble signal WB is obtained by the PLL circuit according to the above. In the comparison circuit 28, based on the phase comparison result of the PLL circuit, correct phase information is obtained for the timing corresponding to the bit boundary of the wobble data. The held channel signal Sch is demodulated.

In the wobble signal processing circuit 13,
The edge information of the channel signal Sch is detected by the delay circuit 29 and the exclusive OR circuit 30, and the following phase comparison circuit 32, voltage control type oscillation circuit 33,
In the PLL circuit using the low-pass filter 34, a clock CKE of the channel signal Sch including a large amount of jitter is generated based on the edge information.

In the wobble signal processing circuit 13 (FIG. 8), the channel signal Sch output from the comparison circuit 28 is sequentially latched in the flip-flop 36 based on the clock CKE, so that each channel of the channel signal Sch is Is played. The reproduced data is transferred to the subsequent flip-flop 37, and the output data of the flip-flops 36 and 37 is output to the arithmetic circuit 3
By comparing at 8, the timing corresponding to the case where the same logic level continues, that is, the timing corresponding to the bit inversion in the wobble data WD is detected.

Based on the detected bit boundaries,
The clock C of the channel signal Sch is calculated by the counter 39.
By counting KE, bit boundaries in the wobble data are sequentially detected. Thus, in this embodiment, at least one address data block has one address data block.
In this case, the wobble data WD is set so that bit inversion occurs.
Is generated, the counter 39 is reset to the correct timing at least once for one address data block in the arithmetic circuit 38 as well. Therefore, even when the wobble signal waveform is disturbed due to detrack, track jump, or the like, the clock CKE with the correct timing can be quickly generated.

In the wobble signal processing circuit 13,
In accordance with the timing detected by the counter 39, the decoding result of the arithmetic circuit 38 is sequentially latched by the flip-flop 40, and the wobble data WD is decoded, thereby forming bit synchronization.

The counter 39 outputs a gate signal G corresponding to the timing of the bit boundary in the wobble data.
T is generated and output to the clock generation circuit 19.

Of the wobble data WD latched by the flip-flop 40 (FIG. 9), the latest 52 bits are held in the shift register 45, and the upper 4 bits and the lower 4 bits are compared in the arithmetic circuit 46. Then, the timing at which the sync number sync no appears in the upper four bits is detected. As a result, the optical disk device 1 detects frame synchronization without assigning a reference signal such as a synchronization pattern that violates the modulation rule to the wobble signal.

After the successive lower 48 bits are divided by the dividing circuit 47 from the latest 52 bits held in the shift register 45, the comparing circuit 48 determines whether or not the division result is a value 0. Thus, the timing at which one address data block appears in the continuous 48 bits is detected. Accordingly, the optical disk device 1 can detect the frame synchronization without assigning a reference signal such as a synchronization pattern that violates the modulation rule to the wobble signal.

Thus, in the optical disc apparatus 1, after the timing of the frame synchronization is detected twice, the counter 5 is output via the NAND circuit 49 based on the result of the double detection.
By resetting 0, false detection of frame synchronization is effectively avoided. Accordingly, the sync number sync stored in the shift register 45 is based on the detected timing.
No and the track number track no are taken into the latch circuits 51 and 52 and output to the system control circuit 15 and the like.

On the other hand, the clock generation circuit 19 (FIG. 1)
In 1), after the wobble signal WB is extracted from the push-pull signal PP by the band-pass filter 61, it is binarized by the comparison circuit 62, whereby the edge information of the wobble signal WB is detected. Only the correct edge information corresponding to the bit boundary of the wobble data WD is input to the subsequent phase comparison circuit 64 based on the gate signal GT detected by the wobble signal processing circuit 13, and the phase comparison circuit 64, etc. PLL by
In the circuit, the clock CK is generated based on the correct edge information.

As a result, in the optical disk device 10, the clock CK can be obtained with much higher precision than in the prior art.
Is generated. Further, since the wobble signal WB is generated only with the modulated signal that satisfies the modulation rule, in this embodiment, it is possible to obtain correct edge information without interruption at a fixed cycle, which also makes it possible to obtain the same as before. Then, the clock CK is generated with extremely high precision.

According to the above configuration, for wobble data obtained by detecting groove meandering, frame synchronization is detected from a result of comparison of predetermined bits, so that a wobble signal can be formed only by a modulation signal satisfying a modulation rule. Even in the case of generation, frame synchronization can be ensured. Therefore, the synchronization pattern is omitted, the wobble signal is generated only by the modulation signal in accordance with the modulation rule, and more correct edge information can be obtained in the optical disk device 10 correspondingly, and a clock with higher precision can be generated accordingly. . Also, the redundancy in the wobble signal can be reduced by omitting the synchronization pattern.

At this time, since the wobble signal is generated by allocating the error detection code, the frame synchronization can be detected by the error detection processing using the error detection code, and the erroneous detection of the frame synchronization can be effectively avoided. Can be.

Furthermore, the wobble data is generated by inverting the logical level of the error detection code and ensuring that the bit is inverted within one address block by using a reserved bit. Bit synchronization can be correctly performed based on the timing of (1).

In the above-described embodiment, a case has been described in which the bit inversion of the reserved bit is set so as to ensure that the bit is inverted within one address data block. However, the present invention is not limited to this, and the present invention is not limited to this. May be omitted according to the above. For example, if sufficient bit inversion always occurs for all combinations of track numbers and sync numbers assigned to the master disc, this can be omitted.

Further, in the above-described embodiment, the case where the error detection code is generated by inverting the error detection code CRC has been described. However, the present invention is not limited to this. If sufficient bit inversion always occurs for all combinations of numbers and sync numbers, the error detection code calculated from the generator polynomial may be directly recorded as necessary.

In the above-described embodiment, a case has been described in which a wobble signal is generated by allocating an error detection code. However, the present invention is not limited to this, and it is necessary to detect frame synchronization with practically sufficient reliability. If you can
The error detection code may be omitted. For example, a case where sufficient reliability can be ensured by comparing the track number and / or the sync number by repeating the same track number and / or the sync number a plurality of times or the like.

On the contrary, the reserved bits may be assigned to the bits for preventing erroneous detection, and the reliability of frame synchronization may be improved by using the bits for preventing erroneous detection. That is, in this case, all or a part of the track number and / or the sync number is assigned and compared with the original track number and / or the sync number, so that the reliability of the frame synchronization can be improved. At this time, the logic level of the erroneous detection prevention bit can be inverted to improve reliability. Further, in the error detection processing in the division circuit 47, the reliability can be improved even if a bit for preventing erroneous detection is set so that an error is detected at an erroneous timing.

Further, in the above-described embodiment, a case is described in which wobble data is generated by successive address data blocks so that track numbers and / or sync numbers change sequentially, and a wobble signal is generated by the wobble data. However, the present invention is not limited to this, and the same address data block may be repeated a predetermined number of times to generate a wobble signal.

In the above-described embodiment, the frequencies 4 + 1/4 [Hz / ch] and 4-1 / 4 [Hz / c] are applied to the logical 1 and 0 channels of the channel signal ch.
h] is assigned to generate a wobble signal. However, the present invention is not limited to this, and it is only necessary to generate a wobble signal so that zero crossing occurs at a bit boundary. Can be set variously, and if sufficient characteristics for practical use can be obtained, the wobble signal may be generated such that the signal level rapidly changes at the center of the bit.

Further, in the above-described embodiment, a case has been described in which wobble data is phase-modulated and then frequency-modulated. However, the present invention is not limited to this, and is widely applicable to frequency modulation instead of phase modulation. Can be applied. In this case, it is necessary to generate the wobble signal such that the center of the bit crosses 0 instead of the bit boundary according to the modulation rule.

In the above-described embodiment, the case has been described where the signal level of the wobble signal is set so as to cross the zero level at a predetermined timing. However, the present invention is not limited to this, and the present invention is not limited to this. , May be set to cross a certain reference level. That is, when a wobble signal is generated so as to always cross a certain reference level at a timing corresponding to a bit boundary or a bit center of wobble data, the phase of the wobble signal is held at a constant phase at the corresponding timing. Therefore, if the wobble signal is reproduced in consideration of the constant phase on the reproduction side, a clock with high accuracy can be generated with correct phase information, and the same effect as in the above-described embodiment can be obtained. By the way, in this case, the wobble signal is set to 2
This can be dealt with by changing the reference level of the comparison circuit to be converted into a value.

Further, in the above-described embodiment, the case where the entire groove is meandered by the wobble signal has been described. However, the present invention is not limited to this. It can be widely applied to meandering by a signal.

In the above embodiment, the wobble signal processing circuit 13 directly compares the phase of the wobble signal and then binarizes the phase comparison result to detect the phase information. Although the description has been given of the case where the phase information is detected by binarizing the wobble signal by the comparison circuit, the present invention is not limited to this, and can be widely applied to the case where the phase information is extracted by various methods as necessary. it can.

Further, in the above-described embodiment, a case has been described where frame synchronization is detected by comparing the sync number among the demodulated wobble data. However, the present invention is not limited to this. The frame synchronization may be detected by comparing the numbers, or may be combined with the detection of the frame synchronization based on the sync number. In these cases, a shift register having a longer bit length is required.

Further, in the above-described embodiment, a case where frame synchronization is detected by comparing a part of address data in two consecutive address data blocks has been described. However, the present invention is not limited to this. The frame synchronization may be detected by comparing all or a part of the address data with respect to three or more address data blocks. By doing so, the reliability can be further improved.

In the above-described embodiment, a case has been described in which edge information corresponding to a bit boundary of wobble data is extracted from a binary signal to generate a clock. However, the present invention is not limited to this. The present invention can be widely applied to a case where a clock is generated by directly extracting edge information corresponding to a bit boundary from a wobble signal.

Further, in the above-described embodiment, a case has been described in which a wobble signal is generated at frequencies n + d [hz / ch] and nd [Hz / ch]. However, the present invention is not limited to this, and separate timing The present invention can be widely applied to a case where a wobble signal is generated by inserting a reference signal for detection or the like.

In the above-described embodiment, the case where the wobble signal is generated by the address data based on the track number and the sync number has been described. However, the present invention is not limited to this, and the wobble signal is generated by the address data including the time information. It can be widely applied when generating.

Further, in the above-described embodiment, the case where the groove is meandered by the wobble signal has been described. However, the present invention is not limited to this. Can be widely applied when recording

In the above embodiment, the present invention is applied to a phase-change type optical disc.
The present invention is not limited to this, and write-once optical discs,
It can be widely applied to magneto-optical disks and the like.

[0128]

As described above, according to the present invention, first and second data strings are generated from a serial data string obtained by reproducing preformatted data, and the first and second data strings are generated. By detecting the address data preformatted on the optical disk based on the comparison result between the columns and detecting the timing of the frame synchronization, the frame synchronization can be reliably performed even when the preformat is performed only with the modulation signal that satisfies the modulation rule. can do.

[Brief description of the drawings]

FIG. 1 is a signal waveform diagram for explaining wobble signal generation according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a mastering device used for generating the wobble signal of FIG. 1;

FIG. 3 is a signal waveform diagram showing a relationship between a wobble signal and wobble data.

FIG. 4 is a signal waveform diagram showing a relationship between wobble data and a wobble signal different from the case of FIG.

FIG. 5 is a block diagram illustrating an optical disk device that accesses an optical disk manufactured by applying the mastering device of FIG. 3;

FIG. 6 is a block diagram showing a wobble signal processing circuit of the optical disk device of FIG.

FIG. 7 is a signal waveform diagram for explaining the operation of the wobble signal processing circuit in FIG. 6;

FIG. 8 is a signal waveform diagram showing a continuation of FIG. 7;

FIG. 9 is a block diagram showing a continuation of FIG. 6;

FIG. 10 is a signal waveform diagram for describing an operation of the wobble signal processing circuit in FIG. 9;

FIG. 11 is a block diagram illustrating a clock generation circuit of the optical disk device of FIG. 5;

FIG. 12 is a signal waveform diagram for describing bi-phase mark modulation.

FIG. 13 is a characteristic curve diagram for explaining groove generation.

FIG. 14 is a characteristic curve diagram for describing generation of a channel signal to which phase modulation is applied.

[Explanation of symbols]

1 Mastering device 2 Master disk 6
Wobble data generation circuit, 7 wobble signal generation circuit, 10 optical disk device, 12 optical disk,
13: Wobble signal processing circuit, 18: Clock generation circuit

Claims (20)

[Claims] 1. A method of manufacturing an optical disk, wherein predetermined serial data is preformatted on an optical disk, wherein said serial data is formed by at least address data comprising position information or time information, and a first standard is formed according to a predetermined modulation rule. Clock and second
The serial data is modulated by switching the reference clock to modulate the serial data, generating a modulated signal by frequency-modulating the modulation result of the serial data, and preformatting the modulated signal on the optical disc. A method for manufacturing an optical disk, comprising: recording the modulated signal on the optical disk; and generating the modulated signal only from a modulated signal according to the modulation rule. 2. The method according to claim 1, wherein the serial data is preformatted on the optical disk by meandering a groove according to the signal level of the modulated signal. 3. The method according to claim 2, wherein an error detection code of the address data is assigned to the serial data. 4. The method for manufacturing an optical disk according to claim 3, wherein a bit inversion bit is set in the serial data. 5. An auxiliary bit is assigned to the serial data, and when at least the other bits have the same logical level, the logical level of the auxiliary bit is set to a logical level different from the logical level of the other bits. 4. The method for manufacturing an optical disk according to claim 3, wherein the method is performed. 6. The method according to claim 3, wherein bits for preventing erroneous detection of the address data are assigned to the serial data. 7. The logic level of the bit for preventing erroneous detection is set to the same logic level as all or a part of the address data and the error detection code, or to an inverted logic level. Item 7. A method for manufacturing an optical disk according to Item 6. 8. In a serial data string obtained by demodulating the modulated signal, the same pattern as the address data and the error detection code is not detected at a location other than the location corresponding to the address data and the error detection code. 7. The method according to claim 6, wherein the logic level of the erroneous detection prevention bit is set as described above. 9. An optical disk on which predetermined serial data is recorded in a preformat, wherein said serial data is formed by address data comprising at least position information or time information, and said optical disk is provided with a first modulation rule according to a predetermined modulation rule. Reference clock and the second
The reference data is switched and the serial data is modulated, the modulation result of the serial data is frequency-modulated to generate a modulated signal, and the modulated signal is pre-formatted,
An optical disc, wherein the serial data is recorded, and the modulated signal is generated only from a modulated signal according to the modulation rule. 10. The optical disk according to claim 9, wherein a groove is formed to meander according to the signal level of the modulated signal, and the serial data is recorded. 11. The system according to claim 1, wherein said serial data has an error detection code for said address data.
The optical disc according to 0. 12. The optical disk according to claim 10, wherein a bit inversion bit is set in said serial data. 13. An auxiliary bit is assigned to the serial data, and when at least another bit has the same logical level, the auxiliary bit is set to a logical level different from the logical level of the other bit. The optical disk according to claim 10, wherein: 14. The optical disk according to claim 10, wherein bits for preventing erroneous detection of said address data are assigned to said serial data. 15. The logic level of the erroneous detection prevention bit is set to the same logic level as all or a part of the address data and the error detection code, or to an inverted logic level. The optical disc according to claim 14. 16. In the serial data string obtained by detecting the meandering of the groove, the same pattern as the address data and the error detection code is not detected at a location other than the location corresponding to the address data and the error detection code. 15. The optical disk according to claim 14, wherein the logic level of the bit for preventing erroneous detection is set as described above. 17. An optical disk apparatus for accessing an optical disk in which predetermined serial data is converted into a modulated signal and recorded in a preformat, wherein the modulated signal obtained from the optical disk is demodulated and a data sequence of a demodulation result is provided. Detecting the continuation of bits of the same logical level from the data string of the demodulation result, detecting the timing corresponding to the bit center of the serial data, or the timing corresponding to the boundary between the bits, A clock is generated from the modulated signal with reference to timing, and a first and second data sequence is generated from the data sequence of the demodulation result with reference to the detected timing, and the first and second data sequences are generated. A data string is sequentially updated with the data string of the demodulation result, and a comparison result is sequentially obtained between the first and second data strings. An optical disk device, wherein a timing at which address data assigned to the serial data is reproduced is detected based on the comparison result. 18. The optical disk device according to claim 17, wherein the modulated signal is reproduced from a meandering groove formed on the optical disk. 19. The optical disk apparatus according to claim 18, wherein whether the first data string is correct address data is determined based on an error detection code assigned to the serial data. 20. The optical disk device according to claim 18, wherein an erroneous detection of the address data is determined by a bit for preventing erroneous detection allocated to the serial data.