JPH10312050A - Photoreticle for production of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a photoreticle having plural kinds of basic resistance elements on one sheet of wafer without preparing plural conditions for ion implantation by forming the patterns of a semiconductor device from patterns varying in characteristics. SOLUTION: The photoreticle 3 is a multiimposition photoreticle having semiconductor chip patterns for 9 pieces and has respectively 3 pieces each of 3 kinds of mastarization type semiconductor chip patterns 4, 5, 6. The patterns are so formed in the patterns 4, 5, 6 that the basic resistance elements are formed of polysilicon. The patterns are so formed that the resistance values of the basic resistance elements are the largest with the patterns 4 and have the values smaller in order of the pattern 5 and the pattern 6. The semiconductor chip patterns 4, 5, 6 vary in the resistance values of the respective basic resistance elements in such a manner. Plural kinds of the basic resistance elements are thus obtd. on one sheet of the semiconductor wafer by using one sheet of the photoreticle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a photo reticle for manufacturing a semiconductor device, and more particularly to a photo reticle for manufacturing a master slice type semiconductor device having a plurality of semiconductor device patterns on one photo reticle.

[0002]

2. Description of the Related Art A semiconductor device is configured such that semiconductor elements such as a diode, a transistor, a resistor, and a capacitor are rationally arranged on a semiconductor wafer, and these are combined to function as an electric circuit. In order to form and bond the above-described elements on a semiconductor wafer, a diffusion layer forming pattern, a contact hole forming pattern, a wiring forming pattern, and the like are required. In order to form these patterns on a semiconductor wafer, a photomask or a photo reticle is used.

[0003] Methods for producing a pattern of a semiconductor device on a semiconductor wafer include a reduction projection exposure method, a contact exposure method, a reflection projection exposure method, and an electron beam direct writing method. Using a photo reticle,
In the case of manufacturing by a contact exposure method or a reflection projection exposure method, a photomask is used.

A method for manufacturing a photo reticle and a photo mask,
The method of transferring a pattern onto a semiconductor wafer by using them is described in detail in, for example, an introduction to new LSI engineering.

A method for manufacturing a photo reticle and a photo mask is as follows. First, a rectangular pattern of a semiconductor device is converted into digital data, and this pattern data is transferred as a chrome image onto a low expansion glass substrate to form a photo reticle. The pattern of this photo reticle is reduced to 1/5
Alternatively, the photomask is reduced to 1/10 and has the same pattern size as the pattern actually formed on the semiconductor wafer.

Conventionally, in a photo reticle used for manufacturing a semiconductor device, one (one imposition) or a plurality (multiple imposition) semiconductor chips are formed on one photo reticle on the same photo reticle. . In the case of a one-sided reticle, the pattern of the semiconductor chip is formed by repeating the exposure by repeating the exposure. If the number of repeats is large, the production efficiency is deteriorated. If a pattern of a plurality of semiconductor chips can be mounted on the photo reticle, a plurality of the same semiconductor chips are formed on one reticle (multi-layer reticle).

[0007] Among semiconductor devices, in particular, in a semiconductor device having an analog circuit mounted thereon, the manufacturing variation of the resistance value greatly affects the characteristics of the circuit. In a master slice equipped with an analog circuit, E is a sample for evaluating electrical characteristics.
When manufacturing an S (engineering sample), it is necessary to manufacture three types of semiconductor devices having large, medium, and small resistance values. Therefore, the three types of semiconductor devices may be mounted on one semiconductor wafer. is there.

[0008] This is to evaluate in advance the electrical characteristics of a product having a maximum value and a minimum value of the resistance to the manufacturing variation in consideration of the fact that the resistance value will change due to manufacturing variations when mass-produced products are manufactured in the future. This is because it is necessary. In that case, three types of dose amounts of ion implantation are performed, and semiconductor devices having three types of resistance values are formed on the same semiconductor wafer.

Here, with respect to a master slice on which an analog circuit is mounted, an example of the above-described conventional photo reticle and an example of a manufacturing method for forming three types of resistance values will be described with reference to the drawings.

FIG. 4 shows a photo reticle 1 showing a conventional example.
8 and chips 15, 16 and 17 that have been reduced projection exposed on a semiconductor wafer. In FIG. 4, the photo reticle 18 is a multi-faced photo reticle having a pattern of nine semiconductor chips. Also,
The photo reticle 18 has nine master slice type semiconductor chip patterns 19 each.
Here, in the pattern 19, a pattern is formed such that a basic resistance element is formed by a diffusion resistance. The semiconductor wafers 15, 16, and 17 form resistance elements by changing ion implantation conditions so that the resistance values of the basic resistance elements are different from each other.

As for a method of forming a semiconductor device having a plurality of characteristics with respect to the same semiconductor chip, a plurality of patterns may be formed on the same wafer in addition to the above-described method of changing the dose of ion implantation using a plurality of wafers. Japanese Patent Application Laid-Open No. 58-164218, Japanese Patent Application Laid-Open No. 56-32142, Nikkei Electronics 1989.10.2, Nikkei Electronics 19
No. 91.9.30 and Nikkei Electronics 199
There is an example described in 2.1.20.

The method of manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. 58-164218 discloses a method of manufacturing a semiconductor device by repeating a plurality of photo reticles 20 and 21 on a photomask 22 as shown in FIG. Create a pattern. Then, the photomask 2 thus created
2, a plurality of semiconductor devices are formed on a semiconductor wafer 23.

The technique disclosed in Japanese Patent Application Laid-Open No. 56-32142 relates to a reticle for producing a mask for pattern printing used in manufacturing a semiconductor integrated circuit by forming a plurality of types of patterns on one reticle. By repeating this, a plurality of semiconductor chip patterns are formed on the mask.

Nikkei Electronics 1989.10.2
The technology described in No. 1, Nikkei Electronics 1991.9.30, and Nikkei Electronics 1992.1.20 is based on a “sharing bus method” in which various types of semiconductor chips are simultaneously formed on a single semiconductor wafer. In this method, a plurality of circuit patterns are provided on one photo reticle.

[0015]

However, the first problem is that, in the case of the above-described conventional multi-faced photo reticle, only one kind of semiconductor device can be formed on the same wafer, and the efficiency is low in the case of multi-kind small-quantity production. Was bad. The reason is that only one semiconductor device pattern is formed on one photo reticle.

A second problem is that, when a plurality of types of ion implantation doses are prepared and semiconductor devices having different resistance values are mounted on a plurality of wafers, production management becomes complicated, and Production efficiency deteriorated. The reason is that the dose needs to be changed for each wafer, and the condition of changing the dose is accompanied.

A third problem is that of Japanese Patent Application Laid-Open No. 58-16 / 1983.
In the technology disclosed in Japanese Patent No. 4218 and Japanese Patent Application Laid-Open No. 56-32142, it is necessary to prepare a plurality of photo reticles. The reason is that, since this is a method of forming a pattern on a semiconductor wafer by a 1-time exposure method, it is necessary to prepare a plurality of photo reticles and use them to make a variety of photomasks. Further, in recent years, the reduced projection exposure method has become mainstream rather than the equal-size exposure method, and there has been a problem that it is not suitable for recent semiconductor device manufacturing methods.

The fourth problem is that Nikkei Electronics 1989.10.2.
No. 91.9.30 and Nikkei Electronics 199
The technique disclosed in No. 2.1.20 has a problem in that a photo reticle cannot be manufactured for a kind of semiconductor chip pattern for the purpose of varying manufacturing variations in resistance. The reason for this is a `` ride-and-go bus '' method in which semiconductor chips of various types of circuit configurations with different applications are formed on a single semiconductor wafer. This is because the system is not mounted on a photo reticle.

An object of the present invention is to improve the productivity in the manufacture of a semiconductor device. In a master slice type semiconductor device, a plurality of types of ion implantation are prepared on a single semiconductor wafer without preparing a plurality of conditions for ion implantation. It is another object of the present invention to provide a photo reticle for manufacturing a semiconductor device provided with the basic resistance element described above.

[0020]

In order to achieve the above object, a photo reticle for manufacturing a semiconductor device according to the present invention comprises:
A photo reticle for manufacturing a master slice type semiconductor device having a plurality of semiconductor device patterns on one photo reticle, wherein the patterns of the semiconductor device are patterns having different characteristics.

The pattern of the semiconductor device is a pattern in which only the resistance value of the basic resistance element differs.

The basic resistance element is made of polysilicon.

The basic resistance element has a different resistance value by changing any one of sheet resistance, resistance element width and resistance element length.

Further, among the patterns of the semiconductor device, those having a different pattern only in a specific element are included.

[0025]

The photo reticle according to the present invention has a plurality of basic resistive element patterns made of, for example, polysilicon in one photo reticle.

Therefore, a master slice type semiconductor device in which a plurality of types of basic resistive elements are formed on a single semiconductor wafer by using a single photo reticle is manufactured by processing by a reduced projection exposure method. can do.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a photo reticle for manufacturing a semiconductor device according to Embodiment 1 of the present invention and a reduced projection exposure on a semiconductor wafer using the photo reticle according to Embodiment 1 of the present invention. FIG.

In FIG. 1, the photo reticle 3 according to the first embodiment of the present invention is a multi-faced photo reticle having a pattern of nine semiconductor chips, and the photo reticle 3 is composed of three types of master slice type semiconductor chips. Each of the patterns 4, 5, and 6 has three patterns. Here, in the patterns 4, 5, and 6, a pattern is formed such that a basic resistance element is formed of polysilicon. The pattern is formed such that the resistance value of the basic resistance element is the largest in pattern 4 and then becomes smaller in the order of pattern 5 and pattern 6.

FIG. 2 is a diagram showing the pattern of the polysilicon resistive element in the semiconductor chip patterns 4, 5, and 6 in FIG.

The resistance pattern 7 shown in FIG.
Resistance element, resistance pattern 8 used for
Indicates a polysilicon resistance element used for the semiconductor chip 5, and a resistance pattern 9 indicates a pattern of the polysilicon resistance element used for the semiconductor chip 6, respectively.
The polysilicon resistance element has a through-hole part 10 and a resistance element part 11.

Generally, the resistance value of a polysilicon resistor is expressed by the following equation. R = σ × (L / W) Here, R is a resistance value, σ is a sheet resistance value, L is a resistance element length, and W is a resistance element width.

Therefore, the resistance patterns 7, 8,.
9, when the sheet resistance σ and the resistance element width W are the same, the lengths of a, b, and c corresponding to the resistance element length L are as follows: a>
Since b> c, the resistance value R is: resistance pattern 7> resistance pattern 8> resistance pattern 9. Here, the resistance element width W is, for example, 12 μm, and the sheet resistance σ is, for example, 34 μm.
The resistance element length L is 0 Ω / □, for example, 35 μm, and a value assuming the maximum and minimum manufacturing variations of the resistance value may be prepared.

As described above, the semiconductor chip patterns 4, 5, and 6 shown in FIG. 1 have different resistance values of the basic resistive elements, and are formed on one semiconductor wafer using one photo reticle. A master slice type semiconductor device having a plurality of types of basic resistance elements can be manufactured.

(Embodiment 2) FIG. 3 is a view showing a pattern of a polysilicon resistance element provided in a pattern of a photo reticle for manufacturing a semiconductor device according to Embodiment 2 of the present invention.

In the first embodiment shown in FIG. 2, the resistance element length L is changed as a means for changing the resistance value of the basic resistance element. However, in the second embodiment shown in FIG. 3, the resistance element width W is changed. .

The resistance patterns 12, 13, 14 shown in FIG.
In the above, if the sheet resistance σ and the resistance element length L are the same, the widths of a, b, and c corresponding to the resistance element width W are a <b.
Since b <c, the resistance value R is: resistance pattern 12> resistance pattern 13> resistance pattern 14.

The first and second embodiments of the present invention described above.
It goes without saying that the present invention can be similarly applied to the case where an element pattern of a type taking into consideration the maximum and minimum manufacturing variations is prepared not only for the polysilicon resistor but also for an element pattern at a specific location such as a gate of a MOS transistor. No.

[0039]

As described above, according to the present invention, a plurality of types of resistance elements can be formed without preparing a plurality of conditions for ion implantation. The reason is that the material of the resistance element is polysilicon.

Further, a level sample of the basic resistance element can be provided on one semiconductor wafer by using only one photo reticle. The reason for this is that a plurality of types of semiconductor chip patterns are provided on one photo reticle, and the patterns of the basic resistance elements of each semiconductor chip are different.

According to the present invention, not only a polysilicon resistor but also an element pattern of a type which takes into consideration the maximum and minimum manufacturing variations of an element pattern at a specific location such as a gate of a MOS transistor can be prepared. The same can be applied.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a conventional example.

FIG. 5 is a diagram showing a conventional example.

[Explanation of symbols]

1, 15, 16, 17, 23 semiconductor wafer 2 semiconductor chip 3, 18, 20, 21 photo reticle 4, 5, 6, 19 pattern of semiconductor device 7, 8, 9, 12, 13, 14 polysilicon basic resistance element Pattern 10 Through-hole pattern 11 Resistor pattern 22 Photomask

Claims (5)

[Claims] 1. A photo reticle for manufacturing a master slice type semiconductor device having a plurality of semiconductor device patterns on one photo reticle, wherein the semiconductor device patterns are patterns having different characteristics. A photo reticle for manufacturing a semiconductor device, comprising: 2. The photo reticle for manufacturing a semiconductor device according to claim 1, wherein the pattern of the semiconductor device is a pattern in which only a resistance value of a basic resistance element is different. 3. The photo reticle according to claim 2, wherein the basic resistance element is made of polysilicon. 4. The semiconductor according to claim 3, wherein the basic resistance element has a different resistance value by changing any one of a sheet resistance, a resistance element width, and a resistance element length. Photo reticle for manufacturing equipment. 5. The photo reticle for manufacturing a semiconductor device according to claim 1, wherein, among the patterns of the semiconductor device, those having different patterns only in specific elements are included.