JPH10311867A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which, with almost no increase in the number of external terminals, can easily inspect an analog circuit part which is built into the semiconductor device. SOLUTION: An inspection signal SA generated by a microprocessor 4 and changed in level by a level changing circuit 10 is input to an analog circuit part 6 by a switching circuit 12 in place of an analog signal Ain from an external terminal Tai, and a determining circuit 14 which determines whether or not the level of an output signal Ao from the analog circuit part 6 is within the normal range is made to hold its determination signal SR at a predetermined timing, so that inspection of the analog circuit part 6 can be performed automatically only inside a semiconductor device 2 under control of the microprocessor 4. Therefore, inspection of the analog circuit part 6 can be performed easily, and since the output of the analog circuit part 6 does not need to be taken out, almost no increase is required in the number of external terminals of the semiconductor device 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a digital circuit portion and an analog circuit portion are mixed, and more particularly to a semiconductor device having a self-test function.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device having a built-in digital circuit, an inspection method for autonomously inspecting the built-in circuit in the semiconductor device has been known. (Built-in self-test).

For example, Japanese Patent Application Laid-Open No. 2-38879 discloses a pattern generating circuit for generating a test pattern such as a pseudo-random pattern to be input to a circuit to be tested, a circuit for generating a test pattern, and the like. An apparatus having an error detection circuit for detecting and holding an error in an output pattern from a device is disclosed. Japanese Unexamined Patent Application Publication No. 3-59478 discloses a signature for compressing and storing an output pattern instead of an error detection circuit. An apparatus with a circuit is disclosed. In these devices, instead of supplying a test pattern from the outside and observing the output of the circuit under test, a test pattern is generated inside the semiconductor device by a pattern generation circuit, and the output of the circuit under test is determined or Only the processed result is output to the outside or stored in a memory area that can be read from the outside.

If the input / output of the result of this determination or processing and the start command to the pattern generation circuit is performed through an external terminal or the like used as a general-purpose input / output port, an external terminal dedicated to inspection is provided. In other words, the internal circuit can be inspected without increasing the size of the semiconductor device package determined by the number of external terminals.

In recent years, with the advance of semiconductor device manufacturing technology, digital circuits and analog circuits have been integrated into one semiconductor device, and therefore, it is necessary to test not only digital circuits but also analog circuits. Is growing.

[0006]

However, in an analog circuit, even if a test pattern such as a pseudo-random pattern generated by a pattern generation circuit is input, the output does not become a digital signal, and furthermore, a failure occurs in the output in a random pattern. Since it does not always appear, the inspection circuit used for the digital circuit as described above cannot be applied as it is.

In such a semiconductor device, an analog signal input from the outside and processed by an analog circuit section is usually subjected to A / D conversion by an A / D converter built in the semiconductor device. Since the processing is performed by the digital circuit section, it is often unnecessary to connect the output of the analog circuit section to an external terminal.

That is, in a semiconductor device having a built-in analog circuit section, an extra external terminal for taking out the output of the analog circuit section which is not necessary during normal operation must be provided only for testing the analog circuit section. In addition, when there are a large number of analog circuit sections to be inspected, there is a problem that the package of the semiconductor device is enlarged. In addition, the analog circuit section must be inspected manually by supplying analog signals to the analog circuit section using an expensive analog tester and observing the output from an external terminal for inspection. In addition, there is a problem that the inspection requires time and effort.

[0009] In addition, "DESIGN FOR TESTABILITY OF A MU
DULAR, MIXED SIGNAL FAMILY OF VLSI DEVICES "(IEEE
INTERNATIONAL TEST CONFERENCE 1993 p.797-p.804)
Is provided with a scan circuit for generating various digital data and a D / A converter for converting the data generated by the scan circuit into an analog signal, so that various internal terminals can be provided without increasing the number of external terminals. Although a device capable of generating an analog signal is disclosed, in this device, it is necessary to provide a D / A converter only for testing an internal circuit, and the configuration for performing the test is increased in size. There was a problem that would.

[0010] The present invention has been made in order to solve the above problems.
An object of the present invention is to provide a semiconductor device capable of easily inspecting an analog circuit portion built in the semiconductor device without increasing the number of external terminals.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device according to the first aspect of the present invention, wherein when the analog section inspection control means activates the inspection signal generation means, the inspection signal generation means is activated. Generates a binary level test signal in time series, and the signal switching means inputs the test signal to an analog circuit unit instead of an analog signal input via an external terminal.

In the analog circuit section, a certain causal relationship represented by a transfer function is generally established between an input signal and an output signal, and an output signal is uniquely determined for a predetermined input signal. In particular, when the analog circuit section includes an integrator or the like that is affected not only by the present input but also by the past input, the output signal is a series of input signals (for example, binary signals generated in time series). Level test signal).

Therefore, the analog section inspection control means determines whether or not the signal level of the output of the analog circuit section is within a predetermined normal range after the preset measurement time has elapsed. The result of the determination is fetched and stored in the data storage means from which the stored content can be read via the external terminal group.

That is, if the operation of the analog circuit section is normal, the normal range used by the judgment means can be set near the signal level at which the output of the analog circuit section should be at the end of the measurement time. Thus, the normal / abnormal state of the analog circuit can be determined. As described above, according to the semiconductor device of the present invention, the self-inspection of the analog section can be easily performed only by activating the analog section inspection control means, and the inspection result is stored in the data via the external terminal group. It can be easily obtained by reading the storage contents of the means.

In addition, by using a binary signal as a test signal and storing a result of determining whether or not the output signal is within a normal range as a test result, the test of the analog circuit section can be performed by a digital signal. , It is not necessary to add a complicated circuit such as a DA converter, and the configuration for inspecting the analog circuit unit can be reduced in size.

The test signal generating means includes, for example, a signal generating data storing means for storing signal generating data corresponding to the signal level of the test signal for each preset unit time. A data reading means for reading the signal generation data stored in the signal generation data storage means for each unit time, and converting the signal generation data read by the data reading means into a predetermined signal level to generate an inspection signal. And level conversion means.

Next, in the semiconductor device according to the third aspect,
The digital part inspection means self-inspects the digital circuit section for abnormalities. As a result, if the digital circuit part is normal, the analog part inspection activation means activates the analog part inspection control means. Note that the digital circuit unit is configured by a microprocessor that executes processing according to a preset program, and the digital unit inspection unit, the analog unit inspection start unit, and the analog unit inspection control unit are executed by a microcomputer. It is implemented as a process.

That is, after it is confirmed that the digital circuit section operates normally, the inspection of the analog circuit section is performed by controlling the digital circuit section whose operation has been confirmed, so that the reliability of the inspection of the analog circuit section is improved. Can be done. Also, in order to activate the analog part inspection control means,
Since there is no need to give a special command from the outside, the number of external terminals does not increase, and it is possible to contribute to miniaturization of the package of the semiconductor device.

However, the analog section inspection control means may be configured to be activated when a predetermined activation signal is input via an external terminal group. In this case, it is possible to arbitrarily inspect only the analog circuit section.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of a semiconductor device (LSI) 2 of the present embodiment in which a digital circuit and an analog circuit are configured to coexist on one chip and used for an electronic control unit (ECU) of a vehicle. It is a block diagram.

As shown in FIG. 1, a semiconductor device 2 of this embodiment includes a microprocessor 4 as a digital circuit for processing a digital signal, an analog circuit 6 including a noise filter for an analog signal, and the like. A / D converter 8 which converts analog signal Ao output from section 6 into digital signal Dc and inputs it to microprocessor 4
And the inspection signal sa output from the microprocessor 4
A level conversion circuit 10 for converting to a predetermined signal level, an analog signal Ain input via an external terminal Tai, or a level-converted test supplied from the level conversion circuit 10 in accordance with a selection signal CS from the microprocessor 4 A switching circuit 12 for supplying one of the signals SA to the analog circuit section 6 and determining whether or not the output level of the analog circuit section 6 is within a predetermined normal range;
And a determination circuit 14 for holding the determination signal SR in accordance with the hold signal CH from the CPU 4 and inputting the stored determination signal SR to the microprocessor 4.

Note that the semiconductor device 2 has an analog signal Ain
A general-purpose IO for inputting / outputting various data to / from the microprocessor 4 in addition to an external terminal Tai for inputting
An external terminal Tpb used as a port, an external terminal Tmd for inputting a mode selection signal MD used when testing an internal circuit of the microprocessor 4, and a start-up for starting a self-test of the analog circuit unit 6 described later. An external terminal Tat for inputting the signal AT is provided. Usually, the external terminal Tpb is connected to an external memory such as an optional EEPROM or used as an input / output terminal for a serial communication function.

FIG. 2 is a block diagram showing a detailed configuration of the microprocessor 4. As shown in FIG. 2, the microprocessor 4 includes a CPU 16 that executes processing according to a program, a ROM 18 that stores a program and data necessary for operating the CPU 16,
6, a RAM 20 for temporarily storing the calculation result of
An I / O circuit 22 for inputting / outputting various signals to / from the outside of the microprocessor 4;
A timer 24 for generating an interrupt signal IT for U16,
A limiting circuit 30 for limiting access from the CPU 16 to the ROM 18 according to a mode selection signal MD input via the external terminal Tmd.

The CPU 16 has two data buses and an address bus. A ROM 18, an I / O circuit 22, and a limiting circuit 30 are connected to the first data bus 26 and the first address bus 28. The RAM 20 and the timer 2 are connected to the second data bus 27 and the second address bus 29, respectively.
4 are connected. This means that the next instruction to execute is RO
This is to enable the previously read instructions to be executed simultaneously while reading from M18. CPU 16
Has registers A to E that can be used for arbitrary purposes and a register F that is used as a flag TFLAG indicating the execution state of a self-test process described later.

In the I / O circuit 22, the digital signal PB input / output to / from the outside of the semiconductor device 2 via the external terminal Tpb, the inspection signal sa output to the level conversion circuit 10, the determination circuit 14 Judgment signal SR input from the
Digital signal Dc from A / D converter 8, switching circuit 12
Switching signal CS for controlling the determination signal SR
, A start signal AT input via the external terminal Tat, and the like. These signals are sent to the CPU 16 without passing through the I / O circuit 22.
May be configured to be directly input / output to / from the server.

Furthermore, in the ROM 18, in addition to the program for executing the processing that the semiconductor device 2 of the present embodiment should perform, the program for the self-test processing described later, and the analog circuit section 6 in the self-test processing are checked. In this case, signal generation data and the like used for the operation are stored. When the mode signal MD is input, the limiting circuit 30
When the PU 16 accesses an area other than the area where the self-inspection processing program and the signal generation data are stored, the access to the ROM 18 by the CPU 16 is restricted so that the external terminal Tpb is accessed. That is, when the CPU 16 attempts to read the command or data from the ROM 18 while the mode signal MD is being input, it actually reads from the external terminal Tpb.

FIG. 3 is a circuit diagram showing a detailed configuration of the level conversion circuit 10. As shown in FIG. As shown in FIG. 3, the level conversion circuit 10 includes a pair of voltage dividing resistors R1 and R2 connected in series to divide the power supply voltage VDD between the power supply voltage VDD and the ground voltage GND.
And an analog switch SW that turns on when the inspection signal sa from the microprocessor 4 is at the high level and supplies the divided voltage Va by the voltage dividing resistors R1 and R2 to the switching circuit 12.
1 and an inspection signal sa from the microprocessor 4 is applied via an inverting circuit NOT, and is turned on when the inspection signal sa is at a low level to supply the ground voltage Vb (= GND) to the switching circuit 12. It is composed of

That is, the level conversion circuit 10 converts the high level of the test signal sa supplied from the microprocessor 4 into a voltage Va and the low level into a voltage Vb, and converts the level-converted test signal SA into a switching circuit. 12. Next, FIG. 4 is a circuit diagram illustrating a detailed configuration of the determination circuit 14.

As shown in FIG. 4, the determination circuit 14 includes three voltage-dividing resistors R3 to R5 connected in series to divide the power supply voltage VDD between the power supply voltage VDD and the ground voltage GND, and an inverting input terminal (-). The output signal Ao of the analog circuit section 6 is applied to
A voltage comparator 32 having a non-inverting input terminal (+) applied with a divided voltage (hereinafter, referred to as a comparison voltage) VH at a connection point of the resistors R3 and R4, and an output of the analog circuit section 6 having an inverting input terminal (-). A voltage comparator 34 to which a signal Ao is applied and a divided voltage (hereinafter referred to as a comparison voltage) VL at a connection point of the resistors R4 and R5 is applied to a non-inverting input terminal (+), and both voltage comparators 32 and 34 AND circuit A for calculating the AND of the output levels of
ND and the output of the AND circuit AND are held by a holding signal CH from the microprocessor 4, and the determination signal SR
Register circuit 3 for outputting to microprocessor 4
6.

That is, in the judgment circuit 14, the AND circuit AN
In response to the output signal Ao of the analog circuit section 6, the output of D becomes High level when the output signal Ao is higher than the comparison voltage VL and lower than the comparison voltage VH, and otherwise becomes Low level. Holds the output level of the AND circuit AND at the time when the holding signal SR is input as the determination signal SR.

The comparison voltages VL and VH are appropriately set according to the circuit configuration of the analog circuit section 6 and the pattern of the test signal sa (SA). Next, the self-inspection processing executed by the CPU 16 will be described with reference to the flowchart shown in FIG.

When this process is started, first, in step (hereinafter simply referred to as S) 210, a ROM inspection process described later is executed, and in subsequent S220, the result of the ROM inspection process is stored in the registers C and E. Values RC, RE (hereinafter, referred to as
Similarly, it is determined whether the ROM 18 is normal based on the values of the registers A to E as RA to RE.
If E ≠ RC), the present process is terminated. On the other hand, when it is determined that the ROM 18 is normal (RE = RC), the process proceeds to S230, and after executing an analog part inspection process described later, the process ends.

Next, the ROM executed in S210
The inspection process will be described with reference to the flowchart shown in FIG. In the ROM inspection process, data read from the ROM 18 are logically operated one after another according to a predetermined primitive polynomial to calculate a data-compressed value called a signature. The presence or absence of an abnormality is determined based on whether or not the value matches the determined value. Note that this signature is a well-known one described in detail in, for example, Japanese Patent Application Laid-Open No. 3-59478. Therefore, further detailed description is omitted, but here, the calculation of the signature is performed by hardware instead of hardware. Register E corresponds to the linear feedback register (LFSR), and register D corresponds to the LFS
This corresponds to a parallel input to R.

During the execution of this processing, the mode setting signal M is set so that an arbitrary area of the ROM 18 can be accessed.
D shall be invalidated. As shown in FIG. 7, when this processing is started, first, in S310, the flag TFLAG is set to 1 to indicate that the inspection processing is being executed, and in S320, the registers A, Inspection parameters are set in B, C, and E. Specifically, the start address of the ROM 18 is set in the register A, the end address of the ROM 18 is set in the register B, the expected test value is set in the register C, and the signature initial value is set in the register E.

At S330, the value RA of the register A is
Is used as an address, data is obtained from the ROM 18 and stored in the register D. In the following S340, the registers D, E
The signature calculation is executed between the values RD and RE stored in the register E, and the calculation result is stored in the register E. Further S35
At 0, the value RA of the register A is updated by incrementing the value, and the value RA of the register A is set to the ROM address from which data is to be read next, and the process proceeds to S360.

In S360, the values RA,
By comparing the RB, that is, the address of the ROM 18 from which the data is to be read next, with the end address of the ROM 18, it is determined whether or not the signature calculation for all the data stored in the ROM 18 has been completed. If (RA ≦ RB), the processes of S330 to S350 are repeatedly executed. On the other hand, in S360, the signature calculation has been completed for all data (RA> R
When it is determined to be B), the present process ends.

That is, when this processing is executed, a value obtained by performing a signature operation on all data stored in the ROM 18 is stored in the register E. Therefore, the previous S2
20 compares the operation result RE of the signature stored in the register E with the inspection expected value RC set in the register C, and if these values are equal (RE =
(RC) ROM 18 is determined to be normal, and if not equal (RE @ RC), it is determined that ROM 18 is abnormal.

Next, the analog part inspection processing executed in S230 will be described with reference to the flowchart shown in FIG. In the analog part inspection processing, a binary level (Va, Vb) inspection signal SA is given to the analog circuit part 6 in time series according to preset signal generation data, and the signal level of the output signal Ao is set to a predetermined level. Within normal range (VL ≦
Ao ≦ VH).

When executing this processing, the register E
Stores the signature operation value which is the processing result of the ROM inspection processing executed in S210.
This processing is configured to be executed without using the register E. When this processing is started, first, in S4
At 10, the flag TFLAG is set to 1 to indicate that the inspection process is being executed, and at S420, parameters for inspection are set in the registers A and B. Specifically, the start address of the area where the signal generation data is stored is set in the register A, and the end address of the area is set in the register B.

Then, in S430, the value RA of the register A is
, The signal generation data is obtained from the ROM 18 and stored in the register C. In subsequent S440, the value RA of the register A is incremented and updated so that the value RA of the register A becomes the address where the signal generation data to be read next is stored. Furthermore,
In S450, the value RD of the register D used as a data counter is cleared to 0, and the process proceeds to S460.

In S460, a switching signal CS is output, and
The test signal SA from the level conversion circuit 10 is set so as to be supplied to the analog circuit unit 6. In the subsequent S470, the CPU 16 itself is set so that the timer 16 receives the timer interrupt signal IT from the timer 24. 24 sets and starts the timer 24 so as to periodically (time interval T) generate the timer interrupt signal IT.

Thereafter, the timer interrupt signal IT causes C
In the PU 16, a timer interrupt process described later is executed every predetermined time T. Here, the timer interrupt processing is shown in FIG.
This will be described along the flowchart shown in FIG. When the present process is started, first, in S610, a portion other than the most significant bit (MSB) of the signal generation data stored in the register C is masked, and in subsequent S620, I is set according to the value of the masked signal generation data. The test signal sa is generated by setting the output of the / O circuit 22. That is, if the MSB is 1, the high level is set, and if the MSB is 0, the low level is set. The I / O circuit 22 keeps holding the set signal level until it is reset.

At S630, it is determined whether or not the value RD of the data counter (register R) is equal to or greater than the number of bits N (8 in this embodiment) of the register RC. Then, the value RD of the data counter is incremented and updated, and in step S650, the value RC of the register C in which the signal generation data is stored is shifted by one bit toward the MSB, and then the present process is terminated. .

On the other hand, if it is determined in step S630 that the value RD of the data counter is smaller than the number N of bits of the register C, the process proceeds to step S660. Thereafter, S660 to S6
At 80, the signal generation data is acquired, the signal generation data address is updated, the data counter is cleared, and the present process is completed, just like S430 to S450.

That is, when the analog part inspection processing is executed,
By the timer interrupt processing, the value of each bit of the signal generation data set in the register C is sequentially output as the check signal sa from the MSB side, and the value of each bit is held for each timer interrupt period T And as a result,
The test signal sa is as shown in FIG. 10A, and the output signal Ao of the analog circuit unit 6 to which the test signal SA whose level has been converted by the level conversion circuit 10 is input is
For example, it is as shown in FIG. FIG. 10A shows an example in which the test signal sa is generated from time t0 with n-bit signal generation data of 11010... 01.

Here, returning to the analog part inspection processing of FIG. 8, in step 480, it is determined whether or not the processing has been completed for all the signal generation data. This is determined by determining whether the value RA of the register A indicating the address where the signal generation data to be read next is stored is greater than the value RB of the register B indicating the end address of the same area. If the value is equal to or less than the value of the register RB (RA ≦ RB), this step is repeatedly executed to wait, and the value RA of the register A is greater than the value RB of the register B (RA> R
If determined as B), the flow shifts to S490, where the CPU 16
CPU 16 does not accept timer interrupt signal IT.
By setting itself and stopping the timer 24, the timer interrupt processing is set so as not to be activated, and the generation of the inspection signal sa is terminated.

In S500, the holding signal CH is output to the judgment circuit 14, and the judgment signal S is sent to the judgment circuit 14.
After holding R, in S510, the held determination signal SR is fetched and set in the register C. Further S
At 520, the switching signal CS is output, and the analog signal Ain input via the external terminal Tai is input to the analog circuit unit 6
In step S530, the flag TFLAG is cleared to 0 to indicate that the inspection process has been completed, and then the present process is terminated.

That is, when the analog section inspection processing is executed, the signal level of the output signal Ao when the inspection signal SA is input to the analog circuit section 6 is within the normal range (VL ≦ Ao ≦ V
H) is stored in the register C. As a result, at the end of the self-inspection processing (see FIG. 6A), the result of the signature calculation by the ROM inspection processing is set in the register E, and the determination result by the analog section inspection processing is stored in the register C. Become.

In the self-check process, the flag TFLA
G sets a flag when the ROM inspection processing is executed or the analog section inspection processing is executed (TFLAG ← 1).
Is cleared when the analog part inspection is completed (TFL
AG ← 0), and if an abnormality is found in the ROM inspection, the processing is terminated without executing the analog part inspection processing. Therefore, the external terminal Tp
By reading the contents of the flag TFLAG via the CPU, it is possible to know whether or not the self-test has been completed normally (TFLAG = 0), and after a lapse of a predetermined time sufficient to execute the self-test process. Flag is also set (TFLA
If G = 1), it is possible to know that an abnormality has occurred in the ROM inspection.

Next, the periodic processing executed by the CPU 16 will be described with reference to the flowchart shown in FIG. Note that this periodic process is configured as an interrupt process that can be executed by causing the timer 24 to periodically output a timer interrupt signal different from the above-described timer interrupt signal IT. In addition, unlike the self-test process, this periodic process may be stored in an area where access is restricted by the restriction circuit 30.

As shown in FIG. 6B, when the present process is started, first, in S240, it is determined whether or not the start signal AT is input via the external terminal Tat. This processing ends as it is. On the other hand, if it is determined that the activation signal AT has been input, the flow shifts to S250, where the analog section inspection processing is executed in exactly the same manner as in S230, and this processing ends. That is, when this processing is enabled, it is possible to arbitrarily execute only the analog part inspection processing by inputting the activation signal AT.

Next, in the semiconductor device 2 configured as described above, an inspection procedure for inspecting the internal circuit, in particular, the microprocessor (digital circuit section) 4 and the analog circuit section 6, will be described with reference to a flowchart shown in FIG. It is explained along. First, in S110, the microprocessor 4
A function inspection (digital part inspection A) 110 for inspecting the function of (1) is executed.

In this function inspection, the external terminal T
When the mode selection signal MD is input from md, the CPU 16
The instruction and data are set so as to be read from the external terminal Tpb instead of the ROM 18, and the instruction is directly input to the CPU 16 from a digital tester or the like connected to the external terminal Tpb. The content of the instruction input via the external terminal Tpb is, for example, that various operations are executed using the registers A to F in the CPU 16 and the operation results are output to the external terminal Tpb.
output through the external terminal Tpb.
It is determined whether or not the function is normal.

After the inspection of the CPU 16 as described above,
Similarly, a command is directly input to the CPU 16 via the external terminal Tpb, and this time, the RAM 20, the I / O circuit 22, the timer 2
4 is read and written to C
By causing the PU 16 to execute and outputting the result via the external terminal Tpb, these peripheral circuits 20, 22, 2
Test 4 is performed.

If the results of these tests are all normal,
Proceeding to the next S120, the CPU 16 activates the self-inspection process. This is performed by inputting, from the external terminal Tpb, a command for setting the head address where the self-test processing program is stored in the program counter. As described above, the self-inspection processing program is stored in the area where the access to the ROM 18 is not restricted by the restriction circuit 30, so that when this instruction is input, the CPU 1
In step 6, the self-inspection process is read out sequentially according to the setting of the program counter, and the above-described self-inspection process is executed.

In the following S130, the process stands by until the self-inspection process started in S120 is completed.
The inspection result stored in the registers C and E inside the U16 is read out via the external terminal Tpb, and the inspection is completed by confirming the inspection result.

As described above, in the semiconductor device 2 of the present embodiment, the microprocessor 4 generates the binary-level test signal sa in time series, and outputs the level-converted test signal SA to the analog circuit section. 6 and an output signal Ao from the analog circuit unit 6 at a predetermined timing.
The analog circuit 6 is inspected by determining whether or not the signal level is within the normal range, and the microprocessor 4 takes in the determination result.

Therefore, according to the semiconductor device 2 of the present embodiment, the inspection of the analog circuit section 6 is performed by the microprocessor 4
Can be automatically performed only inside the semiconductor device 2, so that the inspection of the analog circuit section can be easily performed. Further, since it is not necessary to input an analog signal for inspection from outside the semiconductor device 2 using an analog tester or the like and to take out the output of the analog circuit section 6 to the outside, almost no external terminals of the semiconductor device 2 are used. Since there is no increase, and no complicated circuit such as a DA converter is used, the configuration for testing the analog circuit section 6 can be minimized.

Further, in the semiconductor device 2 of this embodiment, RO
Since the signature calculation at the time of the M inspection process is performed according to the program stored in the ROM 18 using the register in the CPU 16, there is no need to provide special hardware for the signature calculation, and the ROM 18 (digital circuit unit) is not required. The configuration for performing the inspection can be minimized.

Further, in the semiconductor device 2 of this embodiment, RO
As a result of the M inspection processing, the analog part inspection processing is performed only when there is no abnormality in the ROM 18, that is, only when it is confirmed that there is no abnormality in the microprocessor 4 that controls the analog part inspection processing. Therefore, the analog part inspection processing is not performed wastefully, in other words,
The reliability of the inspection result of the analog part inspection processing can be improved.

Further, in the semiconductor device 2 of this embodiment,
Since only the analog section inspection processing is started by inputting the activation signal AT to the external terminal Tat, only the analog circuit section 6 can be arbitrarily inspected. As mentioned above, although one Example of this invention was described, this invention is not limited to the said Example, It can implement in various aspects.

For example, in the above embodiment, each bit of the signal generation data for generating the inspection signal sa corresponds to the signal level for each unit period T, and this signal generation data is stored in the ROM 18 in its original form. The signal generation data is compressed and stored in the ROM 18, and the RO is stored.
When generating the inspection signal sa by reading from the M18, it may be configured to expand to the original data. In this case, the storage area for the signal generation data can be reduced, and the configuration for inspection can be made smaller.

In the above-described embodiment, the flag TFLAG indicating whether or not the inspection has been normally completed is provided. However, by reading the contents of the registers C and E, the inspection result can be known. Is not always necessary and may be omitted. Further, in the above embodiment, the external terminal Tat for inputting the activation signal AT for activating the self-test of the analog circuit unit 6 is provided to execute the periodic processing. It may be omitted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a semiconductor device according to an embodiment.

FIG. 2 is a block diagram illustrating a detailed configuration of a microprocessor.

FIG. 3 is a circuit diagram illustrating a detailed configuration of a level conversion circuit.

FIG. 4 is a circuit diagram illustrating a detailed configuration of a determination circuit.

FIG. 5 is an inspection flowchart showing an entire inspection procedure.

FIG. 6 is a flowchart of a self-inspection process and a periodic process executed by a microprocessor.

FIG. 7 is a flowchart illustrating a ROM self-test process executed in step 210 of the self-test process.

FIG. 8 is a flowchart showing an analog part inspection process executed in step 230 of the self-inspection process and step 250 of the periodic process.

FIG. 9 is a flowchart illustrating a timer interrupt process executed together with the analog unit inspection process.

FIG. 10 is an explanatory diagram illustrating an inspection signal generated during an analog unit inspection process and an output signal from an analog circuit unit.

[Explanation of symbols]

2 ... Semiconductor device 4 ... Microprocessor 6
... Analog circuit section 8 ... A / D converter 10 ... Level conversion circuit 12
... Switching circuit 14 ... Judgment circuit 16 ... CPU 18 ... ROM
Reference Signs List 20 RAM 20 RAM 22 I / O circuit 24 Timer 26 First data bus 27 Second data bus 28 First address bus 29 Second address bus 30 Limiting circuit 32, 34 Voltage comparator 3
6. Register circuits R1 to R5: Voltage dividing resistors SW1, SW2: Analog switches

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/822

Claims (4)

[Claims] A digital circuit for processing a digital signal; an analog circuit for processing an analog signal; and converting the analog signal processed by the analog circuit into a digital signal and inputting the digital signal to the digital circuit. A single-chip semiconductor device comprising: a signal conversion unit; and an external terminal group for inputting / outputting an external signal to / from the digital circuit unit and the analog circuit unit. A data storage means capable of reading the data, a test signal generating means for generating a binary level test signal in time series, and a test signal generated by the test signal generating means being inputted through the external terminal. Signal switching means for inputting to the analog circuit unit in place of an analog signal, wherein the signal level of the output of the analog circuit unit is within a preset normal range. Determining means for determining whether or not there is, analog section inspection control for activating the test signal generating means, taking in the result of determination by the determination circuit when a preset measurement time has elapsed, and storing the result in the data storage means A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein said inspection signal generation means includes: signal generation data storage means for storing signal generation data corresponding to a signal level of the inspection signal for each predetermined unit time; A data reading means for reading the signal generation data stored in the signal generation data storage means for each unit time; and converting the signal generation data read by the data reading means into a predetermined signal level to generate an inspection signal. And a level converting means. 3. The semiconductor device according to claim 1, wherein said digital circuit inspection means performs a self-inspection for the presence or absence of an abnormality in said digital circuit part, and said digital circuit inspection means performs a self-inspection of said digital circuit part. As a result, when the digital circuit section is normal, an analog section test activation section for activating the analog section test control section, and further, the digital circuit section executes processing according to a preset program. And a digital section inspection section, an analog section inspection activation section, and an analog section inspection control section are realized as processing executed by the microcomputer. 4. The semiconductor device according to claim 1, wherein the analog section inspection control means is configured to be activated when a predetermined activation signal is input through the external terminal group. A semiconductor device characterized in that: