JPH10307543A - Driving circuit integrated display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure a sufficient picture signal band without increasing the occupying area of a signal conductor driving circuit by distributing a timing signal to a buffer circuit and a distributing switch after a control line and picture signal bus wiring cross each other or without crossing each other at all. SOLUTION: An output signal is inputted in the same timing to analog switch group 14 from a timing signal generating circuit 11 through a buffer circuit group 12 in the same number rows as this. An output signal conductor 17 distributes a timing signal in response to the row number of a buffer circuit 12 after crossing only in the vicinity of a cross point 113 with bus wiring 13. Output lines of the buffer circuit 12 are control wiring 18 to drive gates 110, and these are electrically connected to each other, and uniformly transmit the timing signal to the analog switches 110. The picture signal bus wiring 13 is connected to respective elements of an analog switch 14, and since the output lines 111 are connected to a signal conductor 120, a parasitic capacity load of the picture signal bus wiring 13 is reduced, and reduction in a band characteristic is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device such as a liquid crystal display device, and more particularly to a drive circuit integrated type display device in which a drive circuit for driving the display device is formed on the same substrate as an image display unit. Related to the device.

[0002]

2. Description of the Related Art In a driving circuit integrated type display device, pixels are arranged at intersections of a plurality of scanning lines and signal lines orthogonally arranged on a glass substrate, and a scanning line driving circuit for supplying a scanning signal to the scanning lines. A circuit and a signal line driving circuit for supplying a video signal to the signal line are monolithically formed on a glass substrate on which pixels are formed.

The basic configuration of a signal line driving circuit is as follows:
A timing signal generating circuit for performing timing control in the circuit, a buffer circuit for receiving and outputting a timing signal, a video signal bus line for supplying a video signal from outside the driving circuit, and an output of the buffer circuit;
It is configured by an analog switch that is a video signal distribution switch that samples a video signal of a video signal bus line and supplies the sampled video signal to a signal line.

In a conventional liquid crystal display device integrated with a driving circuit, in order to prevent the deterioration of the band characteristic of a video signal due to a decrease in an operation margin due to an increase in driving load and an increase in definition due to an increase in size, a plurality of driving circuits are required. A plurality of video signal bus lines for controlling analog switches connected to the signal lines by a common timing signal and supplying different video signals to each analog switch are provided. As a result, the period allowed for sampling is longer than in the case where the analog switch group is controlled at individual timings, so that the video signal can be sufficiently sampled.

[0005]

Since the time allowed for sampling is shortened as the display device becomes larger and higher definition, a larger number of analog switches are controlled at the same timing. The number of video signal bus lines also tended to increase. However, the conventional technique has a problem that the area occupied by the signal line driving circuit on the glass substrate increases as the number of video signal bus wirings increases, and the effective display area of the display device decreases. In view of the above background, it is an object of the present invention to secure a sufficient video signal band without increasing the area occupied by a signal line driving circuit.

[0006]

In the present invention, a buffer circuit and an analog switch are arranged between a video signal bus and a display area of a liquid crystal display device integrated with a driving circuit. The control terminals of the analog switch group are connected to a buffer circuit, and the buffer circuits are commonly connected to a single output signal line of the timing signal generation circuit. The analog switch is also connected between the video signal bus and the signal line in the display area. The analog switch distributes the video signal of the video signal bus to the signal line of the display area according to the sampling signal supplied to the control terminal from the timing signal generation circuit.

With this configuration, when the timing signal generating circuit is arranged outside the video signal bus, the area where only the single output signal line intersects the video signal bus is minimized. Further, when the timing signal generating circuit is arranged inside the video signal bus, there is no need for a single output signal line to cross the video signal bus, and therefore, there is no need for a crossing area. As a result, the stray capacitance of the bus wiring can be reduced, and sufficient video signal band characteristics can be obtained.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 shows a first embodiment according to the present invention. This is a signal line drive circuit of a drive circuit integrated type liquid crystal display device. FIG. 2 is a schematic configuration diagram of a cross-sectional structure of the drive circuit-integrated liquid crystal display device shown in FIG.

The manufacturing process of the driving circuit integrated type liquid crystal display device according to this embodiment will be briefly described with reference to FIG. First, the array insulating substrate (glass substrate) 228
In order to reduce the influence of impurities in the substrate and on the surface, a plasma CVD method, a normal pressure CVD method, and the like are used.
An insulating undercoat film 222 such as silicon nitride or silicon oxide is formed. Then, after forming the first amorphous silicon 223 by a plasma CVD method,
The concentration of hydrogen in the film is reduced in the heating step. This amorphous silicon 223 is provided as a light shielding layer. Further, a film of silicon nitride 219 and a second amorphous silicon is formed by a plasma CVD method, and after a dehydrogenation process, is annealed using an excimer laser to convert the second amorphous silicon into polysilicon.
An active layer 216 is formed. The film formed in the above process is subjected to patterning and device isolation through a PEP process, and then to an active device (TFT for circuit) in a drive circuit.
Channel layers 225b and 227 of the pixel switching element (pixel TFT) in the display area.
And the storage capacitor electrode 226 of the display pixel is formed.

Next, a gate insulating film,
In addition, a silicon oxide 213 serving as an insulating film of an auxiliary capacitor is formed. This silicon oxide becomes a dense film with few defects by undergoing a high-temperature heating step.

Next, a Mo (molybdenum) -W (tungsten) alloy thin film is formed by sputtering,
Patterning is performed through the steps, and the TFT gates form the latitude lines 29 and 210, the auxiliary capacitance wiring 215, and the like.

Subsequently, a resist or Al is patterned as a mask at the time of the impurity implantation, and then the impurity is implanted, so that the source 216 and the drain 226 of the TFT are formed.
In order to form the LDD region 224, B (boron) and P (phosphorus) are implanted as P-type and N-type impurities, respectively. The TFTs 229 and 230 and the N-type TFT 231 are formed.

Next, a silicon oxide 218 to be a first interlayer insulating film is formed by a normal pressure CVD method, a contact hole is opened, and an aluminum film is formed by a sputtering method. The aluminum film is patterned through a PEP and an etching process to form connection electrodes 211 and 212 to a source region and a drain region of the TFT, and various wirings represented by signal lines.

Finally, silicon nitride 21 to be a protective film or a second interlayer insulating film is formed by a plasma CVD method.
7 and a contact hole is opened, and in the case of a pixel TFT of a liquid crystal display device, an ITO (Indium Tin Oxide) film as a transparent electrode film is formed by a sputtering method.
The pixel electrode 214 is formed by patterning by etching. An alignment film 266 is applied thereon. The counter substrate 21 is provided with a filter layer including a black matrix layer 22 and a color layer 23, a counter electrode 25 including an ITO film, and an alignment film 26a. Array insulating substrate 2
A liquid crystal 28 is held between the liquid crystal 28 and the counter substrate 21, and the gap is sealed with a sealant 27. In this embodiment, the opposing substrate 21 extends only to the seal application portion including the image display area, but may be configured to cover the drive circuit portion (see FIGS. 6 and 7).

As a mask for the above-described impurity implantation, a Mo film formed when forming a gate wiring and an auxiliary capacitance wiring is formed.
There is also a method of using W together. In this case, the MoW film formation is divided into, for example, two times, and the first MoW film 29 is used as a mask for implanting N-type impurities, and the second MoW film 210 is used as a mask for implanting P-type impurities. , N-type TF
T can be made separately.

Through the above steps, a liquid crystal display device integrated with a drive circuit is formed on the insulating substrate. In the present embodiment, as shown in FIG. 1, the counter substrate 21 covers the array substrate 228 up to the region including the image display region 115 and the seal coating portion 112, but the region outside the array substrate 228 alone includes only the array substrate 228. , A driving circuit. In this drive circuit, a buffer circuit 12 and an analog switch group 14 serving as a video signal distribution circuit are arranged inside a latitude line 13 on a video signal bus. That is, the output signals from the timing signal generating circuit 11 are input to the analog switch group 14 shown in the drawing at the same timing via the buffer circuit group 12 in the same number of rows. The output signal line 17 from the timing signal generation circuit 11 intersects the bus line 13 only in the vicinity of the cross point 113, and then distributes the timing signal on the image display unit side in accordance with the number of columns of the buffer circuit 12. Connected to.

An output line of the buffer circuit 12 is connected to a control line 18 for driving a gate 110 of the analog switch 14.
It has become. The video signal bus wiring 13 is connected to each element of the analog switch 14 by a connection line 19. Since the control lines 18 are electrically connected to each other, it is possible to quickly and uniformly transmit the timing signal to the analog switch 110. The output line 111 of the analog switch 14 is connected to the signal line 120 in the image display area. By adopting the above configuration, the overlap with the video signal bus wiring 13 is reduced, so that the parasitic capacitance load of the video signal bus wiring 13 can be reduced. As a result, the band characteristic of the video signal bus wiring can be reduced. Can be prevented from decreasing.

(Embodiment 2) FIG. 3 shows a signal line drive circuit of a drive circuit integrated type liquid crystal display device according to a second embodiment of the present invention. In this embodiment, the array substrate 228
The arrangement of the counter substrate 21 is the same as that of the first embodiment, but the configuration of the drive circuit is different. As shown, the buffer circuit 32 is arranged further inside the analog switch 34.

With the above configuration, the output line 3 of the timing signal generation circuit 31 can be changed in the same manner as in the first embodiment.
7 not only intersects near the cross point 313 of the video signal bus wiring 33 but also the video signal connected from the video signal bus wiring 33 to the input side of each analog switch 34 Since the length is shortened, the capacitance hanging on the video signal bus wiring 33, that is, the parasitic capacitance of the video signal bus wiring 33 itself can be reduced.
As a result, the band characteristics of the video signal bus wiring 33 can be further improved.

(Embodiment 3) FIG. 4 shows a signal line drive circuit of a drive circuit integrated type liquid crystal display device according to a third embodiment of the present invention. As shown in the figure, a timing signal generation circuit 41 for controlling the basic timing of the drive circuit is arranged inside the video signal bus wiring 43. With the above configuration, the control wiring 47 connected from the timing signal generation circuit 41 to the buffer circuit 42 is arranged without overlapping with the video signal bus wiring, and the video signal bus wiring 33 and the video signal display area 115 The analog switch 44 that connects to the signal line 120 is controlled. This embodiment is different from the first embodiment in that the video signal bus wiring 33
Can be reduced. As a result, the band characteristics of the video signal bus wiring can be further improved.

(Embodiment 4) FIG. 5 shows a signal line drive circuit of a drive circuit integrated type liquid crystal display device according to a fourth embodiment of the present invention. As shown in the figure, a timing signal generation circuit 51 for controlling the basic timing of circuit driving is arranged inside the video signal bus wiring 53, and the video signal output from the analog switch 54 to each signal line 111 is minimized. The blocks are collectively arranged so as not to interfere with the timing signal generation circuit.

By adopting the above configuration, each signal line of the liquid crystal display device is not redundantly wired to the timing signal generation circuit, so that the circuit arrangement is smaller than that of the second embodiment. This makes it easier to prevent design errors and improve the yield of the liquid crystal display device itself.

(Embodiment 5) FIG. 6 shows a signal line drive circuit of a drive circuit integrated type liquid crystal display device according to a fifth embodiment of the present invention. The configuration of the driving circuit is the same as that of the second embodiment shown in FIG. 3, but as shown in the figure, the opposing substrate 21 entirely opposes the array substrate 228, and the driving circuit portion of the display device is entirely It is configured so as to be sandwiched between the array substrate 228 and the counter substrate 21, and furthermore, the video signal bus wiring 63 and the analog switch 64 are formed so as to overlap with the sealant application section 112. The buffer circuit 62 is provided between the sealing material application unit 112 and the image display area 115, and the timing signal generation circuit 61 is provided outside the sealing material application unit 112.

With the above configuration, the video signal bus wiring and the analog switch are covered with a material having a lower relative dielectric constant than the liquid crystal, so that the wiring group and the circuit group are arranged in the liquid crystal as in the prior art. It is possible to reduce the occurrence of parasitic capacitance with the common electrode on the opposing substrate and the occurrence of parasitic capacitance between the array wirings, as compared with the case where the above is performed. As a result, the sealing material application area is not changed much from the conventional example,
It is possible to prevent a band characteristic of a video signal bus line from being deteriorated and to make a frame of a liquid crystal display device narrower.

(Embodiment 6) FIG. 7 shows a signal line drive circuit of a drive circuit integrated type display device according to a sixth embodiment of the present invention. As shown in the figure, the opposing substrate 21 and the array substrate 228 face each other, and the timing signal generating circuit 71 is provided on the outer peripheral portion. A buffer circuit 72 and an analog inference 74 are arranged inside the video signal bus wiring 73 in the sealant application section 112, and a common electrode on the opposite substrate is arranged so as to avoid the video signal bus wiring 73 and the analog switch 74. .

As described above, since the video signal bus wiring 73 is arranged on the outer peripheral portion of the array substrate, the common electrode can be formed with the video signal bus wiring 73 even if formed with lower accuracy than the conventional configuration. And the analog switch 74 can be disposed. As a result, the video signal bus wiring 3
The band characteristics of No. 3 can be further improved while maintaining low cost.

The present invention is not limited only to the above embodiment. For example, each element on the array substrate may be formed through a process different from the manufacturing process shown in the above embodiment, and the circuit configuration and the cell structure may be different from the video signal supply bus wiring and other components. As long as the arrangement relationship with the circuit group is the same as that of the above embodiment, the analog switch may be a P-type TFT or the analog switch may be of a transfer gate type. Further, even when a plurality of the above embodiments are combined and configured on the same drive circuit, it is possible to improve the band characteristic of the video signal supply bus wiring, and furthermore, the analog switch Even in the case where a circuit for enhancing the driving capability such as an analog buffer circuit is inserted between the pixel signal line and the pixel section signal line, in the sense that the band characteristic of the video signal supply bus wiring is improved, It shows a similar effect.

[0028]

According to the present invention, the timing signal is distributed to the buffer circuit and the distribution switch after the control line crosses the video signal bus line or without the control line crossing the video signal bus line at all. With this configuration, the area of intersection between the control lines and the video signal bus lines can be reduced or eliminated. Thus, the stray capacitance of the bus wiring can be reduced, sufficient video signal band characteristics can be obtained, and good display can be obtained without increasing the area occupied by the drive circuit.

[Brief description of the drawings]

FIG. 1 is a circuit layout diagram of a drive circuit integrated display device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part of the liquid crystal display device of FIG.

FIG. 3 is a circuit layout diagram of a driving circuit integrated type liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a circuit layout diagram of a driving circuit integrated type liquid crystal display device according to a third embodiment of the present invention.

FIG. 5 is a circuit layout diagram of a driving circuit integrated type liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 6 is a circuit layout diagram of a drive circuit integrated type liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 7 is a circuit layout diagram of a drive circuit integrated type liquid crystal display device according to a sixth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Timing signal generation circuit 12 ... Buffer circuit 13 ... Video signal bus wiring 14 ... Video signal distribution switch (analog switch) 16 ... Shift register 17 ... Timing generation circuit output wiring 18 ... Buffer circuit output wiring 111 ... Signal line 714 ... Counter electrode

Claims (12)

[Claims] 1. An array substrate, a counter substrate provided with a gap opposed to the array substrate, liquid crystal supplied to the gap, a seal coating section, and the seal coating for sealing the liquid crystal in the gap. A sealing material applied to a portion, an image display area including a signal line disposed on the array substrate, a video signal bus for transmitting a video signal, a latitude line, a timing signal generation circuit for generating a timing signal, and the timing A switch for supplying a video signal from the video signal bus wiring to the signal line in accordance with a signal, a buffer circuit for supplying the switch with the timing signal from the timing signal generating circuit; A drive circuit integrated display device, which is arranged closer to the display area than a signal bus wiring. 2. The drive circuit integrated display device according to claim 1, wherein said buffer circuit and said switch are arranged between said image signal supply bus wiring and said image display section. 3. The drive circuit according to claim 1, wherein the timing signal generation circuit has a single output signal line disposed at an end of the array substrate and transmitting a timing signal to the switch. Integrated display device. 4. The drive circuit integrated display device according to claim 1, wherein the counter substrate does not cover the video signal bus wiring, the timing signal generation circuit, the switch, and the buffer circuit. 5. The drive circuit-integrated display device according to claim 1, wherein the countermeasure plate covers the video signal bus wiring, the timing signal generation circuit, the switch, and the buffer circuit. 6. The video signal bus wiring is provided at an end of the array substrate, and the timing signal generation circuit, the switch and the buffer circuit are arranged between the video signal bus wiring and the image display area. The display device integrated with a drive circuit according to claim 1, wherein: 7. The drive circuit-integrated display device according to claim 1, wherein the video signal bus wiring and the switch are arranged in a seal material application area. 8. The counter substrate further has a common electrode,
2. The drive circuit integrated display device according to claim 1, wherein said common electrode does not cover said video signal bus wiring and said switch. 9. An array substrate, an opposing substrate provided with a gap opposed to the array substrate, a liquid crystal supplied to the gap, a seal coating section, and the seal for sealing the liquid crystal in the gap. A sealing material applied to an application section, an image display area including a signal line disposed on the array substrate, a video signal bus wiring for transmitting a video signal, a timing signal generation circuit for generating a timing signal, and the timing A switch for supplying a video signal from the video signal bus wiring to the signal line according to a signal, a buffer circuit for supplying the switch with the timing signal from the timing signal generation circuit, the buffer circuit and the switch The timing signal generating circuit is disposed closer to the display area than the video signal bus wiring, and transmits a timing signal to the switch. A drive circuit integrated display device having a single output signal line. 10. The driving circuit integrated display device according to claim 9, wherein said counter substrate further has a common electrode, and said common electrode does not cover said video signal bus wiring and said switch. 11. The driving circuit-integrated display device according to claim 9, wherein said timing signal generating circuit is arranged at an end of said array substrate. 12. An array substrate, an opposing substrate provided with a gap facing the array substrate, a liquid crystal supplied to the gap, a seal application section, and the seal for sealing the liquid crystal in the gap. A sealing material applied to the application section, an image display area including a signal line disposed on the array substrate, a video signal bus wiring for transmitting a video signal provided on the array substrate, and a video signal bus line disposed on the array substrate. Signal generation circuit for generating a timing signal, a switch for supplying a video signal from the video signal bus wiring according to the timing signal, and a parallel buffer circuit for supplying the switch with the timing signal from the timing signal generation circuit And an output signal line connecting the parallel buffer circuits to each other, the switch being connected to the parallel buffer circuit and the switch. Is disposed closer to the display area than the video signal bus wiring.