JPH10302277A - Optical disk device and track error signal generation method - Google Patents

Abstract

(57) [Summary] [Problem] To extract accurate phase difference information and obtain a highly reliable T
It is an object of the present invention to provide an optical disk device capable of reproducing an E signal. A PL for generating a data read clock is provided.
An L circuit 7, an automatic frequency variable waveform equalizer that emphasizes and amplifies a specific frequency band, a comparator, an external control delay device that adjusts a phase difference balance, a phase comparator that detects a phase difference, A variable frequency equalizer that can vary the frequency characteristics by an external input, and has means for varying the frequency characteristics so as to be proportional to the clock frequency in synchronization with the clock. It is characterized by having. During the variable speed reproduction, the constant relation of the waveform equalizer can be varied while maintaining the optimum state according to the change of the reproduction frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk apparatus for recording and reproducing data by light, and more particularly to an optical disk apparatus in which a data transfer rate during reproduction is made variable and a track error signal for track servo is generated by a phase difference method. It concerns the device.

[0002]

2. Description of the Related Art In recent years, an optical disk device has played an important role as a basic product of multimedia, and especially a CD.
-A ROM drive device is indispensable as an additional storage device for a personal computer. Further, as a next-generation optical disk device, a DVD drive device has been developed in which the storage capacity is significantly improved compared to a CD-ROM. Incidentally, the DVD has a mark length and a track pitch that are both about 1/2 (area ratio 1/4) smaller than a CD-ROM, and the laser spot from which data is read also has a shorter laser beam. Due to the increase in wavelength, downsizing to an area ratio of about 60% has been realized.

[0003] In these disks, encoded data is continuously recorded in the form of pits on the reflection surface of the disk in a spiral form from the inner peripheral side to the outer peripheral side. The data string recorded in this manner is called a track, and at the time of reproduction, data is read by tracing (tracking) the track with an optical pickup.

A TE for controlling this tracking is used.
The (track error) signal is generated as follows. In the three-beam tracking, a grating is provided in an optical path to create a sub beam, and three beams are generated. 1
In beam tracking, tracking control is performed using only the main beam. Beam detection and control are classified into a phase difference method, a heterodyne method, a push-pull method, and the like, depending on the configuration of a beam detection circuit.

[0005] In a CD-ROM, three-beam tracking is common. On the other hand, in the case of DVD, the pit area of the disk is reduced in order to increase the recording capacity, and the spot area reduction ratio cannot catch up with the pit area reduction ratio of the disk. Detection by the method is generally performed.

Hereinafter, tracking control by a conventional phase difference method will be described with reference to the drawings. FIG. 19 is a configuration diagram of a conventional optical disk device, and FIG. 20 is a basic configuration diagram of the phase difference TE signal detector 9 of FIG. In FIG. 19, 1 is an optical disk on which information signals are recorded at a constant linear velocity, and 2 is a spindle motor on which the optical disk 1 is mounted and rotates. Reference numeral 3 denotes a pickup, which includes an objective lens for converging a laser beam on the recording surface of the optical disk 1 and a direction perpendicular to the surface of the optical disk 1 (hereinafter, referred to as a focus direction) and a radial direction of the optical disk 1 (referred to as a focus direction). An actuator (motor) for moving in a tracking direction), various prisms including a semiconductor laser, and optical elements such as a signal detection detector are integrally formed. Reference numeral 4 denotes a sled motor, which is used for tracking a movement range that cannot be handled by the pickup 3 and for moving the pickup 3 largely between tracks (access operation).

An RF signal detector 5 generates an analog RF signal from the output of the pickup 3. Reference numeral 6 denotes an RF signal slicer for generating a digital RF signal (data signal) from the aforementioned analog RF signal, and reference numeral 7 denotes a PLL (Phase Locked) for synchronizing the aforementioned digital RF signal.
And a demodulator 8 for demodulating the data of the digital RF signal using the output signal PLCK of the PLL circuit 7.

A phase difference TE signal detector 9 generates a phase difference TE signal from the output of the pickup 3. 10
Numeral denotes a servo signal detector, which detects other servo-related signals such as an FE (focus error) signal and an RF ripple signal (a signal for counting at the time of a track jump). Reference numeral 11 denotes a servo controller which performs servo control based on the detected other servo signals. The servo controller 11 also has a function of performing focus adjustment, track servo system offset adjustment, balance adjustment, gain adjustment, and the like based on the detected servo signal. Reference numeral 12 denotes a motor driver that drives each motor based on the output of the servo controller 11.

Next, in FIG. 20, reference numeral 21 denotes a four-divided signal detecting detector for receiving the reflected light from the optical disk 1, and reference numeral 22 denotes an IV for converting an output current signal of the signal detecting detector 21 into a two-system voltage signal. A (current-to-voltage) converter, 23 is a waveform equalizer for emphasizing and amplifying a specific frequency band of the output of the IV converter 22, and 24 is a device for slicing the output of the waveform equalizer 24 at a certain slice level and digitizing it. A comparator 25 is an externally controlled delay for adjusting the phase difference balance between the two outputs of the comparator 24.
Reference numeral 6 denotes a phase comparator for detecting the phase difference between the outputs of the two systems of the external control delay unit 25, and reference numeral 27 denotes a charge pump for performing charging or discharging based on the output of the phase comparator 26.

Here, the operation principle of the conventional phase difference TE signal detector 9 will be described together with a supplementary diagram, together with the concept of the phase difference method. The phase difference method detects a track error signal from a phase difference generated in a light receiving signal based on a positional relationship between a pit and a spot.

FIG. 21 is a diagram showing the distribution of the received light intensity on the pits, spots and lens surfaces. FIG. 21 shows a state in which the spot on the optical disk 1 advances along the pit. FIG.
1 (a) shows a state where the spot is on the right side, FIG. 21 (b) shows a state where the spot is on the center, and FIG. 21 (c) shows a state where the reflected light is received on the lens surface in the state where the spot is on the left side. It shows an intensity distribution. By performing ray tracing using the reflected light as an incident light ray, an intensity distribution on the light receiving element (signal detection detector 21) can be obtained. Diagonal sum signal A1 + from this light receiving element
A2, A3 + A4 (or signals A1, A3 or A2, A4 adjacent to each other in the track mapping direction) are extracted by the IV converter 22 as two-system voltage signals. Each of the voltage signals is shaped into a waveform by the waveform equalizer 23, and then converted into a digital signal by the comparator 24.

After receiving the track error balance adjustment signal TEBAL from the servo controller 11, the external control delay 25 adjusts the phase difference balance between the two digital signals, and the phase comparator 26 advances the phase. , And generates charge and discharge pulses according to the delay.
Further, the charge / discharge pulse is converted into an analog waveform through the charge pump 27 to generate a TE signal. As described above, a method using a four-divided element is generally used for the light receiving element (the signal detection detector 21), but signal detection is also performed using a two-divided element.

FIG. 22 is a waveform chart of a TE signal detection process at each circuit position in the basic configuration diagram of FIG. Note that FIG.
The circuit position number of 0 is the waveform number a1, b1, a of FIG.
2, b2, a3, b3, a4, b4, a5, b5, a
6, b6, and c are displayed respectively. In order to simplify the description, it is assumed that there is no phase difference balance deviation between the output signals a2 and b2 of the two waveform equalizers 23 in the figure (the waveforms a3 and a4, and b3 and b4 are equal waveforms). ). Hereinafter, the operation of the conventional phase difference method will be described with reference to the circuit positions and waveforms of FIGS.

The function of the waveform equalizer 23 will now be described with reference to FIG. FIG. 23 is a frequency characteristic diagram of the waveform equalizer 23. The waveform equalizer 23 is a circuit for reducing interference between waveforms generated from a low optical frequency band to achieve high density. As shown in FIG. 23, the gain of a signal band (f2 or more) generated by short pits is increased by Gbst with respect to a signal band (f1 or less) generated by long pits, and f1, f2, G
In this configuration, bst is optimized according to the characteristics of the optical system and the frequency band of the generated signal. Here, the slice level Vsl of the comparator 24 (see a2 and b2 in FIG. 22) is set to be the average value of the input signal of the comparator 24.

FIG. 24 is a waveform chart showing the effect of improving the characteristics of the waveform equalizer 23. As shown in FIG. 24, the IV converter 2
Even if the output a1 of No. 2 is input to the comparator 24 as it is, pulse shortage of the short pit signal occurs, and phase difference information is lost. However, such an IV converter 22
Is applied to the waveform equalizer 23, only the signal amplitude of the short pit portion can be amplified to the signal amplitude of the long pit portion, and signal loss can be prevented. Thus, the output a1 (b1) of the IV converter 22 is improved in signal amplitude in the short pit portion by the waveform equalizer 23 to become the output signal a2 (b2), and the output signal a2 (b2) is obtained.
, And becomes an output signal a3 (b3).

Next, the external control delay unit 25 will be described with reference to FIG.
26 and FIG. FIG. 25 is a detailed circuit diagram of the external control delay unit 25, and FIG. 26 is a voltage control delay unit 31, 32.
4 is a characteristic diagram of a TEBAL signal versus a delay amount of FIG. 25, reference numerals 31 and 32 denote voltage control delay units, 33 denotes a comparator, 34 and 35 denote analog multiplexers, and 36 denotes an inverter. The voltage control delay devices 31 and 32 are elements that can vary the delay amount according to the voltage level of the TEBAL signal input from the outside, and for example, are linear with respect to the TEBAL signal input as shown in FIG. It has the characteristic of providing a large amount of delay. Further, the comparator 33 detects whether the TEBAL signal input to the control is positive or negative. For example, if the TEBAL signal is positive, the delay amount of the voltage control delay unit 31 is variable, and if the TEBAL signal is negative, the delay amount of the voltage control delay unit 32 is variable. It is a configuration to do.

FIG. 27 is a diagram showing the state of the phase balance of the TE signal. As shown in FIG. 27, it is assumed that the servo controller 11 (FIG. 19) is in a state in which an offset is superimposed on a detected TE signal with respect to a track error (a state in which the phase balance is shifted). At this time, the servo controller 11 detects the average value of the TE signal through, for example, a low-pass filter (LPF) having a sufficiently long time constant, and detects the deviation of the average value from the reference potential so that the average value becomes zero. The TEBAL signal to be corrected is output. FIG.
The voltage control delay units 31 and 37 control the delay amount based on the TEBAL signal versus delay amount characteristic of FIG. Thus,
The DC component offset caused by the phase imbalance can be electrically corrected to remove the optical phase shift, and the TE signal amplitude center can be adjusted so as to match the reference potential of the signal. It can be in a state where it has been removed.

Next, the phase comparator 26 (FIG. 20) will be described. FIG. 28 is a detailed circuit diagram of the phase comparator 26. In FIG. 28, 41 and 42 are D flip-flops, and 43 and 44 are inverters. External control delay 2
5 are output to the D flip-flops 41, 4
2 and input the inverted signals a6 and b6 of the output signals a4 and b4 of the external control delay unit 25 to the preset terminals of the D flip-flops 41 and 42, respectively. The phase comparator 26 configured as described above has the configuration shown in FIG.
As shown in the figure, when the spot is on the right side, the D flip-flop 41 is set first based on the output signal a4 of the preceding external control delay unit 25, so that the output (ie, charge pulse) a5 of the phase comparator 26 is obtained. Conversely, when the spot is on the left side, the D flip-flop 42 is set first based on the output signal b4 of the preceding external control delay 25, so that the output (ie, charge pulse) b5 of the phase comparator 26 is obtained. Can be When the spot is at the center, the signals a4 and b4 are simultaneously output from the D flip-flop 41,
The D flip-flops 41 and 42 do not operate, and neither output (charge pulse) a5 nor b5 is generated.

Next, the charge pump 27 will be described. FIG. 29 is a detailed circuit diagram of the charge pump 27.
29, reference numerals 51 and 52 denote analog switches, 5
Reference numerals 3 and 54 are constant current sources, and 55 is a capacitor. The analog switches 51 and 52 output the signal a of the phase comparator 26.
5, the voltage of the output signal is Hi according to the voltage level of b5.
It operates as switch on when gh and switch off when low. Therefore, the current values of the constant current sources 53 and 54 are set to required values, and the output signal a of the phase comparator 26 is
5 and b5 are applied to the charge pump 27. Then, when the phase is advanced, the output signal a5 of the phase comparator 26 becomes High.
(See when the spot is on the right side in FIG. 22), the analog switch 51 is turned on, and the constant current source 5
A charge current is supplied from 3 to the capacitor 55. On the other hand, when the phase is delayed, the output signal b5 of the phase comparator 26 becomes H
Since it is high (see when the spot is on the left side in FIG. 22), the analog switch 52 is turned on, and the discharge current is discharged from the capacitor 55 by the constant current source 54. Thus, a voltage proportional to the charging / discharging current and the time is generated in the capacitor 55 (T in FIG. 22).
E signal waveform c), TE corresponding to the pit phase difference
The signal c can be detected.

Here, an actual optical disk apparatus reproduces a disk on which CLV recording has been performed by the CAV method for power saving, and when the rotation number of the optical disk reaches a specified rotation number in order to shorten the access time. A variable-speed reproduction technique of reading data even in a non-existing state (a technique of forcibly phase-locking an RF signal having a frequency component shifted using a wideband PLL circuit and reading data) is used. In these cases, there is a state where the frequency component of the reproduced signal is higher (or lower) than the specified value.

FIG. 30 is a diagram showing the frequency fluctuation of the data fundamental frequency in variable speed reproduction. FIG. 30 shows a state where variable speed reproduction is performed using a PLL circuit having a phase lock range of ± 50% with respect to a specified frequency component, for example.

During period A, access is being performed at a constant speed of the specified frequency Ftyp. Now, it is assumed that the pickup 3 is sought to the outer peripheral side in order to reproduce data of a different address. In the period B, the optical disc 1 cannot be immediately decelerated due to the inertia of the combined rotating body,
Data reproduction is started using 1.5F in which the data fundamental frequency is varied up to + 50%. In period C,
During this time, the spindle motor 2 gradually decelerates, and with the deceleration, the data basic frequency gradually increases to the specified frequency Fty.
It decreases toward p.

Conversely, it is assumed that the pickup 3 is sought to the inner circumference in order to reproduce data of a different address. In the period D, since the optical disk 1 cannot be accelerated immediately due to the inertia of the combined rotating body, data reproduction is started using 0.5F in which the data fundamental frequency is changed to -50%. In the period E, the spindle motor 2 gradually accelerates during that period, and the data fundamental frequency gradually increases toward the specified frequency Ftyp with the acceleration.

[0024]

However, the above-mentioned conventional configuration has the following problems. First,
Since the waveform equalizer sets the constant of the amplification degree so as to function for a certain fixed frequency component (frequency component obtained at a normal specified number of revolutions), the frequency component is shifted with variable speed reproduction. In the reproduction state, the correction function as the waveform equalizer cannot be sufficiently obtained, and a state occurs in which the generated phase difference track error signal does not reflect accurate phase difference information.

Also, since the adjustment value set by the phase difference balance adjustment is set at the time of the specified rotation, the reproduction is performed in a state where the frequency components are shifted as described above. In this state, an offset remains in the phase difference track error signal.

As described above, in the case where the reproduction signal is deviated from the prescribed frequency, such as CAV reproduction or variable speed reproduction, since the conventional individual circuits do not cope with the deviation of the frequency component, the reproduction signal is large. A track error signal having an error is generated. As a result, there is a possibility that accurate track servo cannot be performed and data cannot be read normally.

Further, if a pit is crushed due to a scratch on a disc, a defect in production or recording, etc., a large difference may occur in a detected phase difference signal due to a slight difference in comparison. FIG. 31 is a waveform diagram of a TE signal detection process in the case where pits are collapsed in the basic configuration diagram of FIG. FIG. 31 shows a waveform diagram when the pit collapsed area is reproduced using the waveform equalizer 23 of FIG. 20 having the characteristics shown in FIG. The output signal a2 of the waveform equalizer 23 is a waveform diagram showing a state in which the signal level slightly applies to the slice level Vsl even in the pit collapsed area, and the output signal b2 shows a state in which the output signal b2 does not apply to the slice level Vsl.

The operation of the phase difference TE signal detector 9 described in the above-described conventional technique when the output signals a2 and b2 as described above are input is performed by using the output of the phase comparator 26 as a5
A charge pulse having an incorrect charge section Ter1 as shown in FIG.

As a result, a TE signal having a large offset error is generated, which leads to the occurrence of a data read disabled section. Here, the circuit configuration of the phase comparator 26 is temporarily improved, and at least one of the outputs a2 and b2 of the waveform equalizer 23 goes high first, and then the other goes high.
Even if a circuit is added so that the charge pulse (discharge pulse) is reset when one of the two becomes low before the voltage becomes h, the charge pulse having an error section indicated by Ter2 is improved. No remarkable improvement effect of eliminating generation of a large offset error is not achieved.

The present invention solves the above-mentioned conventional problems, and extracts accurate phase difference information even when a reproduced signal deviates from a specified frequency component, such as in CAV reproduction or variable speed reproduction. It is an object of the present invention to provide an optical disc device capable of reproducing a highly reliable TE signal by suppressing a phase difference output signal to a minimum even if a pit collapse region exists.

[0031]

In order to achieve this object, an optical disk apparatus according to the present invention comprises a PLL circuit for synchronizing a data signal and generating a data read clock, and a specific frequency of various data signals in different combinations. A waveform equalizer that emphasizes and amplifies the band, a comparator that slices the waveform equalizer output at a predetermined level, and an external control delay that adjusts the phase difference balance of the comparator output.
A phase comparator for detecting a phase difference of an external control delay device output,
A charge pump for performing charge or discharge by the output of the phase comparator. The waveform equalizer can change the frequency characteristic by an external input.
The frequency characteristic is automatically varied so as to be proportional to the clock frequency in synchronization with the data read clock generated by the LL circuit.

With the above arrangement, the constant relation of the waveform equalizer can be varied while maintaining the optimum state in accordance with the change in the reproduction frequency during variable speed reproduction.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first and second aspects of the present invention, an optical disk is irradiated with a light beam, reflected light is received by a plurality of light receiving elements, and the sum and difference of outputs of the light receiving elements are combined. An optical disk device that generates a clock signal in synchronism with the data signal by a PLL circuit, and generates a phase difference track error signal by combining the sum and difference of the outputs of the light receiving elements.
IV conversion means for combining the sum and difference of outputs of the light receiving elements to convert a received light current into a detection voltage, waveform equalization means for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, Voltage comparison means for binarizing the output obtained by the equalization means with a predetermined voltage value, external control delay means for adjusting the amount of delay of the phase difference balance of the output of the voltage comparison means by an external signal, A phase comparing means for detecting a phase difference between outputs of the external control delay means; and a charging / discharging means for charging / discharging the power storage means based on the output of the phase comparing means, wherein the waveform equalizing means is synchronized with the clock signal. And a method for generating a track error signal in which the frequency characteristic is varied so as to be in a proportional relationship with an external signal having a proportional relationship with the frequency of a clock signal, and the method is synchronized with a lock state of a PLL circuit. The frequency characteristics of the automatic frequency variable waveform equalizer can be linearly varied, and the constant relationship of the waveform equalizer optimally set at the specified frequency can be maintained in the optimum state according to the change in the reproduction frequency. It has the effect that it can be automatically varied.

According to the third and fourth aspects of the present invention, an optical disk is irradiated with a light beam, the reflected light is received by a plurality of light receiving elements, and a data signal is formed by combining the sum and difference of the outputs of the light receiving elements. An optical disc apparatus for generating a clock signal in synchronism with a data signal by a PLL circuit and generating a phase difference track error signal by combining the sum and difference of outputs of the light receiving elements, wherein the sum of the outputs of the light receiving elements is IV conversion means for converting the received light current to a detection voltage by combining the difference and the difference, a waveform equalization means for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and a waveform equalization means. Voltage comparison means for comparing the output with a predetermined voltage value to binarize the output, and external control delay means for adjusting the amount of delay of the phase difference balance of the output of the voltage comparison means by an external signal; And a charge / discharge means for charging / discharging the power storage means based on the output of the phase comparison means. The external control delay means is synchronized with the clock signal. And a method for generating a track error signal in which the delay amount is varied in an inversely proportional relationship with an external signal having an inversely proportional relationship with the frequency of the clock signal, wherein the delay of the voltage control delay device is synchronized with the locked state of the PLL. The amount can be varied linearly, and the phase balance relationship optimally set at the specified frequency can be automatically varied according to the change in the reproduction frequency while maintaining the optimal setting state.

According to the fifth and sixth aspects of the present invention, an optical disk is irradiated with a light beam, the reflected light is received by a plurality of light receiving elements, and a data signal is formed by combining the sum and difference of the outputs of the light receiving elements. An optical disc apparatus for generating a clock signal in synchronism with a data signal by a PLL circuit and generating a phase difference track error signal by combining the sum and difference of outputs of the light receiving elements, wherein the sum of the outputs of the light receiving elements is IV conversion means for converting the received light current to a detection voltage by combining the difference and the difference, a waveform equalization means for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and a waveform equalization means. Voltage comparison means for comparing the output with a predetermined voltage value to binarize the output, and external control delay means for adjusting the amount of delay of the phase difference balance of the output of the voltage comparison means by an external signal; A phase comparing means for detecting a phase difference between outputs of the unit control delay means, and a charging / discharging means for charging / discharging the power storage means based on the output of the phase comparing means. An optical disc apparatus and a track error signal generating method, which are phase comparing means with a limit function for setting a limit value by a delay amount, wherein a limit value is set by a delay amount so that unnecessary phase difference information is not output to a phase comparator. Therefore, even if an abnormal comparator output signal is generated due to a pit collapse area of the optical disk or the like, it is possible to suppress the phase difference error to a minimum.

According to the seventh and eighth aspects of the present invention, an optical disk is irradiated with a light beam, the reflected light is received by a plurality of light receiving elements, and a data signal is formed by combining the sum and difference of the outputs of the light receiving elements. An optical disc apparatus for generating a clock signal in synchronism with a data signal by a PLL circuit and generating a phase difference track error signal by combining the sum and difference of outputs of the light receiving elements, wherein the sum of the outputs of the light receiving elements is IV conversion means for converting the received light current to a detection voltage by combining the difference and the difference, a waveform equalization means for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and a waveform equalization means. Voltage comparison means for comparing the output with a predetermined voltage value to binarize the output, and external control delay means for adjusting the amount of delay of the phase difference balance of the output of the voltage comparison means by an external signal; A phase comparing means for detecting a phase difference between outputs of the unit control delay means, and a charging / discharging means for charging / discharging the power storage means based on the output of the phase comparing means. An optical disk device, comprising: a phase comparison means with a limit function for setting a limit value by a delay amount, wherein the optical disk device synchronizes with a clock signal and changes the delay amount to be in an inverse proportional relationship by an external signal having an inverse proportional relationship with a frequency of the clock signal; This is a method of generating a track error signal. The limit value can be set according to the amount of delay so that unnecessary phase difference information is not output to the phase comparator. Even if a signal is generated, the phase difference error can be suppressed to a minimum. Further, since the above-mentioned limit value can be linearly changed in synchronization with the locked state of the PLL, the constant relation optimally set at the time of reproduction at the specified frequency is maintained in an optimum state according to the change in the reproduction frequency. It has the effect that it can be automatically varied.

According to the ninth and tenth aspects of the present invention, an optical disk is irradiated with a light beam, the reflected light is received by a plurality of light receiving elements, and a data signal is formed by combining the sum and difference of the outputs of the light receiving elements. Then, the clock signal is generated in synchronization with the data signal by the PLL circuit, and the phase difference track error signal is generated by combining the sum and difference of the outputs of the light receiving elements to synchronize the optical disk rotating means with the data signal. An optical disc device, comprising: an IV converter for converting a light receiving current into a detection voltage by combining the sum and difference of outputs of a light receiving element; and a waveform for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands. Equalization means;
Voltage comparison means for binarizing the output obtained by the waveform equalization means with a predetermined voltage value, and external control delay means for adjusting the amount of delay of the phase difference balance of the output of the voltage comparison means by an external signal. A phase comparison means for detecting a phase difference between outputs of the external control delay means, a charge / discharge means for charging / discharging the power storage means based on the output of the phase comparison means, and a control for controlling the operation of each means by controlling the entire apparatus. Means, and the control means comprises:
During the period from the control state where the servo control by the PLL circuit is not synchronized to the time when the clock signal is generated by the PLL circuit in synchronization with the data signal, the external control delay means and the phase comparison means depend on the external signal. An optical disc apparatus and an optical disc driving method, characterized in that the apparatus has an acceleration control for performing a rotational drive based on a predetermined set value, and a PLL circuit is out of synchronization at an initial start-up after loading the disc. By setting the clock as a reference clock corresponding to a prescribed frequency at a certain time immediately before performing synchronization and at a certain time, the automatic frequency variable function can be surely shifted to a normal operation. is there.

An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a configuration diagram of an optical disk device according to Embodiment 1 of the present invention. In FIG. 1, 1 is an optical disk, 2 is a spindle motor, 3 is a pickup,
4 is a thread motor, 5 is an RF signal detector, 6 is an RF signal slicer, 7 is a PLL circuit, 8 is a demodulator, 10 is a servo signal detector, 11 is a servo controller, and 12 is a motor driver. Each of the circuit configuration blocks described above has the same function as that of the conventional configuration block, is given the same name and the same reference numeral, and redundant description is omitted.

Reference numeral 13 denotes a CPU (arithmetic processing unit) which controls the above-described respective constituent blocks and controls the entire operation of the optical disk apparatus. Reference numeral 14 denotes a memory which temporarily stores processing data and control programs involved in the arithmetic processing. .

Reference numeral 109 denotes an automatic frequency variable phase difference TE signal detector of a circuit configuration block which characterizes the present invention;
The frequency characteristics can be varied by an external input, and a phase difference TE signal is generated from the output of the pickup 3.

FIG. 2 shows a basic configuration diagram of the automatic frequency variable phase difference TE signal detector 109 of FIG. 1 according to the first embodiment. In FIG. 2, reference numeral 21 denotes a signal detection detector;
Is an IV converter, 24 is a comparator, 25 is an external control delay, 26 is a phase comparator, and 27 is a charge pump. Each of the circuit components described above has the same function as that of the conventional component, is given the same name and the same reference numeral, and redundant description is omitted.

Reference numeral 123 denotes a frequency automatic variable waveform equalizer which is a difference from the prior art and is a feature of the present invention, and is a synchronous output signal of the PLL circuit 7 (see FIG. 1). The frequency characteristics are automatically varied using the PLCK as a clock input, and the specific frequency band of the output signals a1 and b1 of the IV converter 22 is emphasized and amplified.

FIG. 3 is a detailed circuit diagram of the automatic frequency variable waveform equalizer 123, and FIG. 4 is an automatic frequency variable waveform equalizer 1 of FIG.
23 is a frequency vs. voltage characteristic diagram for a data read clock signal PLCK of FIG. In FIG. 3, 131, 13
Reference numeral 2 denotes a voltage-controlled frequency variable waveform equalizer that linearly (in a proportional relationship) varies frequency characteristics according to an input voltage level, and 133 denotes a frequency of a data read clock signal PLCK output from the PLL circuit 7. Configured to output a linear voltage level Vplck (see FIG. 4)
V converter.

FIG. 5 shows an automatic frequency variable waveform equalizer 1 shown in FIG.
FIG. 23 is a diagram illustrating a variable state of a frequency characteristic of FIG. In FIG. 5, the relationship between the frequency f1 of the gain G0 and the frequency f2 of the gain (G0 + Gbst) with respect to the specified frequency Ftyp is the same as the relationship shown in FIG. Therefore, for example, a variable state when performing ± 50% variable speed reproduction will be described.

First, the data read clock signal PLCK output from the PLL circuit 7 fluctuates in the range of 0.5 to 1.5 Ftyp with respect to the specified frequency Ftyp. Therefore, the FV converter 133 adjusts the specified voltage Vtyp by 0.5 to 1.5 V based on the frequency versus voltage characteristics shown in FIG.
It changes to the voltage range of type. Therefore, the specified frequency Ft
While maintaining the relationship between the frequencies f1 and f2 with respect to yp, 0.5f1 corresponding to a voltage range of 0.5 to 1.5 Vtyp,
0.5f2 to 1.5f1 and 1.5f2 can be obtained.

As described above, by applying the automatic frequency variable waveform equalizer 123 of the present invention, the automatic frequency variable waveform equalizer 12 is synchronized with the locked state of the PLL circuit 7.
3, the frequency characteristics f1 and f2 can be linearly varied, and the constant relation of the waveform equalizer optimally set at the specified frequency can be automatically varied while maintaining the optimal state according to the change in the reproduction frequency. it can. Thus, accurate phase difference information can be extracted even when the data signal in CAV reproduction or variable speed reproduction deviates from the specified frequency.

(Embodiment 2) FIG. 6 shows a basic configuration diagram of Embodiment 2 of the automatic frequency variable phase difference TE signal detector 109 shown in FIG. In FIG. 6, reference numeral 21 denotes a signal detection detector, 22 denotes an IV converter, 23 denotes a waveform equalizer,
4 is a comparator, 25 is an automatic variable frequency external control delay, 26 is a phase comparator, and 27 is a charge pump.
Each of the circuit components described above has the same function as that of the conventional component, is given the same name and the same reference numeral, and redundant description is omitted.

Numeral 125 denotes a frequency automatic variable waveform external control delay device which is a difference from the prior art and which is a feature of the present invention, and is a servo controller 11 (FIG. 1).
), The phase difference balance between the outputs of the comparators 24 is adjusted by the balance adjustment signal TEBAL.
The delay amount is automatically varied by using the synchronization output signal PLCK of the circuit 7 (see FIG. 1) as a clock input.

FIG. 7 shows an automatic frequency variable external control delay unit 12.
5 is a detailed circuit diagram of FIG. In FIG. 7, 141, 142
Is a voltage control delay, 143 is a comparator, 144, 1
Reference numeral 45 denotes an analog multiplexer, 146 denotes an analog divider, and 147 denotes an FV converter.
And has the same function as the FV converter 133 described in FIG. By passing the synchronization output signal PLCK of the PLL circuit 7 (see FIG. 1) through the FV converter 147, a voltage level Vplck is obtained based on the characteristics shown in FIG. Further, an analog divider 146 divides the balance adjustment signal TEBAL of the output signal of the servo controller 11 (see FIG. 1) by the voltage level Vplck to generate an adjustment value TEBAL2 shown in FIG. FIG. 8 shows the voltage level Vplc.
It is a figure showing the relation between k and adjustment value TEBAL2. FIG.
As shown in the figure, the adjustment value TEBAL2 is in inverse proportion to the value of the voltage level Vplck at the specified frequency. That is, when the voltage level Vplck at the specified frequency is Vtyp, the adjustment value TEBAL2 is obtained as Vadj. Similarly, when the voltage level Vplck is 1.5 V
adjustment value TEBAL when the value is typ (0.5 Vtype)
2 is obtained as 0.67 Vadj (2 Vadj in the same order).

FIG. 9 is a diagram showing the relationship between the adjustment value TEBAL2 of the voltage control delay devices 141 and 142 and the delay amount. In FIG. 9, the voltage control delay units 141 and 142 are linear (proportional) with respect to the adjustment value TEBAL2.
Can be obtained. That is, the delay amount is obtained as DL with respect to Vadj from the adjustment value TEBAL2 obtained in FIG. 8 according to FIG. Similarly, the adjustment value TEBAL2 becomes 1.5 Vadj (0.5 Vadj).
When, the delay amount is obtained as 1.5DL (0.5DL same order).

The balance adjustment signal TEBAL is merely a balance signal for correcting a phase difference, and in a circuit configuration that balances using a delay amount, the balance adjustment signal TEBAL is optimal when the frequency of the detection signal (of the pit signal) changes. A state of imbalance occurs. Therefore, in the circuit configuration of the present invention,
At the time of the initial start-up after the insertion of the disc, the balance is adjusted and controlled so that the TE signal is adjusted in the PLL locked state and the state where the rotation can be regarded as the specified rotation. Therefore,
Even if a variable speed reproduction state that deviates from the specified frequency thereafter occurs, it is possible to maintain the optimal balance state even at the frequency after the variable speed.

As described above, according to the present invention, the delay amount DL of the voltage control delay device can be varied linearly in synchronization with the locked state of the PLL, and the phase balance relationship optimally set at the specified frequency can be obtained at the reproduction frequency. Can be automatically varied in accordance with the change in the state while maintaining the optimum setting state. Therefore,
Accurate phase difference information can be extracted even in signal reproduction in which the data signal is shifted from the specified frequency, including CAV reproduction.

(Embodiment 3) FIG. 10 is a basic configuration diagram of Embodiment 3 of the automatic frequency variable phase difference TE signal detector 109 of FIG. In FIG. 10, 21 is a signal detection detector, 22 is an IV converter, 23 is a waveform equalizer, 24 is a comparator, 25 is an external control delay, 27
Is a charge pump. Each of the circuit components described above has the same function as that of the conventional component, is given the same name and the same reference numeral, and redundant description is omitted.

Reference numeral 126 denotes a phase comparator with a limiter function, which is a feature of the present invention, which is different from the conventional technology, and detects the phase difference of the output of the external control delay unit 25. The limit value of the output phase difference can be set by the delay amount.

FIG. 11 shows a phase comparator 126 with a limiter function.
FIG. In FIG. 11, 151, 15
2, 153 and 154 are D flip-flops, 155 and 1
56 is a monostable multivibrator, 157, 1
58 is an inverter, and 159 and 160 are NOR gates.

FIG. 12 is a waveform chart of the TE signal detection process in FIGS. 10 and 11. 10, 11, and 1
2, each waveform number a4, b4, a5, b5, a6, b6,
a7, b7, a8, b8, a9, and b9 are indicated by the waveform numbers of the corresponding signals.

In FIGS. 10 to 13, the portion composed of D flip-flops 151 and 153 and NOR gates 159 and 160 corresponds to the conventional phase comparator 26.
In addition to this, the monostable multivibrator 15
Pulses generated by D flip-flops 5 and 156 and D flip-flops 152 and 154 are supplied to NOR gates 159 and 160.

Monostable multivibrator 15
5, 156 are output signals a4, b4 of the external control delay unit 25.
At the rising edge (positive going pulse), signals a6 and b6 having a predetermined pulse width (Tlmt) are output. Signals a7, b inverted by inverters 157, 158
7 is supplied to the clock inputs of the D flip-flops 152 and 154, and the D flip-flops 152 and 154 are set with a delay of Tlmt from the signals a4 and b4 and the signal a
8, b8 are output. The D flip-flops 152 and 154 are reset by the falling of the signals a4 and b4 (negative going pulses).

Thus, the D flip-flops 151, 1
53 is set by the rise (positive going pulse) of the signals a4 and b4, and the NOR gate 15
9 and 160, the signal is reset by an earlier signal of the signals a4 and b4 and the signals a8 and b8. So, for example,
Even if one of the signals a2 and b2 is missing due to pit collapse, the signals a5 and b5 will be reset after Tlmt. In comparison with FIG. 31 of the related art, if there is a pit collapse region, a long charge pulse exceeding Ter1 and Ter2 is generated, whereas an error section Ter3 is generated.
Can be restricted to

In the circuit operation described above, the phase difference TE signal is generally ± 4 in a state where the phase difference is balanced.
A phase difference of about 5 degrees appears as an amplitude component. In tracking within a permissible deviation (for example, about ± 0.05 μm for a track pitch of 1.6 μm for CD), about ± several degrees (45 degrees x (±
0.05 / 0.4) = ± 5.6 degrees), so that unnecessary phase differences are desirably cut off. Therefore, the monostable multivibrators 155 and 15
6, the delay amount Tlmt corresponding to the unnecessary phase difference
Is set, a charge pulse suppressed to the error section Ter3 can be generated as shown by the waveform a5.

Therefore, in the above-described example of the CD, the delay amount Tlmt
Is calculated. For example, a delay amount corresponding to 5.6 degrees with respect to the longest pit frequency in the specified rotation is obtained. Assuming that the longest pit at standard speed of the above-mentioned CD is 11T (T is 4.32 MHz in channel bits), 1
Since the frequency f at 1T is 196 KHz, 5.6 degrees corresponding to one cycle (that is, 360 electrical degrees) is calculated as 5.6 / 360 × 1/196 KHz = 79 nsec.

As described above, according to the third embodiment of the present invention, the limit value can be set by the delay amount so that unnecessary phase difference information is not output to the phase comparator. Even if an abnormal comparator output signal is generated due to a collapsed area or the like, the phase difference error can be suppressed to a minimum.

(Embodiment 4) FIG. 13 is a basic configuration diagram of Embodiment 3 of the automatic frequency variable phase difference TE signal detector 109 shown in FIG. In FIG. 13, 21 is a signal detection detector, 22 is an IV converter, 23 is a waveform equalizer, 24 is a comparator, 25 is an external control delay, 27
Is a charge pump. Each of the circuit components described above has the same function as that of the conventional component, is given the same name and the same reference numeral, and redundant description is omitted.

Reference numeral 127 denotes a phase comparator with an automatic frequency variable limiter function of a circuit component which is different from the prior art and which is a feature of the present invention.
5, the limit value of the output phase difference can be set by the delay amount, and the delay amount can be automatically varied by the external input of the synchronous output signal PLCK of the PLL circuit 7.

FIG. 14 is a detailed circuit diagram of the phase comparator 127 with an automatic frequency variable limiter function shown in FIG. 14, 151, 152, 153 and 154 are D flip-flops, 157 and 158 are inverters, 159 and 16
0 is a NOR gate. These circuit components are the same as the circuit components of FIG. 11 in the third embodiment, and are denoted by the same reference numerals and names, and redundant description will be omitted.

Reference numerals 161 and 162 denote time constant automatic variable monostable multivibrators whose time constants can be varied according to an external input voltage level (Vplck). An FV converter 163 has the same function as the FV converter 133 described in the first embodiment with reference to FIGS. Synchronous output signal PLCK of PLL circuit 7 (see FIG. 1)
Through the FV converter 163 to obtain a linearly proportional voltage level Vplck. Further, the voltage level Vpl
By supplying ck to the automatically variable time constant monostable multivibrators 161 and 162, limit pulses are generated according to the relationship between the voltage level Vplck and the limit pulse width Tlmt shown in FIG.

FIG. 15 is a diagram showing the relationship between the voltage level Vplck and the limit pulse width Tlmt. As shown in FIG. 15, the limit pulse width Tlmt is equal to the voltage level Vp.
It is inversely proportional to the value of lck. That is, when the voltage level Vplck at the specified frequency is Vtyp, it is obtained as the limit pulse width Tlmt. Similarly, when the voltage level Vplck is 1.5 Vtyp (0.5 V
type), the limit pulse width Tlmt is 0.6
7 Vadj (same order as 2 Vadj).

As described above, according to the fourth embodiment of the present invention, the limit value can be set by the amount of delay so that unnecessary phase difference information is not output to the phase comparator. Therefore, even if an abnormal comparator output signal is generated due to the presence of a pit collapse area or the like on the optical disc, it is possible to suppress the phase difference error to a minimum. Further, since the above-mentioned limit value can be linearly changed in synchronization with the locked state of the PLL, the constant relation optimally set at the time of reproduction at the specified frequency is maintained in an optimum state according to the change in the reproduction frequency. Automatically variable. As a result, accurate phase difference information can be extracted even when the data signal deviates from the specified frequency during CAV reproduction or variable speed reproduction.

(Embodiment 5) Next, a control flow of the optical disk device according to Embodiment 5 of the present invention will be described.
FIGS. 16, 17, and 18 show abnormal operations such as the initial startup after loading the disc, the loss of focus due to external vibration or the like, and the loss of lock of the PLL circuit due to a seek error or the like. A flowchart for reliably and stably leading the optical disk device described in the first, second, and fourth embodiments of the present invention to a normal operation is shown.

According to the present invention, the frequency characteristic is automatically varied in accordance with the signal frequency by using the PLL output, so that it functions effectively in a normal operation state and operates reliably and stably. However, if any of the circuit blocks falls into an abnormal state, for example, out of focus → PLCK abnormality → f1, f
2 Abnormal setting → RF signal distortion → PLL malfunction → Masu P
An LCK abnormality → ... will fall into a vicious cycle loop, and will not be able to recover. Therefore, as shown in the control flow described below, in any of the PLCK states, an abnormal (runaway) state → a self-running state →
By always passing through the sequence of the rough lock state → lock state →..., The related circuit configuration blocks can function normally, and it is possible to avoid falling into a vicious cycle. Here, the self-running state refers to a state in which the rotation start control is performed as if the setting value is in an open loop control state, deviating from the PLL lock servo state, as described in detail in the following sequence.

(1) In order to lead to normal operation at the time of initial start-up after loading a disk. First, in FIGS. 1 and 16, the offset of the servo controller 11 is adjusted to start the spindle motor 2 and the initial start-up value is set. (S1). Then pick up 3
Is turned on (S2), and the motor driver 12 is turned on.
To start the spindle motor 2 (S3), and the focus is pulled in by the detection signal of the pickup 3 (S3).
4) Perform rough CLV control of the spindle motor 2 (S
5).

At this time, up to step 4, the PLL circuit 7
Since the PLL is not locked, the synchronous output signal PLCK is not output and the motor starts in a free-running state. On the other hand, the servo controller 11 does not output the balance adjustment signal TEBAL because the tracking servo is not synchronized, and the unset state continues.

Subsequently, when the number of revolutions of the spindle motor 2 is accelerated to a sufficient speed in step 5, the PLL circuit 7 locks the PLL and enters a locked state, outputs a synchronous output signal PLCK, and outputs the synchronous output signal PLCK. CL
V control is performed (S6). When the CLV control is performed, the servo controller 11 performs track balance adjustment (S7), outputs a balance adjustment signal TEBAL, and enters a set state.

Next, track pull-in is performed (S8),
The tracking servo can be synchronized. Subsequently, focus balance adjustment (S9) and focus gain adjustment (S1)
0) to start the focus servo.

Further, the gain of the tracking servo is adjusted (S11), and access to the TOC area is started (S1).
2) Perform TOC read (S13). Thus, the process proceeds to the next process.

(2) To Lead to Normal Operation When Out-of-focus Occurs First, in FIG. 1 and FIG. 17, when normal reproduction operation is continued and another object hits the optical disk device, for example. It is assumed that an out-of-focus state occurs due to an external vibration or the like (S21). At this time, until then
The PLL circuit 7 which has been in the LL lock state is released from the PLL lock, and becomes a runaway state. On the other hand, the servo controller 11
Although the tracking servo is released, the setting state at the time of startup continues, and the output of the balance adjustment signal TEBAL continues.

The servo signal detector 10 detects out of focus (S22), and the CPU 13 controls the motor driver 12 to stop the spindle motor 2 and the sled motor 4,
Both motors stop (S23).

The CPU 13 resets the PL from the locked state.
The L circuit 7 is reset (S24), the spindle motor 3 is started by the motor driver 12 (S25), and the focus is pulled back by the detection signal of the pickup 3 (S26), and rough CLV control of the spindle motor 2 is performed. Is performed (S27). At this time, from step 24 to step 26, since the PLL circuit 7 is not PLL-locked, the synchronous output signal PLCK is not output, and the PLL circuit 7 starts up in a free-running state.

Subsequently, when the number of revolutions of the spindle motor 2 is accelerated to a sufficient speed, the PLL circuit 7 locks the PLL and enters a locked state, and performs CLV control of the spindle motor 2 (S28). When the CLV control is performed, the track is pulled in (S29) and the synchronization of the tracking servo is continued. Thus, the process proceeds to the next process.

(3) In order to lead to normal operation when the PLL circuit is unlocked First, referring to FIGS. 1 and 18, when a failure occurs in the thread motor 4 at the time of a track jump during a normal reproduction operation, for example, Thus, it is assumed that a seek error or the like has occurred and the lock has been released (S31). At this time, the PLL circuit 7 which has been in the PLL locked state is released from the PLL locked state and becomes a runaway state. On the other hand, the servo controller 11 keeps the setting state at the time of start-up while tracking servo is released, and the output of the balance adjustment signal TEBAL continues.

The servo signal detector 10 detects that the PLL is unlocked (S32), the CPU 13 controls the motor driver 12 to stop the thread motor 4, and the thread motor 4 stops (S33).

The CPU 13 resets the PL out of the locked state.
The L circuit 7 is reset (S34), and rough CLV control of the spindle motor 2 is performed (S35). At this time,
From step 34 to step 35, since the PLL circuit 7 is not PLL-locked, the synchronous output signal PLCK is not output and the vehicle accelerates in a self-propelled state.

Subsequently, when the number of revolutions of the spindle motor 2 is accelerated to a sufficient speed, the PLL circuit 7 locks the PLL and enters a locked state, and performs CLV control of the spindle motor 2 (S36). When the CLV control is performed, the track is pulled in (S37), and the synchronization of the tracking servo is continued. Thus, the process proceeds to the next process.

As described above, according to the present invention, the clock is set to the specified frequency during the initial start-up after the disk is mounted, when the PLL circuit loses synchronization, and during a certain time immediately before synchronization is performed. By using the corresponding reference clock, the automatic frequency variable function can be reliably shifted to the normal operation.

[0085]

As described above, according to the present invention, accurate phase difference information can be extracted even in a state where a reproduced signal is deviated from a prescribed frequency component during CAV reproduction or variable speed reproduction.
Further, even if there is a pit collapse area on the disk, the phase error can be suppressed with a minimum, and an excellent optical disk apparatus capable of reproducing a phase difference track error signal with high reliability can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an optical disk device according to a first embodiment of the present invention.

FIG. 2 is a basic configuration diagram in Embodiment 1 of the frequency automatic variable phase difference TE signal detector of FIG. 1;

FIG. 3 is a detailed circuit diagram of an automatic frequency variable waveform equalizer.

FIG. 4 is a diagram illustrating frequency versus voltage characteristics of the automatic frequency variable waveform equalizer of FIG. 3 with respect to a data read clock signal.

FIG. 5 is a diagram showing a variable state of a frequency characteristic of the automatic frequency variable waveform equalizer of FIG. 3;

FIG. 6 is a basic configuration diagram of a frequency automatic variable phase difference TE signal detector according to a second embodiment of FIG. 1;

FIG. 7 is a detailed circuit diagram of an automatic frequency variable external control delay unit.

FIG. 8 is a diagram illustrating a relationship between a voltage level Vplck and an adjustment value TEBAL2.

FIG. 9 is a diagram showing a relationship between a delay amount and an adjustment value TEBAL2 of the voltage control delay device.

FIG. 10 is a basic configuration diagram of Embodiment 3 of the automatic frequency variable phase difference TE signal detector of FIG. 1;

FIG. 11 is a detailed circuit diagram of a phase comparator with a limiter function.

FIG. 12 is a waveform chart of a TE signal detection process in FIGS. 10 and 11;

FIG. 13 is a basic configuration diagram of a frequency automatic variable phase difference TE signal detector according to a third embodiment of FIG. 1;

FIG. 14 is a detailed circuit diagram of the phase comparator with the automatic frequency variable limiter function of FIG. 13;

FIG. 15 shows voltage level Vplck versus limit pulse width T.
Diagram showing the relationship with lmt

FIG. 16 is a flowchart for leading a normal operation at the time of initial startup after loading a disc;

FIG. 17 is a flowchart for leading a normal operation when an out of focus occurs.

FIG. 18 is a flowchart for leading a normal operation when the PLL circuit is unlocked;

FIG. 19 is a configuration diagram of a conventional optical disk device.

20 is a basic configuration diagram of the phase difference TE signal detector of FIG.

FIG. 21 is a diagram showing a light reception intensity distribution of a pit, a spot, and a lens surface.

FIG. 22 shows T at each circuit position in the basic configuration diagram of FIG. 20;
Waveform diagram of E signal detection process

FIG. 23 is a frequency characteristic diagram of the waveform equalizer.

FIG. 24 is a waveform chart showing a characteristic improvement effect of a waveform equalizer.

FIG. 25 is a detailed circuit diagram of an external control delay unit.

FIG. 26 is a characteristic diagram of a TEBAL signal versus a delay amount of the voltage control delay device.

FIG. 27 is a diagram showing a state of a phase balance of a TE signal.

FIG. 28 is a detailed circuit diagram of a phase comparator.

FIG. 29 is a detailed circuit diagram of a charge pump.

FIG. 30 is a diagram illustrating a frequency fluctuation of a data fundamental frequency in variable speed reproduction.

FIG. 31 is a waveform chart of a TE signal detection process in the case where pits are collapsed in the basic configuration diagram of FIG. 20;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Optical disk 2 Spindle motor 3 Pickup 4 Thread motor 5 RF signal detector 6 RF signal slicer 7 PLL circuit 8 Demodulator 9 Phase difference TE signal detector 10 Servo signal detector 11 Servo controller 12 Motor driver 13 CPU 14 Memory 21 Signal detection detector 22 IV converter 23 Waveform equalizer 24, 33, 143 Comparator 25 External control delay device 26 Phase comparator 27 Charge pump 31, 32, 141, 142 Voltage control delay device 34, 35, 144, 145 Analog Multiplexers 36, 43, 44, 148, 157, 158 Inverters 41, 42, 151, 152, 153, 154 D flip-flops 51, 52 Analog switches 53, 54 Constant current sources 55 Capacitors 109 Automatic frequency variable phase difference TE Signal detector 123 Automatic frequency variable waveform equalizer 125 Automatic frequency variable external control delay 126 Phase comparator with limiter function 127 Phase comparator with automatic frequency variable limiter function 131, 132 Voltage controlled frequency variable waveform equalizer 133, 147 , 163 FV converter 146 Analog divider 155, 156 Monostable multivibrator 159, 160 NOR gate 161, 162 Time constant automatic variable monostable multivibrator

Claims (10)

[Claims] An optical disk is irradiated with a light beam and reflected light is received by a plurality of light receiving elements, a data signal is generated by combining the sum and difference of the outputs of the light receiving elements, and is synchronized with the data signal by a PLL circuit. An optical disk device that generates a clock signal and generates a phase difference track error signal by combining the sum and difference of the outputs of the light receiving elements, and detects a received light current by combining the sum and difference of the outputs of the light receiving elements IV conversion means for converting to a voltage, a waveform equalizing means for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and an output obtained by the waveform equalizing means to a predetermined voltage. Voltage comparing means for comparing with a value to binarize the value, external control delay means for adjusting the amount of delay of the phase difference balance of the output of the voltage comparing means by an external signal, A phase comparing unit that detects a phase difference between outputs of the delay unit; and a charging / discharging unit that performs charging / discharging of the power storage unit based on an output of the phase comparing unit. An optical disk device, wherein the frequency characteristic is changed so as to be in a proportional relationship by an external signal having a proportional relationship with a frequency of the clock signal in synchronization. 2. An optical disk is irradiated with a light beam and reflected light is received by a plurality of light receiving elements, a data signal is generated by combining the sum and difference of outputs of the light receiving elements, and the data signal is synchronized with the data signal by a PLL circuit. And generating a clock signal, and combining the sum and difference of the outputs of the light receiving elements to generate a phase difference track error signal, wherein the sum and difference of the outputs of the light receiving elements are combined and received. An IV conversion step of converting a current into a detection voltage, a waveform equalization step of amplifying a predetermined frequency band of the detection voltage with a higher amplification factor than other frequency bands, and an output obtained in the waveform equalization step. A voltage comparing step of binarizing by comparing with a predetermined voltage value, and adjusting a delay amount of a phase difference balance of an output of the voltage comparing step by an external signal. An external control delay step, a phase comparison step of detecting a phase difference between outputs of the external control delay step, and a charge / discharge step of charging / discharging a power storage unit based on an output of the phase comparison step, wherein the waveform The track error signal generating method according to claim 1, wherein in the equalizing step, the frequency characteristic is varied so as to have a proportional relationship with an external signal having a proportional relationship with the frequency of the clock signal in synchronization with the clock signal. 3. An optical disk is irradiated with a light beam, the reflected light is received by a plurality of light receiving elements, a data signal is generated by combining the sum and difference of the outputs of the light receiving elements, and the data signal is synchronized with the data signal by a PLL circuit. An optical disk device that generates a clock signal and generates a phase difference track error signal by combining the sum and difference of the outputs of the light receiving elements, and detects a received light current by combining the sum and difference of the outputs of the light receiving elements IV conversion means for converting to a voltage, a waveform equalizing means for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and an output obtained by the waveform equalizing means to a predetermined voltage. Voltage comparing means for comparing with a value to binarize the value, external control delay means for adjusting the amount of delay of the phase difference balance of the output of the voltage comparing means by an external signal, A phase comparing unit that detects a phase difference between outputs of the delay unit; and a charging / discharging unit that performs charging / discharging of the power storage unit based on the output of the phase comparing unit. An optical disk device, wherein the delay amount is changed so as to be in inverse proportion with an external signal having an inverse proportion with the frequency of the clock signal. 4. An optical disk is irradiated with a light beam, the reflected light is received by a plurality of light receiving elements, a data signal is generated by combining the sum and difference of the outputs of the light receiving elements, and the data signal is synchronized with the data signal by a PLL circuit. And generating a clock signal, and combining the sum and difference of the outputs of the light receiving elements to generate a phase difference track error signal, wherein the sum and difference of the outputs of the light receiving elements are combined and received. An IV conversion step of converting a current into a detection voltage, a waveform equalization step of amplifying a predetermined frequency band of the detection voltage with a higher amplification factor than other frequency bands, and an output obtained in the waveform equalization step. A voltage comparing step of binarizing by comparing with a predetermined voltage value, and adjusting a delay amount of a phase difference balance of an output of the voltage comparing step by an external signal. An external control delay step; a phase comparison step of detecting a phase difference between outputs of the external control delay step; and a charge / discharge step of charging / discharging a power storage unit based on an output of the phase comparison step. The method of generating a track error signal, wherein the control delay step varies the delay amount so as to have an inverse proportional relationship with an external signal having an inverse proportional relationship with the frequency of the clock signal in synchronization with the clock signal. 5. An optical disk is irradiated with a light beam and reflected light is received by a plurality of light receiving elements, a data signal is generated by combining the sum and difference of outputs of the light receiving elements, and the data signal is synchronized with the data signal by a PLL circuit. An optical disk device that generates a clock signal and generates a phase difference track error signal by combining the sum and difference of the outputs of the light receiving elements, and detects a received light current by combining the sum and difference of the outputs of the light receiving elements IV conversion means for converting to a voltage, a waveform equalizing means for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and an output obtained by the waveform equalizing means to a predetermined voltage. Voltage comparing means for comparing with a value to binarize the value, external control delay means for adjusting the amount of delay of the phase difference balance of the output of the voltage comparing means by an external signal, A phase comparing means for detecting a phase difference of an output of the delay means; and a charging / discharging means for charging / discharging a power storage means based on an output of the phase comparing means. An optical disk device, which is a phase comparison means with a limit function for setting a limit value of the above-mentioned delay amount according to the delay amount. 6. An optical disk is irradiated with a light beam, the reflected light is received by a plurality of light receiving elements, a data signal is generated by combining the sum and difference of outputs of the light receiving elements, and the data signal is synchronized with the data signal by a PLL circuit. And generating a clock signal, and combining the sum and difference of the outputs of the light receiving elements to generate a phase difference track error signal, wherein the sum and difference of the outputs of the light receiving elements are combined and received. An IV conversion step of converting a current into a detection voltage, a waveform equalization step of amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and an output obtained in the waveform equalization step. A voltage comparing step of binarizing by comparing with a predetermined voltage value, and adjusting a delay amount of a phase difference balance of an output of the voltage comparing step by an external signal. An external control delay step, a phase comparison step of detecting a phase difference between outputs of the external control delay step, and a charge / discharge step of charging / discharging a power storage unit based on an output of the phase comparison step. The track error signal generating method according to claim 1, wherein the comparing step is a phase comparing step with a limit function for setting a limit value of the phase difference of the output based on the delay amount. 7. An optical disk is irradiated with a light beam and reflected light is received by a plurality of light receiving elements, a data signal is generated by combining the sum and difference of outputs of the light receiving elements, and the data signal is synchronized with the data signal by a PLL circuit. An optical disk device that generates a clock signal and generates a phase difference track error signal by combining the sum and difference of the outputs of the light receiving elements, and detects a received light current by combining the sum and difference of the outputs of the light receiving elements IV conversion means for converting to a voltage, a waveform equalizing means for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and an output obtained by the waveform equalizing means to a predetermined voltage. Voltage comparing means for comparing with a value to binarize the value, external control delay means for adjusting the amount of delay of the phase difference balance of the output of the voltage comparing means by an external signal, A phase comparing means for detecting a phase difference of an output of the delay means; and a charging / discharging means for charging / discharging a power storage means based on an output of the phase comparing means. A phase comparison means having a limit function for setting the limit value of the delay amount according to the delay amount, wherein the delay amount is inversely proportional to an external signal having an inverse relationship with the frequency of the clock signal in synchronization with the clock signal. An optical disk device characterized by being variable. 8. An optical disk is irradiated with a light beam, the reflected light is received by a plurality of light receiving elements, a data signal is generated by combining the sum and difference of the outputs of the light receiving elements, and the data signal is synchronized with the data signal by a PLL circuit. And generating a clock signal, and combining the sum and difference of the outputs of the light receiving elements to generate a phase difference track error signal, wherein the sum and difference of the outputs of the light receiving elements are combined and received. An IV conversion step of converting a current into a detection voltage, a waveform equalization step of amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and an output obtained in the waveform equalization step. A voltage comparing step of binarizing by comparing with a predetermined voltage value, and adjusting a delay amount of a phase difference balance of an output of the voltage comparing step by an external signal. An external control delay step, a phase comparison step of detecting a phase difference between outputs of the external control delay step, and a charge / discharge step of charging / discharging a power storage unit based on an output of the phase comparison step; The comparing step is a phase comparing step with a limit function of setting a limit value of the phase difference of the output based on the delay amount, and the external signal having an inverse proportional relationship with the frequency of the clock signal in synchronization with the clock signal. A method for generating a track error signal, wherein a delay amount is varied so as to have an inversely proportional relationship. 9. An optical disk is irradiated with a light beam and reflected light is received by a plurality of light receiving elements, a data signal is generated by combining the sum and difference of outputs of the light receiving elements, and the data signal is synchronized with the data signal by a PLL circuit. An optical disk device for generating a clock signal and generating a phase difference track error signal by combining the sum and difference of the outputs of the light receiving elements to synchronize the optical disk rotating means with the data signal. IV conversion means for combining the sum and difference of the outputs of the elements to convert the received light current into a detection voltage, waveform equalization means for amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, A voltage comparing means for comparing an output obtained by the waveform equalizing means with a predetermined voltage value to binarize the output, and a phase difference balance between outputs of the voltage comparing means by an external signal External control delay means for adjusting the delay amount, phase comparison means for detecting a phase difference between outputs of the external control delay means, and charge / discharge means for charging / discharging the power storage means based on the output of the phase comparison means, Control means for controlling the operation of each means in charge of the entire apparatus, wherein the control means is adapted to synchronize with the data signal by the PLL circuit from a control state in which the servo control by the PLL circuit is not synchronized. During the period of the control state until the clock signal is generated, the external control delay unit and the phase comparison unit have an acceleration control that performs a rotational drive based on a predetermined value set in advance without using an external signal. An optical disc device characterized by the above-mentioned. 10. An optical disk is irradiated with a light beam and reflected light is received by a plurality of light receiving elements, and a data signal is generated by combining the sum and difference of outputs of the light receiving elements.
An optical disk that generates a clock signal in synchronization with the data signal by a circuit, generates a phase difference track error signal by combining the sum and difference of the outputs of the light receiving elements, and synchronizes the optical disk rotating means with the data signal In the driving method, in a control process from a control process in which servo control by the PLL circuit is not synchronized to a process in which the PLL circuit generates the clock signal in synchronization with the data signal, the output of the light receiving element is controlled. An IV conversion step of combining a sum and a difference to convert a received light current to a detection voltage, a waveform equalization step of amplifying a predetermined frequency band of the detection voltage with a higher amplification degree than other frequency bands, and the waveform equalization step A voltage comparison step of comparing the output obtained in step 2 with a predetermined voltage value to binarize the output, and an output of the voltage comparison step An external control delay step of adjusting a delay amount of the phase difference balance by an external signal, a phase comparison step of detecting a phase difference of an output of the external control delay step, and charging of the power storage means based on the output of the phase comparison step. A charging / discharging step of performing a discharge, wherein the external control delaying step and the phase comparing step include an acceleration control step of performing a rotational drive based on a predetermined set value not depending on an external signal. Optical disk driving method.