JPH10301983A - Power consumption calculation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prepare a library without depending on an operation voltage condition by describing pull-up/pull-down resistance values for the respective terminals of respective logic blocks in the library. SOLUTION: The library 10 is provided with the resistance data of the pull-up resistance, pull-down resistance and leakage resistance, etc., of the respective kinds of the logic blocks and a coefficient or the like used at the time of calculating the leakage power consumption of the logic block. Then, a power consumption calculation device 14 inputs the respective resistance data taken out from the library 10, the time (operation voltage data 12) after the time of starting logical simulation until the time of ending it, optional operation time 13 supplied by input and logical simulation data 11 constituted of input round data, the number of times of switching and the time-based ratio data of High/ Low and calculates pull-up/pull-down power consumption. Further, calculated switching power and leakage power are added and the power consumption 19 of the logic block is calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for calculating power consumption, and more particularly to a method for calculating power consumption in LSI (semiconductor integrated circuit) design.

[0002]

2. Description of the Related Art As a method of calculating power consumption when designing a semiconductor integrated circuit, a method is used in which a power consumption value for each operating voltage is described in a library for each logical block.

FIG. 9 shows a schematic configuration of a conventional power consumption calculation system proposed in Japanese Patent Application Laid-Open No. 5-265605. Referring to FIG. 9, information of a data storage unit 90 including connection data 91 of a logic MOS block such as a MOS gate and a MOS buffer, power consumption data 92 of various logic blocks, and operation data 93 of various MOS logic blocks. Is input to the power consumption calculator 19.
The operation data 93 includes an operation frequency indicating an operation speed of various MOS logic blocks, operation rate data indicating an operation ratio,
It includes data such as signal ratio data indicating the ratio of the input or output signal level.

[0004] A power consumption calculating unit 14 calculates power consumption Ps due to switching and leakage power consumption Pr.

Specific power consumption Pi for each MOS logic block
By multiplying the operating frequency fi by the operating rate re,
The switching power consumption Ps is calculated (see the following equation (1)).

Ps = Pi × fi × re (1)

Power consumption data Ph and Pl and signal ratio r for each input or output signal level for each MOS logic block
The leakage power Pr is calculated using h and rl (see the following equation (2)).

[0008] Pr = (Ph x rh) + (Pl x rl) (2)

The total power consumption P is calculated by adding the switching power consumption Ps and the leak power consumption Pr (see the following equation (3)).

P = Ps + Pr (3)

[0011]

However, the above-described conventional power consumption calculation method has the following problems.

(1) The first problem is that it is difficult to obtain power other than the assumed operating voltage when creating a library. In addition, if data corresponding to a large number of operating voltages is described, the description amount of the library becomes enormous.

The reason is that in the above-mentioned conventional method, the power consumption value for each operating voltage is directly described in the library.
That's why.

(2) The second problem is that an accurate power consumption value cannot be calculated.

When the input potential changes from High to Low or from Low to High, the n-channel transistor and the p-channel transistor are temporarily turned off simultaneously.
It is an intermediate state that is not FF. The power consumed at this time is defined as “leak power consumption” (also referred to as “through current”). Also, virtually n-channel transistors,
A p-channel transistor acts like a resistor. This resistance is defined as “leak resistance”.

In the above-mentioned conventional method, since the leakage power is made uniform for each logical block, an accurate power consumption value cannot be calculated when the input waveform becomes rounded. In addition, if a large number of input waveform roundings are described in data, the description amount of the library becomes enormous.

The reason is that the leak power consumption value for each block is described in the library.

Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to describe a pull-up / pull-down resistance value for each terminal of each logic block in a library so that an operating voltage condition can be obtained. It is an object of the present invention to provide a power consumption calculation method and a system capable of creating a library without depending on the power consumption.

Another object of the present invention is to provide a power consumption calculation method and system in which a library can be created by describing a leak resistance value in the library without considering rounding of an input waveform. .

Still another object of the present invention is to provide a power consumption calculation method and system in which only one resistance value for each terminal needs to be described in a library, and the amount of description in the library is reduced.

[0021]

According to a power consumption calculation method of the present invention that achieves the above object, a resistance value of a block is extracted from a library and power consumption for a specified operation power is calculated.

That is, the present invention is characterized in that the resistance value is described in the library in advance, and the power consumption under the operating voltage of the logic block is calculated by a predetermined power consumption calculation formula.

Further, according to the present invention, a terminal of a block, a pull-up and pull-down resistance value, a leak resistance value, and a leak power calculation coefficient are stored in a library in advance, and a logic circuit block corresponding to a given voltage condition is stored. Switching power, pull-up and pull-down power, and leak power are calculated, and the sum of these is used as power consumption.

[Summary of the Invention] In the present invention, the library has a pull-up / pull-down resistance value (33 in FIG. 6).
And 34), a leak resistance value (50 in FIG. 6), and a leak power calculation coefficient (61 in FIG. 6).

The power consumption calculator (14 in FIG. 1) includes a pull-up / pull-down power consumption calculator (16 in FIG. 1),
It has a leak power consumption calculator (17 in FIG. 1) and an overall power consumption calculator (18 in FIG. 1).

In the present invention, the resistance value is described in advance in the library, instead of the power consumption value. Therefore, in the present invention, the power consumption calculation unit can calculate the power consumption using the resistance value described in the library and an arbitrary operating voltage value given by the input.

In the present invention, it is preferable that the library calculate resistance data such as pull-up resistance, pull-down resistance and leak resistance of various logic blocks such as inverters and flip-flops and calculate leakage power consumption of the logic blocks. Is prepared in advance, and the input rounding data of the logic block, the number of switching times at which the block rises and falls within a certain time, and the High number of the logic block within a certain time are prepared. A switching power calculating means for calculating power generated at the time of rising or falling transition of a signal of a logic block, comprising: logic simulation data including data obtained by calculating a ratio of a state or a low state; and the logic block. Pull-up resistor and pull-down resistor connected to Power consumption comprising: pull-up / pull-down power calculation means for calculating the power generated from the current flowing through the circuit; and leakage power calculation means for calculating the leak power generated when the input potential of the logic block enters an intermediate state. It has a calculating device, the power consumption calculating device,
Inputting resistance data such as a pull-up resistor, a pull-down resistor, and a leak resistor extracted from the library and the logic simulation data 1, and
The pull-down power calculation means includes a pull-up resistance data,
Pull-down resistance data, operating voltage data and High /
Pull-up / pull-down power consumption is calculated from the low-level time ratio data and the operation time, and the switching power calculation means calculates switching power from the number of switching times and the power consumed in one switching, and the like, The leak power calculating means calculates the leak power from the leak resistance, the leak power calculation coefficient, and the operating voltage data, and adds the calculated switching power, the pull-up / pull-down power, and the leak power to generate a logic block. Is calculated. Each of these power calculation means may be realized by a program executed by an information processing device such as a computer.

[0028]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

[0029]

Embodiment 1 FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention. Referring to FIG. 1, in a first embodiment of the present invention, a library 10 includes:
It includes a power consumption calculation device 14, logic simulation data 11, and an output device 19.

The library 10 includes resistance data such as pull-up resistors, pull-down resistors, and leak resistors of various logic blocks such as inverters and flip-flops, and coefficients used when calculating the leak power consumption of the logic blocks. ing. The coefficient used when calculating the leak power consumption is called "leak power calculation coefficient".

The logic simulation data 11 includes input round data of a logic block and rise (rise) and fall (f) of the block within a specific time.
all), and data such as data (High / Low temporal ratio data) obtained by calculating the ratio of a logical block being in a High state or a Low state within a specific time.

The power consumption calculating device 14 calculates the power generated when the signal changes between rise and fall of the logic block, and calculates the switching power calculated by the switching power calculator 15 and the current flowing through the pull-up / pull-down resistor connected to the logic block. A pull-up / pull-down power calculator 16 for calculating the generated power, and a leak power calculator 17 for calculating a leak power generated when the logic block enters the intermediate state.
And is composed of Each of these power calculation units may be realized by a program executed by an information processing device such as a computer.

The power consumption calculation device 14 is provided with the library 10
Resistance data such as pull-up resistance, pull-down resistance, and leak resistance extracted from the above, the time from the time when the logic simulation starts to the time when it ends (operation voltage data 15), an arbitrary operation time 13 given by input, and the input Round data, number of switchings, and High / Lo
Logic simulation data 11 composed of time ratio data of w is input.

The power consumption calculator 14 calculates the pull-up resistance data, the pull-down resistance data, and the operating voltage data 1
2, the pull-up / pull-down power consumption is calculated from the time ratio data of High / Low level and the operation time 13 or the like.

Further, switching power is calculated from the number of times of switching and the power consumed in one switching.

The leak power is calculated from the leak resistance, the leak power calculation coefficient, the operating voltage data 12 and the like.

The calculated switching power, the pull-up / pull-down power, and the leak power are added to calculate the power consumption 19 of the logical block.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS.

The library 10, the logic simulation data 11, the operating voltage data 12, and the operating time 13 are supplied to the power consumption calculator 14 (step 2).
0).

The pull-up resistance data, the leak resistance data, and the leak power calculation coefficient are extracted from the library 10 (step 21).

From the logic simulation data, input round data, switching frequency data, High /
The low-level time ratio data is extracted (step 22).

The switching frequency data and one switching power consumption are supplied to the switching power calculator 15 to calculate the switching power Ps (step 2).
3).

The pull-up resistance data, pull-down resistance data, operating power data 12, high / low level time ratio data, and operating time 13 are supplied to a pull-up / pull-down power calculating unit 16, Calculate the up / down power Ppd (Step 2)
4).

The leak resistance data and the leak power calculation coefficient are supplied to the leak power calculator 17 to calculate the leak power Pr (step 25).

The power consumption calculator 18 calculates the power consumption 19 by adding the switching power Ps, the pull-up / pull-down power Ppd, and the leak power Pr (step 26), and outputs the power consumption 19 (step 27). .

Next, the operation and effect of the first embodiment of the present invention will be described. In the first embodiment of the present invention, the power consumption is calculated using the resistance data, so that the first embodiment can correspond to any operating voltage value. Further, since the data stored in the library may be one resistance value, the amount of data stored in the library is reduced.

[0047]

Embodiment 1 Next, the embodiment of the present invention will be described in more detail with reference to an embodiment of the present invention.

Referring to FIG. 6, the library 10 includes a logical block name 60 and a logical block leak resistance value 50.
And a leak power calculation coefficient 61, an input terminal name 30, an output terminal name 31, and a pull-up resistance value 33 and a pull-down resistance value 34 connected to each terminal.
It is composed of

Referring to FIG. 1, power consumption calculating device 14
Comprises a switching power calculation unit 15, a pull-up / pull-down power calculation unit 16, a leakage power calculation unit 17, and a power consumption calculation unit 18 for calculating the total power consumption.

Referring to FIG. 3, FIG. 4, and FIG. 5, the calculation method of these calculation units will be described. FIG. 3 is a diagram showing the circuit configuration of the input buffer, and FIG. 4 is a diagram showing the transistor-level circuit configuration of the input buffer. FIG.
FIG. 4 is a diagram for explaining an embodiment of the present invention, and is a diagram illustrating a method of calculating leakage power consumption.

First, a method of calculating the switching power Ps will be described.

From the logic simulation data 11 to the buffer 32, rise / fa
The number of switchings N to perform ll is obtained. The switching power Ps is calculated by the following equation (4) by multiplying this by a single switching power consumption ΔW and the operation time T.

Ps = ΔW × (N / ΔT) × T (4)

Next, the pull-up / pull-down power Ppd
The calculation method of will be described.

With reference to FIG.
When the h level signal is input to the buffer 32, the output signal of the buffer 32 changes to a low level. At this time,
A current flows from the pull-up resistor Rp connected to the buffer 32 to the buffer 32. Considering the transistor level shown in FIG.
Since 1 and Q2 are in the OFF and ON states, a current flows from the power supply VDD to the pull-up resistor Rp to Q2. The pull-up power Pp is equal to the pull-up resistance Rp
The power increases in proportion to the time passed to the power supply.

The time T1 when the output signal of the buffer 32 is at the low level is determined by the logic simulation data Hig.
It can be calculated from the time ratio data Ht at the h / Low level and the operation time T. Here, Ht indicates the ratio of the High level to the entire operation time.

T1 = (1−Ht) × T (5)

Using the above equation (5), the pull-up power Pp generated at the operating voltage VDD is calculated by the following equation (6).

Pp = ((VDD × VDD) / Rp) × T1 (6)

In the above equation (6), Rp represents a pull-up resistance value 33 extracted from the library 10.

When a Low level signal is input from the input terminal 30 to the buffer 32, the output signal of the buffer 32 becomes H
changes to the high level. At this time, a current flows from the buffer 32 to the pull-down resistor Rd connected to the buffer 32. Considering at the transistor level, Q1 and Q2 of the buffer 32 are turned ON and OFF.
A current flows from 1 to a pull-down resistor Rd connected to GND.

The pull-down power Pd increases in proportion to the time flowing through the resistor Rd. The time Th during which the output signal of the buffer 32 is at the high level can be calculated from the high / low level temporal ratio data Ht of the logic simulation data and the operation time T.

Th = Ht × T (7)

Using the above equation (7), the pull-down power Pd generated at the operating voltage VDD is calculated by the following equation.

Pd = ((VDD × VDD) / Rd) × Th (8)

Therefore, the pull-up / pull-down power consumption Ppd is obtained from the above equations (6) and (8) as follows: Ppd = Pp + Pd (9)

Next, a method of calculating the leak power Pr will be described.

At the moment when the potential of the buffer 32 changes, the transistors Q1 and Q2 are temporarily turned on. At this time, a current flows from the power supply VDD to the ground through the transistors Q1 to Q2, so that power is generated. This leak power Pr increases in proportion to the input rounding Trf.

Therefore, the leakage power Pr generated at the operating voltage VDD is calculated by the following equation (10).

Pr = Kr × ((VDD × VDD) / Rr) × Trf (10)

Here, Rr and Kr are the leak resistance value 50 and the leak power calculation coefficient 61 extracted from the library 10, respectively.

The power consumed by the block 32 is obtained by adding the switching power Ps, the pull-up / pull-down power Ppd, and the leak power Pr calculated from the equations (4), (9) and (10).

P = Ps + Ppd + Pr (11)

[0074]

Embodiment 2 Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 7, the second embodiment of the present invention includes a circuit simulator SPICE level circuit data 70, a logic simulation data 11, a power consumption calculating device 14, and an output device 19.

Referring to FIG. 7, according to the second embodiment of the present invention, instead of library 10 in the first embodiment shown in FIG. 1, circuit data 70 of a circuit simulator SPICE level is used for power consumption calculation. It differs in that it is input to the device 14.

The circuit data 70 at the SPICE level can implement the present invention instead of the library 10 if the logic block is composed of transistors, resistors, capacitors, and the like.

Pull-up / pull-down power calculator 17
Are resistance data such as pull-up resistance and pull-down resistance extracted from the circuit data 70 at the SPICE level, arbitrary operating voltage data 12 and operating time 13 given by the input, input round data extracted from the logic simulation data 11, switching Number of times and Hi
gh / Low level time ratio data and pull-up / pull-down power are calculated.

Next, the operation of the second embodiment of the present invention will be described in detail with reference to the drawings.

Except for the operation of the resistance data calculating means in the second embodiment shown in step 81 of FIG.
Therefore, the description is omitted.

A method of calculating the pull-up / pull-down resistance from the SPICE level circuit data 70 will be described.

In the wiring from the MOS or transistor connected to the input terminal of interest to the MOS or transistor in the next stage, the sum of the respective resistance values connected to VDD and GND is calculated, and the result is used as the pull-up resistance data. And pull-down resistance data.

[0083]

Embodiment 2 Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 7, instead of the library 10 shown in FIG.
The difference is that 0 is input to the power consumption calculation device 14. SP
The ICE level circuit data 70 constitutes a logic block with transistors, resistors, capacitors, and the like.

Pull-up / pull-down power calculator 17
Are resistance data such as pull-up resistance and pull-down resistance extracted from the circuit data 70 at the SPICE level, arbitrary operating voltage data 12 and operating time 13 given by the input, input round data extracted from the logic simulation data 11, switching Number of times and Hi
gh / Low level time ratio data and pull-up / pull-down power are calculated.

Next, the operation of the second embodiment of the present invention will be described in detail with reference to the drawings.

The operation is the same as that of the first embodiment except for the operation of the resistance data calculating means in the second embodiment shown in step 81 of FIG. 8, and the description is omitted.

A method of calculating the pull-up / pull-down resistance from the SPICE level circuit data will be described. In the wiring from the MOS or transistor connected to the input terminal of interest to the MOS or transistor at the next end, the sum of the respective resistance values connected to VDD and GND is calculated, and the result is calculated as pull-up resistance data and pull-down resistance. Data.

[0089]

As described above, according to the present invention,
The following effects are obtained.

(1) A first effect of the present invention is that a library can be created without depending on operating voltage conditions by describing a pull-up / pull-down resistance value for each terminal of each logic block in the library. That is.

The reason for this is that, in the present invention, one pull-up / pull-down resistance value needs to be described in the library for each terminal of each logical block, so that the amount of description in the library is reduced. In addition, this is to cope with any operating voltage condition.

(2) A second effect of the present invention is that a library can be created without considering rounded input waveforms by describing a leak resistance value in the library.

The reason is that, in the present invention, the leak power consumption is calculated in consideration of the value of the rounding of the input waveform.

[Brief description of the drawings]

FIG. 1 is a configuration diagram schematically showing a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method for calculating power consumption according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining one embodiment of the present invention;
FIG. 3 is a diagram illustrating a circuit for explaining a method of calculating power consumption.

FIG. 4 is a diagram for explaining one embodiment of the present invention;
FIG. 4 is an explanatory diagram illustrating a method of calculating pull-up / pull-down power consumption.

FIG. 5 is a diagram for explaining one embodiment of the present invention;
FIG. 4 is an explanatory diagram illustrating a method of calculating leakage power consumption.

FIG. 6 is an explanatory diagram illustrating a configuration of a library according to the embodiment of this invention.

FIG. 7 is a diagram showing a schematic configuration of a second embodiment of the present invention.

FIG. 8 is a flowchart illustrating a method for calculating power consumption according to the second embodiment of the present invention.

FIG. 9 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 1 power consumption calculation device 10 library 11 logic simulation data 12 operating voltage data 13 operation time 14 power consumption calculation device 15 switching power calculation unit 16 pull-up / pull-down power calculation unit 17 leak power calculation unit 18 power consumption calculation unit 19 power consumption 30 Input terminal 31 Output terminal 32 Buffer with pull-up / pull-down resistor 33 Pull-up resistor 34 Pull-down resistor 40 Transistor (Q1) 41 Transistor (Q2) 50 Overall leak resistance 51 Leak resistance (Q1) 52 Leak resistance (Q2) 60 Block name 61 Leakage power calculation coefficient 70 SPICE circuit data 90 Data storage unit 91 Connection data 92 Power consumption data 93 Operation data

Claims (4)

[Claims] 1. A resistance value is previously described in a library,
A power consumption calculation method, wherein power consumption under an operating voltage of a logic block is calculated by a predetermined power consumption calculation formula. 2. A library in which a terminal of a block, a pull-up and pull-down resistance value, a leak resistance value, and a leak power calculation coefficient are stored in advance, and a switching power of a logic block with respect to a given voltage condition, A power consumption calculation method comprising calculating pull-up and pull-down power and leak power, and using the sum of these as power consumption. 3. The library includes resistance data such as pull-up resistance, pull-down resistance, and leak resistance of various logic blocks such as inverters and flip-flops, and a leak power calculation coefficient used when calculating the leak power of the logic blocks. Are prepared in advance, and the input round data of the logical block, the number of switching times at which the block rises and falls within a specific time, and the Hig of the logic block within a specific time.
switching power calculation means for calculating power generated at the rise and fall transitions of a signal of a logic block, comprising logic simulation data including data obtained by calculating the ratio of h state or low state; Pull-up / pull-down power calculation means for calculating power generated from current flowing through the pull-up and pull-down resistors connected to the block, and leak power for calculating leak power generated when the input potential of the logic block is in an intermediate state Calculating means, comprising: a power consumption calculating device comprising: a power consumption calculating device that inputs resistance data such as a pull-up resistor, a pull-down resistor, and a leak resistor extracted from the library and the logic simulation data. The pull-up / pull-down power calculation means, A pull-up resistance data, and a pull-down resistance data, and the time ratio data operating voltage data and High / Low level,
The switching power calculation means calculates the switching power from the number of switching times and the power consumed by one switching, and the like, and the leakage power calculation means calculates the leakage power from the operating time and the like. Calculating the leak power from the resistance, the leak power calculation coefficient, and the operating voltage data, and calculating the power consumption of the logic block by adding the calculated switching power, the pull-up / pull-down power, and the leak power. A power consumption calculation system characterized by the following. 4. A resistance data such as a pull-up resistor, a pull-down resistor and a leak resistor of various logic blocks such as an inverter and a flip-flop, and a leak power calculation coefficient used when calculating a leak power of the logic block. Resistance data such as pull-up resistance, pull-down resistance, and leak resistance extracted from a library stored in advance, input round data of a logic block, and switching count data at which a block rises and falls within a specific time; The logic block is set to H
(a) pull-up resistance data, pull-down resistance data, operation voltage data, and high / low logic data of a logic block with reference to logic simulation data including data in which the ratio of the high state or the low state is calculated. Low
A process of calculating the power consumption flowing through the pull-up resistor and the pull-down resistor of the logic block from the time ratio data of the level and the operation time; (b) the logic from the number of switching times and the power consumed by one switching; (C) a process of calculating a switching power in the block, (c) a process of calculating a leak power generated when the input potential of the logic block is in an intermediate state from the leak resistance and the leak power calculation coefficient, and operating voltage data, A) calculating the power consumption of the logic block by adding the calculated switching power, the pull-up / pull-down power, and the leak power; recoding media.