JPH10294383A - Input protection diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input protection diode circuit enabling micromachining. SOLUTION: An input-protected diode 10 includes an NMOS transistor and a PMOS transistor as circuit elements, and is provided at a signal input line connected to a MOSFET of an internal circuit, and a gate electrode and a P-well of the NMOS transistor are shorted with an earth electrode, and a gate electrode and a N-well of the PMOS transistor are connected to a supply voltage (Vcc), and a source and a drain of the NMOS transistor and a source and a drain of the PMOS transistor are connected respectively to the signal input line. Moreover the input-protected diode 10 is connected to a gate electrode of the MOSFET of the internal circuit via a protective resistance R constituting a time constant circuit together with parasitic capacitors C1 and C2 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for connecting a
The present invention relates to an input protection diode provided on a signal input line input to an FET, and more particularly to an input protection diode that is miniaturized and has high efficiency and high reliability.

[0002]

2. Description of the Related Art In a semiconductor device having a MOSFET in an internal circuit, when a signal is input to an input / output pad and a signal is input to a gate electrode of the MOSFET via a signal input line,
Excessive signal voltage is applied to the gate electrode of the MOSFET via the input / output pad due to the noise accompanying the signal,
In some cases, dielectric breakdown of the gate electrode may be caused. Therefore, usually, a protection circuit including an input protection diode is provided on a signal input line connecting the input / output pad and the MOSFET.

FIG. 6 shows a conventional input protection diode circuit.
The circuit configuration is as shown in FIG. In particular,
The protection diode circuit consists of NMOSFET and PMOSF
ET and PMOSFET gate,
The N-well and the source are respectively connected to the power supply voltage (Vc
c), the gate, P-well, and source of the NMOSFET are short-circuited to the ground electrode (GND), respectively, and the drains of both MOSFETs are connected to the signal input line. The input protection diode is further connected to the gate electrode of the MOSFET in the internal circuit via a protection resistor R forming a time constant circuit together with the parasitic capacitances C1 and C2.

In the input protection diode, when a signal voltage higher than the power supply voltage is input, the PN junction of the PMOSFET becomes a forward direction, a current flows, and a signal voltage lower than GND is input. And the NMOSFET P-
An excessive voltage is not applied to the gate electrode of the MOSFET in the internal circuit due to the current flowing through the N junction in the forward direction. When a voltage significantly higher than the power supply voltage is input, the P-
The N-junction flows in the forward direction and the NMOSFET
The excessive current is prevented from being applied to the gate electrode of the internal circuit due to the current flowing when the PN junction is broken at the gate end. In this case, the current of the NMOSFET is dominant. When a voltage significantly lower than GND is input, the current flowing in the forward direction through the PN junction of the NMOSFET and the PN
An excessive voltage is not applied to the gate electrode of the MOSFET in the internal circuit due to the current flowing when the junction is broken at the gate end. In this case, the PMOSF
The ET current is dominant.

[0005] The NMOSFET and PMOSFET used in the conventional input protection diode are both
It is formed as a basic MOSFET structure. NM
The OSFET (or PMOSFET) is a P-well or P-type substrate (PMO) as shown in FIGS.
LOC on N-well or N-type substrate for SFET) 12
A gate oxide film, a gate electrode, an interlayer insulating film, a gate oxide film, an N-well or an N-type substrate in an active region separated by the device isolation region; A wiring 22 is connected to the electrode 18, a wiring 24 is connected to the source region, and a wiring 26 is connected to the drain region. The PMOSFET is shown in FIG.
As shown in (c), a P + source region 28 (NMOS FE) formed in the N-well or N-type substrate 12 respectively.
In T, the N + source region 28) and the P + drain region 30
(N + drain region 30 in the NMOSFET). The gate electrode 18, the source region 28, and the drain region 30 are electrically connected to the wiring 22, the wiring 24, and the wiring 26 via contact plugs 32, 34, and 36 which fill contact holes penetrating the interlayer insulating film 20, respectively.

[0006]

By the way, with the miniaturization and high integration of semiconductor devices, protection diodes are inevitably required to be miniaturized. However, the above-mentioned conventional protection diode combines two MOSFETs, and mainly utilizes the destruction of the PN junction at the gate end of the MOSFET to dissipate an excessive signal voltage. Need width. For this reason, the active region is widened, and miniaturization of the protection diode has been technically difficult. Therefore, an object of the present invention is to provide a MOS
An object of the present invention is to provide an input protection diode provided on a signal input line for inputting a signal to an FET, the input protection diode being miniaturized.

[0007]

The present inventors have conceived of combining two MOS capacitors in place of a combination of two MOSFETs in order to reduce the active area, and have completed the present invention. It has arrived. In order to achieve the above object, an input protection diode according to the present invention includes an input protection diode connected to a gate electrode of a MOSFET provided in an internal circuit of a semiconductor device and provided on a signal input line for inputting a signal to the MOSFET. In the first and second embodiments, a first and a second electrode are located in an active region surrounded by an isolation insulating film and have a diffusion layer formed in a substrate well and a gate electrode adjacent to the diffusion layer via a gate oxide film. A second MOS capacitor, wherein the gate electrode and the well of the first MOS capacitor are short-circuited to a ground electrode, and the gate electrode and the well of the second MOS capacitor are connected to a power supply voltage (Vcc); Each of the diffusion layers of the MOS capacitor and the second MOS capacitor is connected to a signal input line.

By using a MOS capacitor in which the diffusion layer and the gate electrode are brought close to each other via the gate oxide film, the area of the diffusion layer from which charges can be released can be increased, and the activation of the gate electrode can be increased. The length of the gate end on the region can be increased. For example, each can be about twice as large as a conventional input protection diode. As a result, even when a signal voltage containing high-voltage noise is applied, the charge accumulated due to the destruction of the PN junction at the gate end can be efficiently dissipated. Therefore, dielectric breakdown of the gate electrode of the MOSFET in the internal circuit can be reliably suppressed. Conversely, due to the active region having an area about half that of the conventional input protection diode,
It can have the same charge dissipation capability as a conventional input protection diode.

Further, the first MOS capacitor is replaced with an NMOS.
The second MOS capacitor is connected to the PMOSFE by the FET.
T, the gate electrode of the NMOS transistor and the P-well are short-circuited to the ground electrode, and the PMO
The gate electrode of the S transistor and the N-well are connected to the power supply voltage (Vcc), and the source and drain of the NMOS transistor and the source and drain of the PMOS transistor are respectively connected to the signal input line to form an input protection diode. Is also good. In this embodiment, the MOSFE
By connecting the source and drain of T, MOS
The FET is operated as a MOS capacitor.

[0010]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings by way of examples. Embodiment 1 This embodiment is one of embodiments of the input protection diode according to the present invention. FIG. 1 is a circuit diagram of this embodiment, and FIG.
PM represents a main part of the input protection diode of this embodiment.
The layout of the wiring and contact holes of the OSFET (or NMOSFET) and FIG.
It is sectional drawing of the layer structure in I. As shown in FIG. 1, the input protection diode 10 of the present embodiment includes an NMOSFET and a PMOSFET.
MOSFET as a circuit element and MOSFE of internal circuit
An input protection diode provided on a signal input line connected to T, wherein a gate electrode of an NMOSFET and a P-well are short-circuited to a ground electrode, and a gate electrode of the PMOSFET and an N-well are connected to a power supply voltage (Vcc). Connected to
NMOSFET source and drain and PMOSF
The source and the drain of the ET are connected to the signal input lines, respectively. The input protection diode further includes a parasitic capacitance C
1 and C2 constitute a time constant circuit.
Is connected to the gate electrode of the MOSFET in the internal circuit.

A PMOSFET 11 and an NMOSFET 11 which constitute a main part of the input protection diode 10 are shown in FIG.
As shown in FIG. 1A, a wiring structure is provided in which wirings respectively connected to a source and a drain are mutually connected.
The PMOSFET (or NMOSFET) is shown in FIG.
And (b), an N-well substrate (NMOSF)
ET has a device isolation region 14 made of a LOCOS film on a P-well 12, and the gate oxide film 1 is sequentially formed on the N-well substrate 12 in the region separated by the device isolation region 14.
6, gate electrode 18, interlayer insulating film 20, gate electrode 18
, A wiring 24 conducting to the source region, and a wiring 26 conducting to the drain region. Also, the PMOSFET is composed of a conventional input protection diode and P
Similarly to the MOSFET, as shown in FIG.
P + source region 28 (N + source region 28 in the case of NMOSFET) and P
+ Drain region 30 (N + drain region 30 in the NMOSFET). Gate electrode 18, source region 28
And the drain region 30 is formed of a contact plug 3 buried in a contact hole penetrating the interlayer insulating film 20.
It is electrically connected to the wirings 22, 24, and 26 via 2, 34, and 36.

In this embodiment, the NMOSFET and the PMO
By connecting the source and the drain of the SFET to the signal input line, the source region and the drain region of each MOSFET become equivalent to each other, and the area of the diffusion layer capable of releasing charges and the length of the gate end are respectively reduced to the conventional values. It is increased to about twice the input protection diode. As a result, even when a signal voltage including high voltage noise is applied, the accumulated charges can be efficiently dissipated, so that the input gate of the MOSFET in the internal circuit can be prevented from being destroyed. Conversely, the active region having about half the area of the conventional input protection diode can have the same charge dissipation capability as the conventional input protection diode.

In this embodiment, a PMOSFET and an NMOS
Since the source and the drain are connected to each other in combination with the FET, the MOSFET functions as a MOS capacitor. Therefore, in this embodiment,
A MOS capacitor may be used instead of the MOSFET.

Embodiment 2 This embodiment is a modification of Embodiment 1, and FIG. 3A shows a MOS which constitutes a main part of the input protection diode of this embodiment.
FIG. 3B is a cross-sectional view of the layer structure taken along line II-II in FIG. 3A. In the input protection diode of this embodiment, MOSFE
Instead of T, a MOS capacitor 40 is used.
The MOS capacitor 40 includes a gate electrode 42 and a LOCO
A diffusion layer 44 located in the active region surrounded by the S film and formed in the well. The gate electrode 42 is formed so as to be located on the active region over the entire periphery thereof,
A diffusion layer 44 is formed around the gate electrode 42. The diffusion layer 44 is connected to a wiring 48 via a contact plug 46. In this embodiment, since the gate electrode 42 does not cross the LOCOS film 14, the reliability of the gate electrode 18 can be improved.

Third Embodiment This embodiment is a modification of the second embodiment. FIG. 4A shows a MOS which constitutes a main part of the input protection diode of the third embodiment.
FIG. 4B is a cross-sectional view of the layer structure taken along line III-III in FIG. 4A. In the input protection diode of this embodiment, the MOS
The capacitor 50 includes a LOCOS film 52 below the contact formation region of the gate electrode 42 in addition to the configuration of the second embodiment. Thus, even if a high selectivity cannot be obtained between SiO ₂ forming the interlayer insulating film 20 and Si forming the gate electrode 42 by etching for opening a contact hole on the gate electrode 42, A hole penetrates through the gate electrode 42 to form the gate oxide film 1.
6 is not damaged.

Embodiment 4 This embodiment is a modification of Embodiment 2, and FIG. 5A shows a MOS constituting a main part of the input protection diode of this embodiment.
FIG. 5B is a cross-sectional view of the layer structure taken along line III-III in FIG. 5A. In the input protection diode of this embodiment, the MOS
In the capacitor 60, in addition to the configuration of the second embodiment, the gate electrode 62 is formed in a planar shape having a radius at the corner 64. The rounded corners 64 of the gate electrode 62 are rounded, so that the corners 6 of the gate electrode 62 are formed.
4 prevents the electric field from concentrating and causing damage,
The reliability of the gate electrode 62 can be improved.
It should be noted that the gate electrode 42 of the third embodiment can be configured as the gate electrode 62 of the present embodiment.

[0017]

According to the structure of the present invention, the first MOS capacitor having the gate electrode and the well shorted to the ground electrode, and the second MOS capacitor having the gate electrode and the well connected to the power supply voltage (Vcc). An input protection diode provided for a MOSFET in an internal circuit of the semiconductor device by connecting each diffusion layer of the first and second MOS capacitors to a signal input line to form an input protection diode. Can be miniaturized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an input protection diode according to a first embodiment.

FIG. 2A is a diagram showing a PMOSFET (or an NMOSFET) constituting a main part of the input protection diode according to the first embodiment;
Of wiring and contact holes in FIG. 2, and FIG.
FIG. 3 is a sectional view of the layer structure taken along line II in FIG.

FIG. 3 (a) is a layout diagram of wiring and contact holes of a MOS capacitor constituting a main part of an input protection diode according to a second embodiment, and FIG. 3 (b) is a line II-II of FIG. 3 (a).
FIG. 3 is a cross-sectional view of the layer structure in FIG.

FIG. 4A is a layout diagram of wiring and contact holes of a MOS capacitor constituting a main part of an input protection diode according to a third embodiment, and FIG. 4B is a line III- of FIG. 4A;
It is sectional drawing of a layer structure in III.

FIG. 5A is a layout diagram of wiring and contact holes of a MOS capacitor constituting a main part of an input protection diode according to a fourth embodiment, and FIG. 5B is a line IV-IV of FIG. 5A.
FIG. 3 is a cross-sectional view of the layer structure in FIG.

FIG. 6 is a circuit diagram of a conventional input protection diode.

FIG. 7A is a plan view of a MOSFET, and FIG.
7B is a cross-sectional view showing the layer structure taken along line II in FIG. 7A, and FIG. 7C is a cross-sectional view showing the layer structure taken along line II-II in FIG. .

[Explanation of symbols]

10: Input protection diode according to the present invention, 11: P
MOSFET or NMOSFET, 12 N-well substrate (P-well in NMOSFET), 14 device isolation region, 16 gate oxide film, gate electrode, 2
0 ... interlayer insulating film, 22 ... wiring connected to the gate electrode, 24 ... wiring connected to the source region, 26 ... wiring connected to the drain region, 28 ... P + source region (N
... P + drain region (N + drain region for NMOSFET), 3
2, 34, 36 ... contact plug, 40 ... MOS
Capacitor, 42 gate electrode, 44 diffusion layer, 4
6 Contact plug, 48 Wiring, 50 MO
S capacitor, 52 LOCOS film, 60 MOS
Capacitor, 62... Gate electrode, 64...

Claims (6)

[Claims] 1. An MO provided in an internal circuit of a semiconductor device.
An input protection diode connected to a gate electrode of an SFET and provided on a signal input line for inputting a signal to a MOSFET is located in an active region surrounded by an isolation insulating film and formed in a substrate well. A first MOS capacitor having a diffusion layer and a gate electrode adjacent to the diffusion layer via a gate oxide film, wherein the gate electrode and the well of the first MOS capacitor are short-circuited to a ground electrode; The gate electrode and the well of the second MOS capacitor are connected to a power supply voltage (Vcc), and the respective diffusion layers of the first MOS capacitor and the second MOS capacitor are connected to a signal input line. And input protection diode. 2. The input protection diode according to claim 1, wherein the gate electrode is formed so as to be located on the active region all around the gate electrode. 3. The input protection diode according to claim 1, wherein the gate electrode is formed such that one end thereof is located on the element isolation insulating film. 4. The gate electrode according to claim 1, wherein the gate electrode has an insulating film having the same thickness as the element isolating insulating film below an electrode region in contact with the wiring. Input protection diode according to the item. 5. The input protection diode according to claim 1, wherein the gate electrode is formed to have a planar shape having a radius at a corner. 6. The first MOS capacitor is an NMOSFE.
By T, the second MOS capacitors are respectively constituted by PMOSFETs, the gate electrode of the NMOS transistor and the P-well are short-circuited to the ground electrode, and the gate electrode of the PMOS transistor and the N-well are connected to the power supply voltage (Vcc). Connected, the source and drain of the NMOS transistor and PM
The input protection diode according to any one of claims 1 to 5, wherein a source and a drain of the OS transistor are connected to a signal input line, respectively.