JPH10288648A - Logic circuit test method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for testing a logic circuit with a count value having an optimum detection rate according to a waveform mode. SOLUTION: A device has a pattern generation part 12 for generating a logic pattern for testing and supplying it to a device 11 to be tested, an event pulse generation part 15 for generating an event pulse from the output pulse from the device 11 to be tested when the above logic pattern is given, a counter 16 for counting the number of event pulses being generated, and a comparison part 17 for comparing the count value with the expectation value of an expected value resistor 18. The event pulse generation part 15 selectively generates only event pulses in a specific waveform mode that is set by a setting register 14 out of a plurality of waveform modes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit test method and apparatus for judging pass / fail of a logic circuit under test from an output pattern obtained by supplying a logic pattern for testing to the logic circuit under test.

[0002]

2. Description of the Related Art As a method for testing a logic circuit of a logic LSI or the like, a method is used in which a logic pattern held in a data ROM or the like is given to a logic circuit to be tested and its output pattern is checked to judge pass / fail. For example, see JP-A-62-277569. Specifically, for example, a method is used in which an event pulse obtained according to a logical transition of an output pattern from a test circuit is input to a counter, and the count value is compared with an expected value.

[0003]

However, the conventional method of counting all event pulses from the logic circuit under test cannot optimize the detection rate according to the waveform mode. That is, for example, even if only the logical transition (waveform mode) “01” needs to be counted as an event from the test contents, all the logical transitions “01” and “10” are counted as events. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a logic circuit test method and apparatus capable of testing with a count value having an optimum detection rate according to a waveform mode. And

[0005]

According to the present invention, there is provided a logic circuit test apparatus comprising: a pattern generating means for generating and supplying a test logic pattern to a logic circuit under test; An event pulse generating means for selectively generating an event pulse in one of a plurality of waveform modes from an output pattern from the logic circuit under test; and a plurality of waveform modes for the event pulse generating means. Mode setting means for issuing an instruction to select one of the following, counting means for counting event pulses obtained from the event pulse generating means, and comparing means for comparing the count value of the counting means with an expected value. Features.

A logic circuit test method according to the present invention includes a pattern generation step of generating and supplying a test logic pattern to a logic circuit under test, and the logic circuit under test when the logic pattern is given. An event pulse generating step of selectively generating an event pulse in any one of a plurality of waveform modes from the output pattern from the plurality of waveform modes; and an instruction to select one of the plurality of waveform modes in the event pulse generating step. A step of setting a mode to output, a counting step of counting event pulses obtained in the event pulse generating step, and a comparing step of comparing a count value of the counting step with an expected value.

According to the present invention, the event pulse generating means generates only an event pulse in one of a plurality of waveform modes designated by the mode setting means, so that the event pulse generating means can generate the event pulse in accordance with the contents of the test. By selecting a waveform mode, a logic circuit test can be performed with a count value having an optimum detection rate.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a test circuit according to an embodiment of the present invention. Device under test 1
Reference numeral 1 denotes a logic LSI, for example.
1 that is controlled by the timing generator 13 to provide a predetermined input pattern for testing.
2 and an event pulse generator 15 that generates an event pulse from an output pattern obtained when the input pattern is given to the device under test 11. The event pulse generator 15 selects one waveform mode from a plurality of waveform modes and generates the event pulse. The specification of the waveform mode is performed by the mode setting register 14. In the figure, a circuit that performs an event count by focusing on one of a plurality of output terminals of the device under test 11 is shown. However, for the other outputs, a similar event count system may be used, or a normal test system may be used. Good.

The event pulse obtained from the event pulse generating means 15 is counted by a counter 16.
On the other hand, the expected value register 18 is loaded with the expected value pattern from the pattern generating unit 12 at a predetermined timing, and the count value of the counter 16 and the expected value held in the expected value register 18 are controlled by the timing generating unit 13. The comparison is performed by the comparison unit 17 at a predetermined timing. The result of the comparison is sent to the controller 19, where the pass / fail judgment and analysis are performed. The controller 19 sends necessary control signals to each circuit unit in addition to the judgment and analysis. In order to generate an event pulse by selecting a waveform mode, the expected value pattern differs according to the waveform mode. Therefore, the pattern generating unit 12 can generate the expected value pattern according to the waveform mode. Accordingly, the controller 19 issues an instruction to select the waveform mode to the setting register 14 and, at the same time, issues an instruction to select the expected value pattern corresponding to the pattern generator 12.

FIG. 2 shows a specific example of the configuration of the event pulse generator 15 in a case where four waveform modes 1 to 4 are selected. Mode 1 is a logical transition of “01”, mode 2 is a logical transition of “10”, and mode 3 is “0”.
Logical transition of “1” and “10”, mode 4 is “0110”
And "1001". Accordingly, the mode setting register 14 is a 2-bit register, and the event pulse of each mode is selected by the selector 29 controlled by the setting register 14.

The event pulse of mode 1 is obtained by detecting the logical transition "01" of the output pattern, that is, the rising edge of the waveform. Accordingly, to constitute a rising edge detection circuit, a delay circuit 21 (delay time τ) such as an inverter chain for inverting and delaying the output pattern, and an AND gate 22 for inputting the delay output A and the output pattern
Are provided. In the event pulse of mode 2, the falling edge may be detected in the opposite manner to the above, and the output pattern and the delayed output A are both inverted and input to the AND gate 23.
It consists of. The mode 3 event pulse is AN
It is formed by an OR gate 24 which receives the output B of the D gate 22 and the output C of the AND gate 23 as inputs.

To obtain a mode 4 event pulse,
Two four-stage shift registers 25a and 25b are used. The output of each stage of one shift register 25a is input to the AND gate 27a via the inverters 26a1 and 26a2 at the outputs of the second and third stages. Thus, A
At the output E of the ND gate 27a, a pulse that has detected a logical transition of "1001" is obtained. The output of each stage of the other shift register 25b is input to the AND gate 27b via the inverters 26b1 and 26b2 in the output of the first stage and the last stage. As a result, a pulse that has detected a logical transition “0110” is obtained at the output F of the AND gate 27b. The outputs E of these AND gates 27a and 27b,
When F is input to the OR gate 28, its output G is "1".
Event pulses corresponding to logical transitions of “001” and “0110” can be obtained.
a and 25b may be combined into one.

FIG. 3 shows each waveform mode 1 by the event pulse generator of FIG. 2 corresponding to a specific output pattern.
4 shows a state in which event pulses of 4 are obtained. One of the event pulses in the waveform modes 1 to 4 is selected by the selector 29 and sent to the counter 16,
As described above, the count value is compared with the expected value.

As described above, according to this embodiment, an event pulse is generated by selecting one of a plurality of waveform modes, so that the state of a logic circuit can be tested in a specific waveform mode. As compared with the case where all the event pulses are generated as described above, useless counting of event pulses is not required, so that a test can be performed with a counter value having an optimum detection rate.

The present invention is not limited to the above embodiment.
For example, the test apparatus of the present invention is effective not only when it is configured as an external device of the LSI to be tested as shown in FIG. 1 but also when it is configured as an internal test circuit of the LSI. Further, the setting of the waveform mode can be switched even during the counting. Further, the logic circuit test device according to the present invention can be realized by software processing.

[0016]

As described above, in the test apparatus according to the present invention, the event pulse generating means is configured to generate only the event pulse of one of the plurality of waveform modes designated by the mode setting means. With this configuration, it is possible to select a waveform mode according to the content of the test and perform a logic circuit test with a count value having an optimum detection rate.

[Brief description of the drawings]

FIG. 1 shows a configuration of a logic circuit test apparatus according to an embodiment of the present invention.

FIG. 2 shows a specific configuration example of an event pulse generator of the embodiment.

FIG. 3 shows how an event pulse is generated in the embodiment.

[Explanation of symbols]

11: Device under test, 12: Pattern generator, 13
... Timing generator, 14 ... Mode setting register, 15
... Event pulse generator, 16 counter, 17 comparator, 18 expected value register, 19 controller, 29
…selector.

Claims (3)

[Claims] 1. A pattern generating means for generating and supplying a test logic pattern to a logic circuit under test, and a plurality of waveforms from an output pattern from the logic circuit under test when the logic pattern is given. An event pulse generating means for selectively generating an event pulse in any one of the waveform modes, a mode setting means for instructing the event pulse generating means to select one of the plurality of waveform modes; A logic circuit test apparatus comprising: a counting means for counting an event pulse obtained from the event pulse generating means; and a comparing means for comparing a count value of the counting means with an expected value. 2. A pattern generating step of generating and supplying a test logic pattern to a logic circuit under test, and a plurality of waveforms from an output pattern from the logic circuit under test when the logic pattern is given. An event pulse generating step of selectively generating an event pulse of any one of the waveform modes; a mode setting step of issuing an instruction to select one of the plurality of waveform modes in the event pulse generating step; A logic circuit test method, comprising: a counting step of counting event pulses obtained by a pulse generating step; and a comparing step of comparing a count value of the counting step with an expected value. 3. A pattern generating step of generating and supplying a test logic pattern to a logic circuit under test, and a plurality of waveforms from an output pattern from the logic circuit under test when the logic pattern is given. An event pulse generating step of selectively generating an event pulse of any one of the waveform modes; a mode setting step of issuing an instruction to select one of the plurality of waveform modes in the event pulse generating step; A medium storing a logic circuit test operation program for executing a counting step of counting event pulses obtained by a pulse generating step and a comparing step of comparing a count value of the counting step with an expected value.