JPH10285910A - Control device - Google Patents

Abstract

(57) Abstract: In a control device including a pulse control device and a pulse generation device, the number of signal lines required for transmitting pulse signals and information between the pulse control device and the pulse generation device is reduced. In addition, the present invention provides a control device that does not degrade the accuracy of the pulse signal even when the number of pulse signals increases, and that can use a general data transfer method. SOLUTION: A pulse control device for controlling a pulse signal and a pulse generation device for generating a pulse signal according to an instruction of the pulse control device are connected by a data transmission line, and the pulse control device has a reference time serving as a reference for pulse signal generation. Notify the pulse generation device at regular intervals, further determine the time from the reference time to the time when the pulse signal changes and notify the pulse generation device, the pulse generation device notifies the pulse generation device of the reference time and The pulse signal is generated based on the time from the reference time to the time when the pulse signal changes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for controlling a circuit device such as a power conversion circuit by a pulse signal, and more particularly to a pulse control device for controlling generation of a pulse signal and a pulse signal in accordance with an instruction from the pulse control device. The present invention relates to a control device configured to be separated from a pulse generation device that generates a pulse signal.

[0002]

2. Description of the Related Art A power conversion device for converting and controlling power is composed of a power conversion circuit composed of a number of switching elements and a control device for controlling the power conversion circuit. It has a function of turning on / off a switching element of a power conversion circuit by a signal to convert DC power to AC power or AC power to DC power, and to shape a power waveform. Further, it has a function of controlling electric power supplied to a load such as an electric motor to control the load.

[0003] Such power converters are applied to socially important systems such as power systems, industrial systems such as plants and product assembly lines, and public systems such as railways and water and sewage systems. In these systems, in order to operate the equipment, a control device is often installed at a place away from the power conversion circuit. For this reason, the control device uses a pulse generator that generates a switching signal and a pulse control that controls the generation of the switching signal. The pulse generation device is installed near the power conversion circuit separately from the device, the pulse control device supplies the control pulse signal, which is the basis of the switching signal generation, to the pulse generation device, and the pulse generation device changes the control pulse signal. A method of generating a switching signal for each switching element in accordance with timing is generally used.

On the other hand, a system in which the above-described control device is operated is often placed in a harsh environment in which noise is easily generated, and thus the control device may generate an error due to external noise or the like. Furthermore, errors may occur due to the intrusion of radiation such as alpha rays or the deterioration of components. If an error occurs in the control device due to these factors, the output of the power conversion circuit becomes abnormal and has a serious social impact. Therefore, the above control device is required to be able to continue control normally even if an error occurs,
For this reason, a method of using a multiplexed control device is generally used.

[0005] As a method of multiplexing the control devices, there is known a method in which three pulse control devices and three pulse generation devices are provided for each of the control devices so as to be tripled. According to this method, each pulse controller supplies a control pulse signal to all of the three pulse generators, and each of the three pulse generators receives the control pulse signal supplied from the third pulse controller. A gate pulse signal is output based on the majority decision result. Further, for example, Japanese Patent Laid-Open No. 6-233599
As disclosed in Japanese Unexamined Patent Application Publication No. H11-264, there is known a method in which a gate pulse signal output from a pulse generator of three systems is selected and output by a majority circuit.

In the control device disclosed in this publication, a signal line for supplying a control pulse signal from the pulse control device to the pulse generation device is required. However, a general power conversion device has three or more phases. It is necessary to control the phase AC power, and since power conversion is performed using a plurality of power conversion circuits, the number between the pulse control device and the pulse generation device is equal to the number of phases, or an integral multiple of the number of phases. Need to be provided. Further, it is necessary to provide a signal line for communication of an operation state report, an abnormality occurrence notification, a control command, and the like between the pulse control device and the pulse generation device. For this reason, the number of wires between the pulse control device and the pulse generation device increases, and when the control devices are multiplexed, the number of wires becomes enormous, thereby increasing the cost of the control device. There was a problem that.

In order to solve such a problem, for the purpose of reducing the number of wirings, a switching signal is encoded by a pulse control device and is decoded by a pulse generation device installed near a power conversion circuit. Japanese Patent Laid-Open No. Hei 8-
98506.

In the encoding system specifically disclosed in Japanese Patent Application Laid-Open No. 8-98506, the on / off state of a switching signal on a signal line at a certain point in time is encoded into a plurality of bits of digital data. Is transmitted as parallel data. However, if the data is transmitted as parallel data, the number of signal lines cannot be reduced sufficiently. Therefore, a measure is taken to convert the switching code into one serial signal by a parallel-serial converter and transmit the converted signal, and to re-convert the switching code into a parallel switching code by a serial-parallel converter.

[0009]

In such a time-division serial communication system, the accuracy of the on / off timing of the switching signal is determined by the number of bits of the switching code. The number of bits of the switching code depends on the number of switching signals, that is, the number of switching elements of the entire power conversion circuit. Therefore, when the number of switching signals is increased, there is a problem that the accuracy of the switching signals is reduced.

In this serial communication system, the on / off timing of the switching signal is determined by the arrival timing of the switching code sent from the serial transmission line to the decoding means. When the switching code is transmitted, there is a possibility that an error occurs in the ON / OFF timing of the switching signal, and therefore, there is also a problem that the transmission of the switching code needs to be continued.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional control device, and has a signal line necessary for transmitting pulse signals and information between a pulse control device and a pulse generation device. The number of pulses can be reduced, and even if the number of pulse signals increases, the accuracy of the pulse signals does not decrease, and the pulse data transferred on the data transmission path can be made in time for the start time of the pulse generation cycle corresponding to the pulse data. An object of the present invention is to provide a control device in which a pulse signal error does not occur even when a general data transfer method such as packet transfer is used.

[0012]

In order to achieve the above object, a control device according to the present invention comprises a pulse control device for controlling generation of a pulse signal, and a pulse generation device for generating a pulse signal in accordance with an instruction from the pulse control device. In the control device having a device, the pulse control device is a reference timer that notifies the pulse generation device of a reference time serving as a reference for pulse signal generation at regular intervals, and a time from the reference time to a time when the pulse signal changes. An arithmetic circuit that determines a pulse change time to be indicated and notifies the pulse generator of the change. The pulse generator includes a synchronization timer that operates in synchronization with a reference time notified from the pulse controller, and a notification of the pulse from the pulse controller. Pulse generation circuit that temporarily holds the pulse change time and changes the pulse signal when the time indicated by the synchronization timer matches the pulse change time It is those with a. Thus, the change timing of all the pulse signals is determined by the pulse data indicating the reference time and the pulse data indicating the pulse change time, so that the number of signal paths is sufficiently small, and the accuracy of the pulse signal is the pulse signal. Irrespective of the number of signals, even if the number of pulse signals increases, the accuracy does not decrease even if the number of pulse signals increases. Furthermore, pulse data only needs to be transferred within a range in time for the start time of the corresponding pulse generation cycle. Even if a typical data transfer method is used, the accuracy of the pulse signal does not deteriorate.

In the control device according to the present invention, the pulse control device and the pulse generation device are connected by at least one data transmission path for transmitting a digital code, and the pulse control device sets the same reference time and pulse change time. This is to notify the pulse generation device via the data transmission path. This makes it possible to transfer pulse data from the pulse control device to the pulse generation device using a very small number of data transmission paths.

In the control device of the present invention, the arithmetic circuit of the pulse control device determines each pulse change time of the plurality of pulse signals, and determines each pulse change time of the plurality of pulse signals on the same data transmission line. Is notified to the pulse generation device via the. Thereby, the pulse change time of the plurality of pulse signals can be determined by one set of pulse data.

[0015] The control device of the present invention is also configured such that when the pulse control device does not notify the pulse generation device of the reference time or the pulse change time, the pulse control device issues an operation command to the pulse generation device via the data transmission path. The pulse generation device notifies the pulse control device of the operation state and the abnormality detection via the data transmission path. Thereby, the normal operation of the pulse generation device can be managed without using an extra signal path other than the data transmission path.

According to the control device of the present invention, the pulse generation device corrects the pulse change time according to a predetermined rule to adjust the pulse width of the pulse signal, and then supplies the pulse adjustment circuit to the pulse generation circuit. It is further provided.
Accordingly, even when the branch of the power conversion circuit is configured by a plurality of switching elements, an accident such as destruction of the switching elements does not occur.

The control device of the present invention also includes a control device having a multiplexed pulse control device for controlling generation of a pulse signal and a multiplexed pulse generation device for generating a pulse signal in accordance with an instruction from the pulse control device. In the device, the multiplexed pulse control devices perform the same operation in synchronization with each other, and each of the multiplexed pulse control devices sets a reference time, which is a reference of the pulse signal generation, to all of the multiplexed pulse generation devices at regular intervals. And a calculation circuit that determines the pulse change time indicating the time from the reference time to the time when the pulse signal changes, and notifies all of the multiplexed pulse generators, The pulse generation device includes a synchronization timer, each of which operates in synchronization with an intermediate time of the reference time notified from all of the multiplexed pulse control devices, and a multiplexing timer. A selection circuit that compares and compares the pulse change times notified from all of the pulse control devices selected to select a normal pulse change time, and temporarily holds the pulse change time selected by the selection circuit. A pulse generation circuit that changes the pulse signal when the indicated time coincides with the pulse change time. As a result, even in a multiplexed control device, only a small number of signal paths are required, and even if the number of pulse signals is large, the accuracy does not decrease. No degradation in accuracy occurs. Further, even if a failure occurs in a part of the multiplexed pulse control device and the pulse generation device, the normal operation of the control device can be continued by using the output signal of the normal one. .

The control device of the present invention also connects each of the multiplexed pulse control devices and each of the multiplexed pulse generation devices by at least one data transmission line for transmitting a digital code, and performs multiplexing. Each of the pulse control devices described above notifies the reference time and the pulse change time to all of the multiplexed pulse generation devices via the same data transmission path. Thereby, even in the multiplexed control device, the pulse data can be transferred from the pulse control device to the pulse generation device using an extremely small number of data transmission paths.

In the control device of the present invention, the arithmetic circuits of the multiplexed pulse control device each determine a pulse change time of each of the plurality of pulse signals, The change time is notified to all of the multiplexed pulse generators via the same data transmission path. Thus, even in a multiplexed control device, the pulse change time of a plurality of pulse signals can be determined by one set of pulse data.

The control device of the present invention also provides that the multiplexed pulse control device operates when the multiplexed pulse control device does not notify the multiplexed pulse generation device of a reference time or pulse change time. Notifying the command to the multiplexed pulse generation device via the data transmission line, the multiplexed pulse generation device notifies the multiplexed pulse control device via the data transmission line of the operation state information, , The selection circuits of the multiplexed pulse generators each
When a mismatch is detected by comparing and comparing the pulse change times, the multiplexed pulse control device is notified of the mismatch detection of the pulse change times via the digital data transmission line. As a result, even in a multiplexed control device,
The normal operation of the pulse generator can be managed without using an extra signal path other than the data transmission path.

According to the control device of the present invention, the multiplexed pulse generation device corrects the pulse change time notified from the multiplexed pulse control device according to a predetermined rule, and modifies the pulse width of the pulse signal. After adjusting the pulse width, the pulse adjusting circuit supplies the pulse adjusting circuit with the pulse adjusting circuit. Accordingly, even in the multiplexed control device, even when the branch of the power conversion circuit is configured by a plurality of switching elements, an accident such as destruction of the switching elements does not occur.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a control device according to the present invention will be described below with reference to the drawings. FIG.
It is a block diagram showing composition of a 1st embodiment which applied a control device of the present invention to a power converter.

In the present power converter, a sensor 11 for detecting a voltage / current value of the DC power supply 10 is provided near the DC power supply 10 for supplying DC power. The DC power of the DC power supply 10 is applied to both the positive and negative electrodes of the DC power supply 10.
The positive-side and negative-side input terminals of the three-phase power converter 20 for converting into three-phase AC power are connected to each other. In the three-phase power converter 20, three branches on the positive side and three branches on the negative side are connected in parallel to the input terminals on the positive side and the negative side, respectively, and each branch on the positive side and the negative side are connected in series. I have. The positive and negative branches are respectively connected to the switching elements 20a to 20f.
have. A connection point, which is an output terminal of the three-phase power converter 20, where each of the positive side branch and the negative side branch is connected in series, is connected to the primary side of the transformer 30. A sensor 21 for detecting a voltage / current value of the three-phase power converter 20 is provided between the output terminal of the three-phase power converter 20 and the primary side of the transformer 30.
Is provided. A three-phase three-wire power system 40 is connected to the secondary side of the transformer 30. A sensor 41 for detecting a voltage / current value of the power system 40 is provided between the secondary side of the transformer 30 and the power system 40. Sensor 1
Output terminals 1, 21, 41 are connected to input terminals of a pulse control device 50 that outputs a pulse signal for controlling on / off of the switching elements 20a to 20f of the three-phase power converter 20. The output terminal of the pulse control device 50
The other end of the data transmission line 70 is connected to one end of a data transmission line 70 for transferring data.
Are connected to the input terminals of a pulse generation device 60 that generates gate pulses 22a to 22f as on / off signals of the switching elements 20a to 20f. Pulse generator 6
0 is connected to the gate terminals of the switching elements 20a to 20f.
a to 22f are supplied. A terminal 80 for giving a command to the pulse control device 50 is also connected to the pulse control device 50.

Next, the operation of the power converter will be described. The voltage / current value of the DC power supply 10, the voltage / current value of the three-phase power converter 20, and the voltage / current value of the power system 40 are detected by the sensors 11, 21, 41, respectively, and input to the pulse control device 50. . The pulse control device 50 controls the three-phase power converter 2 based on the voltage / current value input from each sensor and the command given from the terminal 80 at every fixed control cycle.
Control pulse data indicating ON / OFF timing of the switching elements 20a to 20f of 0 is generated and transmitted to the pulse generation device 60 via the data transmission path 70. The pulse generator 60 generates gate pulses 22a to 22f based on the control pulse data received from the pulse controller 50, and outputs the gate pulses 22a to 22f to each switching element. The three-phase power converter 20 switches the switching elements 20 a to 2 by gate pulses 22 a to 22 f input from the pulse generator 60.
By turning on or off 0f, the DC power of the DC power supply 10 is converted to AC power. The AC power output from the three-phase power converter 20 is transformed by the transformer 30 and
Is output to In addition, when the pulse control device 50 does not notify the pulse generation device 60 of the control pulse data, the pulse control device 50 issues an operation command for instructing the operation of the three-phase power converter 20 via the data transmission line 70 to the pulse generation device 60. Send. Further, when the control pulse data is not transferred on the data transmission line 70, the pulse generation device 60 notifies the pulse control device 50 of the operation state and the abnormality detection of the three-phase power converter 20 via the data transmission line 70. Notice.

Next, the configuration and operation of each component of the power converter will be described in more detail. The three-phase power converter 20
U-phase positive-side switching element 20a, U-phase negative-side switching element 20b, V-phase positive-side switching element 20c, and V-phase negative-side switching element 20d
, And a W-phase positive-side switching element 20e and a W-phase negative-side switching element 20f, and gate pulse signals 22a to 22f are given to each of the switching elements from the pulse generation device 60. In the present power converter, each branch of the positive electrode side and the negative electrode side of each phase is configured by one switching element.
In order to increase the pressure resistance of the three-phase power converter 20, a plurality of switching elements may be connected in series. Each switching element is turned on when the gate pulse signal goes high, and turned off when the gate pulse signal goes low.

The pulse control device 50 includes sensors 11 and
DC power supply 10, three-phase power converter 2 obtained from 1, 41
A / A which samples each voltage / current value of the power system 40 in each control cycle and converts the analog value into a digital value.
A D conversion circuit 51, an arithmetic circuit 52 that processes the digital value converted by the A / D conversion circuit 51 and a command given from the terminal 80 to generate control pulse data, a timer 53 that generates a control cycle, The control pulse data, the command signal,
And a transmission circuit 54 for transmitting and receiving a synchronization symbol indicating the start of the control cycle. The components of the pulse control device 50 are connected to each other by a system bus.

In the pulse control device 50, the timer 53
Outputs a control cycle start signal 531 on the system bus at regular intervals.

When the A / D conversion circuit 51 receives the control cycle start signal 531 output from the timer 53, the A / D conversion circuit 51 samples the voltage and current values from the sensors 11, 21, 41, converts them into digital values, and then converts them into digital values. To supply.

The arithmetic circuit 52 supplies the past and present voltage and current values of the DC power supply 10, the three-phase power converter 20, and the power system 40 supplied from the A / D conversion circuit 51 for each control cycle and the terminal 80. The control pulse data is generated by determining the on / off timing of the switching elements 20a to 20f of the three-phase power converter 20 after a predetermined time based on the received command and the control pulse data via the system bus 521. The signal is transmitted to the transmission circuit 54. The arithmetic circuit 52
If the command given from the terminal 80 is for the pulse generator 60, the command is transferred to the transmission circuit 54 via the system bus 521. Further, the arithmetic circuit 52
When response data from the pulse generation device 60 is transferred from the transmission circuit 54 via the system bus 521, the transferred response data is transmitted to the terminal 80.

The transmission circuit 54 has a control cycle start signal 531
Is received, a synchronization symbol indicating the start of the control cycle is transmitted to the pulse generation device 60 via the data transmission path 70. Further, the transmission circuit 54 transmits the control pulse data transferred from the arithmetic circuit 52 and a command to the pulse generation device 60 to the pulse generation device 60 via the data transmission line 70. Further, when receiving the response data from the pulse generation device 60 via the data transmission path 70, the transmission circuit 54 transfers the received response data to the arithmetic circuit 52.

The pulse generation device 60 includes the pulse control device 5
0, a transmission circuit 61 for transmitting and receiving data via a data transmission path 70, a timer 62 operating in synchronization with the control cycle of the pulse control device 50, and a pulse control device 5
0 based on the control pulse data received from control pulse 6
31u, 631v, 631w, and a gate pulse 2 based on control pulses 631u, 631v, 631w input from the pulse generation circuit 63.
And a pulse correction circuit 64 for generating 2a to 22f. When a serial transfer unit such as a communication line is used as the data transmission path 70 as described later, the transmission circuit 61 converts the control pulse data transferred as serial data into parallel data and outputs it. A serial / parallel conversion circuit is provided. The components of the pulse generation device 60 are connected to each other by a system bus.

In the pulse generator 60, the transmission circuit 6
When a synchronization symbol is received from the pulse control device 50 via the data transmission line 70, the timer 62
11 is output. When receiving the control pulse data from the pulse control device 50 via the data transmission line 70, the transmission circuit 61 transfers the received control pulse data to the pulse generation circuit 63 via the system bus 612. At this time, if the control pulse data is serial data, it is converted into parallel data and transferred. The transmission circuit 61
Receives a command from the terminal 80 via the data transmission path 70 from the pulse control device 50, and transfers the received command to the timer 62 or the pulse correction circuit 64 via the system bus 613. Further, when receiving the response data from the timer 62 or the pulse correction circuit 64 via the system bus 613, the transmission circuit 61 transmits the received response data to the pulse control device 50 via the data transmission path 70.

The timer 62 determines that the transmission circuit 61
11 is a timer that restarts from time 0 when the signal 11 is output or when a certain time has elapsed after the transmission circuit 61 outputs the synchronization signal 611.
1 is always output. Here, for the sake of explanation, the timer 62
Is referred to as a pulse generation cycle. Since the generation source of the synchronization signal 611 that is the starting point of the restart of the timer 62 is the control cycle start signal 531 output by the timer 53 of the pulse control device 50, 1
The pulse generation cycle time is equal to one control cycle time, and the phase difference between the pulse generation cycle and the control cycle is always constant.

Based on the control pulse data transferred from the transmission circuit 61 and the time 621 output from the timer 62, the pulse generator 63 switches the switching elements 20a and 20b
And a V-phase control pulse 631v for the switching elements 20c and 20d.
And a W-phase control pulse 631w for the switching elements 20e and 20f.

The pulse correction circuit 64 controls the control pulses 631u and 631 in order to prevent the switching elements from being destroyed by a short-circuit overcurrent generated when the series-connected positive and negative switching elements are simultaneously turned on.
v, 631w, the switching elements 20a and 20b on the positive and negative sides of the power converter 20 and the switching element 20c
And 20d or the gate pulses 22a to 22d so that a dead time period in which the switching elements 20e and 20f are turned off at the same time occurs, and a minimum on-pulse width in which the switching elements are reliably turned on is guaranteed.
Generate f.

The data transmission path 70 is capable of bi-directionally transferring digital data. For example, parallel transfer means such as a system bus or serial transfer means such as a communication line can be applied.

FIG. 2 is a diagram showing the format of the control pulse data of the power converter and a time chart for explaining the relationship between the control pulse data and the actual control pulses. FIG.
FIG. 2A shows a data format of control pulse data, and FIG.
(B) is a time chart for explaining the relationship between control pulse data and actual control pulses.

In FIG. 2A, Tu is change time data indicating the time from the start of the pulse generation cycle to the time when the U-phase control pulse changes, and Cu is 0 if the value is 0, the U-phase control pulse is high. A change flag indicating a change from a low level to a high level, and a value of 1 indicates a change from a low level to a high level. If the value is 1, Tu and Cu are valid if the value is 1, and if the value is 0, For example, it is a valid flag indicating that Tu and Cu are invalid. Similarly, Tv, Cv and Ev are V
Tw, Cw, and Ew are for the W phase control pulse.

In FIG. 2B, in the pulse generation cycle 1, the valid flags Eu, Ev, Ew are all 1 and the change flags Cu, Cv, Cw are all 1, so that the U-phase control pulse, the V-phase control pulse, The W-phase control pulse changes from the low level to the high level after Xu, Xv, and Xw time from the pulse generation cycle start time, respectively. In the pulse generation cycle 2, the validity flags Eu, Ev, and Ew are all 0. , V-phase control pulse, and W-phase control pulse do not change, and the valid flags Eu, E
Since v and Ew are all 1 and the change flags Cu, Cv and Cw are all 0, the U-phase control pulse, the V-phase control pulse,
The W-phase control pulse changes from the high level to the low level after Yu, Yv, and Yw time from the pulse generation cycle start time.

FIG. 3 is a block diagram showing the configuration of the timer 62 of the power converter, and a time chart for explaining the operation. FIG. 3A is a block diagram illustrating the configuration of the timer 62, and FIG. 3B is a time chart illustrating the operation of the timer 62.

In FIG. 3A, a timer 62 includes a counter A 622 which starts counting when a synchronization signal 611 is received, and a counter B 623 which has a reset signal input terminal connected to an output terminal of the counter A 622 and outputs a time 621. And a register 624 for setting the count value of the counter A 622.

In the register 624, the time from the time when the transmission circuit 61 outputs the synchronization signal 611 to the time when the pulse generation cycle starts is set. When the synchronization signal 611 is input, the counter A 622 updates the value in the register 624. Preset and start countdown operation. When the count value becomes 0, that is, when the time set in the register 624 elapses, the reset signal 625 is output to the counter B 623 to stop the counting operation. When the reset signal 625 is input, the counter B 623 resets the count value to 0, starts the count-up operation, and continues counting until the reset signal 625 is input again. When the reset signal 625 is input again, the count value is reset to 0 and the count-up operation is started again. In addition,
The register 624 is connected to the system bus 613, and can be written and read by a command from the terminal 80.

The time chart of FIG. 3B shows that the control cycle start signal 531 output from the timer 53 of the pulse control device 50 and the transmission circuit 54 of the pulse control device 50 use the control cycle start signal 531 as a trigger to transmit data. Transmission line 70
A synchronization symbol transferred to the pulse generation device 60 via the PDC, a synchronization signal 611 output by the transmission circuit 61 of the pulse generation device 60 with the reception of the synchronization symbol as a trigger, and a counter A 622 included in the timer 62 of the pulse generation device 60.
Is activated by the synchronization signal 611 and is output after the time set in the register 624 has elapsed.
5 is represented. Since the control cycle start signal 531 indicates the start of the control cycle, and the reset signal 625 indicates the start of the pulse generation cycle, the phase difference between the control cycle and the pulse generation cycle indicates the transfer time of the synchronization symbol and the register 624. It is the sum of the set times.

FIG. 4 is a block diagram showing the configuration of the pulse generating circuit 63 of the power converter. In FIG. 4, the other end of the system bus 612 whose one end is connected to the output terminal of the transmission circuit 61 is used to temporarily hold the change time data value of each phase of the control pulse data transferred from the transmission circuit 61. Is connected to the input terminal of the register 638. The output terminal of the register 638 has input terminals of registers 632u, 632v, and 632w for holding the change time data value of each phase of the control pulse data for each pulse cycle, and a valid flag for each phase for each pulse generation cycle. The input terminals of the registers 633u, 633v, 633w for holding the values and the input terminals of the registers 634u, 634v, 634w for holding the change flag value of each phase for each pulse generation cycle are independent signals. They are connected by lines (represented by one signal line in the figure). Each register 632u, 632v, 632w, 63
3u, 633v, 633w, 634u, 634v, 63
The control terminal of 4w has a time 621 output by the timer 62.
The detection circuit 639 that detects that the value of
A data set signal 6391 output when detecting that 1 has become 0 is input. The time 621 is input to the detection circuit 639. Registers 632u, 632v,
Each output terminal of 632w is connected to each of the registers 632u and 632w.
v, 632w are connected to one input terminals of comparison circuits 635u, 635v, 635w for comparing each of the change time data values held in v and 632w with the time 621 output by the timer 62, respectively.
Time 621 is input to the other input terminal of v, 635w. Output terminals of the comparison circuits 635u, 635v, 635w are connected to one input terminals of AND gates 636u, 636v, 636w, respectively. The other input terminals of the AND gates 636u, 636v, 636w are connected to the output terminals of the registers 633u, 633v, 633w, respectively. Each AND gate 636
Output terminals of u, 636v, 636w are connected to control terminals of latches 637u, 637v, 637w for holding states of control pulses 631u, 631v, 631w of each phase. Each latch 637u, 637v, 637w
Input terminals of the registers 634u, 634v, 634
w output terminals. Each latch 63
7u, 637v, 637w to control pulses 631u, 6
31v and 631w are output, respectively.

Next, the operation of the pulse generation circuit 63 will be described. The register 638 holds the control pulse data every time the control pulse data is transferred from the transmission circuit 61,
The detection circuit 639 outputs the data set signal 6391 when detecting that the time 621 has become 0, that is, when the pulse generation cycle has started, and
u, 632v, 632w, 633u, 633v, 633
When the data set signal 6391 is output, w, 634u, 634v, and 634w respectively hold the change time data value, the valid flag value, and the change flag value of the control pulse data held in the register 638. Thereby, the registers 632u, 632v, 632w, 633u, 63
3v, 633w, 634u, 634v, and 634w can hold control pulse data transferred at an arbitrary time before one pulse generation cycle at the start of the pulse generation cycle.

At the start of the pulse generation cycle, the pulse generation circuit 63 determines the U phase as follows based on the change time data value, valid flag value, and change flag value of the control pulse data held in each of the registers 632u, 633u, and 634u. A control pulse 631u is generated. That is, register 6
When the change time data value held at 32u matches the time 621 output from the timer 62, the comparison circuit 635u
Becomes high level and the register 63
When the valid flag value of 3u is also 1, the output signal level of the AND gate 636u becomes high level, and the change flag value of the register 634u is set in the latch 637u. As a result, the U-phase control pulse 631u changes at time 6
21 indicates the state specified by the change flag when the pulse change time specified by the control pulse data has been reached (change flag value is 1).
If the change flag value is 0, the transition is made to a high level. The same applies to the V-phase control pulse 631v and the W-phase control pulse 631w.

FIG. 5 is a time chart showing the operation of the pulse control device 50 and the pulse generation device 60 of the power converter.

The pulse control device 50 transmits the synchronization symbol S to the pulse generation device 60 via the data transmission line 70 at the start of the control cycle.
Thus, a pulse generation cycle started after a lapse of a predetermined time from the reception time of the synchronization symbol S is generated.

The pulse control device 50 samples the voltage and current values of the DC power supply and the like by the A / D conversion circuit 51 and performs digital conversion at the start of the control cycle (A), and the control pulse data ( D)
And the pulse generation device 6 via the data transmission path 70
Send to 0. The control pulse data D1 transmitted in the control cycle 1 corresponds to the control pulse in the pulse generation cycle 1, the control pulse data D2 transmitted in the control cycle 2 corresponds to the control pulse in the pulse generation cycle 2, and the control pulse 3 in the control cycle 3 The transmitted control pulse data D3 corresponds to the control pulse in the pulse generation cycle 3. Pulse generator 60
Are used to store the received control pulse data in the registers 632u, 632v, 6
32w, the control pulse data is updated.
u, 631v and 631w are generated.

FIG. 6 is a block diagram showing a configuration of the pulse correction circuit 64 of the power converter. 6, a pulse correction circuit 64 includes a U-phase pulse correction circuit 64u that generates gate pulses 22a and 22b from a U-phase control pulse 631u, and a gate pulse 2 based on a V-phase control pulse 631v.
A V-phase pulse correction circuit 64v for generating 2c and 22d;
Gate pulses 22e, 22 from W-phase control pulse 631w
and a W-phase pulse correction circuit 64w that generates f. Since the U-phase pulse correction circuit 64u, the V-phase pulse correction circuit 64v, and the W-phase pulse correction circuit 64w have the same configuration, only the configuration of the U-phase pulse correction circuit 64u will be described below to simplify the description. I do.

The U-phase pulse correction circuit 64u outputs a trigger signal 641 when the U-phase control pulse 631u changes from a low level to a high level.
1 and is input to a pulse change detection circuit 641 that outputs a trigger signal 6412 when the U-phase control pulse 631u changes from high level to low level. The trigger signal 6411 is connected to the input terminal of the counter 642 and the RS flip-flop 6 that holds the state of the gate pulse 22b.
47 is input to the reset terminal. Trigger signal 6412
Is input to one input terminal of a sequential circuit 645 that outputs a trigger signal 6451 when both the trigger signal 6412 and the trigger signal 6431 output from the counter 643 are input. The system bus 613 is connected to the gate pulse 2
A register 648 for setting a dead time at which 2a and 22b are simultaneously set to a low level state, and a gate pulse 22a
Is in the high level state, that is, the register 649 for setting the minimum on-pulse time. The output terminal of the register 648 is the counters 642 and 6
44 are connected to setting terminals for setting the count value. The output terminal of the register 649 is a counter 643
Is connected to the setting terminal for setting the count value of. The trigger signal 6421 output from the counter 642 is input to the counter 643 and the set terminal of the RS flip-flop 646 that holds the state of the gate pulse 22a. Trigger signal 643 output from counter 643
1 is input to the other input terminal of the sequential circuit 645. The trigger signal 6451 output from the sequential circuit 645 is R
It is input to the reset terminal of the S flip-flop 646 and the counter 644. Trigger signal 6441 output from counter 644 is RS flip-flop 647
Is input to the set terminal. RS flip flop 6
Gate pulses 22a and 22b are output from 46 and the RS flip-flop 647, respectively.

Next, the operation of the pulse correction circuit 64 will be described. When the U-phase control pulse 631u changes from a low level to a high level, the pulse change detection circuit 641 outputs a trigger signal 6411. RS flip flop 64
7 is reset by the trigger signal 6411,
The gate pulse 22b immediately goes to a low level. Also,
The counter 642 is activated by a trigger signal 6411 and outputs a trigger signal 6421 when the dead time set in the register 648 has elapsed. Since the RS flip flop 646 is set by the trigger signal 6421, the gate pulse 22a is
After the dead time elapses after b changes to the low level, it goes to the high level.

When the U-phase control pulse 631u changes from high level to low level, the pulse change detection circuit 641 outputs a trigger signal 6412. Also, a counter 643
When the counter 642 outputs the trigger signal 6421,
That is, it is activated when the gate pulse 22a changes to the high level, and outputs the trigger signal 6431 when the minimum on-pulse time set in the register 649 has elapsed. When both the trigger signal 6412 and the trigger signal 6431 are input, that is, when the time during which the gate pulse 22a is at the high level is equal to or longer than the minimum on-pulse time and the U-phase control pulse 631u is at the low level, A trigger signal 6451 is output. Then, since the RS flip-flop 646 is reset by the trigger signal 6421, the gate pulse 22a becomes low level. The counter 644 is activated by a trigger signal 6451, and outputs a trigger signal 6441 when the dead time set in the register 648 has elapsed. Since the RS flip-flop 647 is set by the trigger signal 6441, the gate pulse 22b is set to the gate pulse 2
After the dead time elapses after 2a has changed to low level, it becomes high level.

Note that, according to a command from the terminal 80 input via the system bus 613, the registers 648, 6
49 can be written and read.

FIG. 7 is a time chart showing the operation of the pulse correction circuit 64. Here, in order to simplify the description, the gate pulses 22a, 22a in the case where only the dead time is considered without correcting the minimum on-pulse time are used.
b is also shown.

The gate pulses 22a and 22b are generated such that when one is at a high level, the other is at a low level. When the gate pulses 22a and 22b change, the dead time Td when both of the gate pulses 22a and 22b become low level so that the switching elements 20a and 20b are not simultaneously turned on by the transmission deviation of both pulses. Generate Further, when the time during which the gate pulse 22a is in the high level state after the generation of the dead time is shorter than the minimum on-pulse time Ts, the time during which the gate pulse 22a is in the high level state is extended to a time equal to the minimum on-pulse time Ts. At this time, the time during which the gate pulse 22b is in the low level state is also extended to guarantee the dead time.

FIG. 8 is a block diagram showing a configuration of a second embodiment in which the control device of the present invention is applied to a power conversion device.

The power converter according to the second embodiment has
Although basically the same as the power conversion device of the first embodiment described with reference to FIG. 1, in the first embodiment, the correction of the dead time and the minimum on-pulse time is performed after the control pulse is generated from the control pulse data. Gate pulses 22a-2
While 2f is output, in the present embodiment, the control pulse data is corrected for the dead time and the minimum on-pulse time, and then the corrected control pulse data is used to output the gate pulses 22a to 22f. As a result, it is possible to reduce the output delay of the gate pulse and the variation in the timing between the gate pulses caused by the correction processing of the dead time and the minimum on-pulse time.

In FIG. 8, the same components as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

Based on the difference from the above-described first embodiment, in this embodiment, the positions and configurations of the pulse generation circuit 65 and the pulse correction circuit 66 of the pulse generation device 60 'are different. The pulse correction circuit 66 is directly connected to the transmission circuit 61 via a system bus 612, and has an output terminal connected to an input terminal of the pulse generation circuit 65 via a system bus 661. Gate pulses 22a to 22f are output from pulse generation circuit 65.

When receiving the control pulse data, the pulse correction circuit 66 changes the change time data and the change flag of the received control pulse data to change the control pulses of the gate pulses 22a to 22f whose dead time and minimum on-pulse time are guaranteed. Data is generated and transmitted to the pulse generation circuit 65 via the system bus 661.

The pulse generation circuit 65 has the same configuration as the pulse generation circuit 63 of the first embodiment described with reference to FIG.
The pulse generating circuit 63 generates three gate pulses 631u, 631v, 631w of U-phase, V-phase, and W-phase, while the pulse generating circuit 65 generates gate pulses on the positive and negative sides of each of the three phases. That is, six gate pulses 22a-
22f is different. When receiving the corrected control pulse data from the pulse correction circuit 66, the pulse generation circuit 65 receives the gate pulses 22a to 22f on the same principle as the pulse generation circuit 63 of the first embodiment described with reference to FIG.
Occurs.

FIG. 9 is a block diagram showing the structure of the pulse correction circuit 66. The pulse correction circuit 66 includes a U-phase pulse correction circuit 66u that generates control pulse data for the U-phase gate pulses 22a and 22b, and a V-phase pulse correction circuit 66v that generates control pulse data for the V-phase gate pulses 22c and 22d. And the W-phase gate pulse 22
e, 22f, a W-phase pulse correction circuit 66w for generating control pulse data, a register 6691 for storing the pulse generation cycle time, and a register for setting the minimum value of the time when the gate pulse is in the high level state, that is, the minimum on-pulse time 6692 and a register 6693 for setting a dead time at which two gate pulses of each phase are simultaneously brought to a low level state.

Each input terminal of the registers 6691, 6692, and 6693 is connected to the system bus 613.
The output terminals of the registers 6691 and 6692 are U phase, V
-Phase and W-phase pulse correction circuits 66u, 66v, 66w
Are connected to the first and second input terminals of an arithmetic circuit 664u for calculating the minimum value of the pulse change time that satisfies the minimum on-pulse time. The output terminal of the register 6693 is connected to each of the U-phase, V-phase, and W-phase pulse correction circuits 66.
adder circuit 66 for adding a dead time to control pulse data for gate pulse 22a of u, 66v, 66w
6u and one input terminal of an adder 667u and the like for adding a dead time to control pulse data for the gate pulse 22b. U-phase pulse correction circuit 66u, V-phase pulse correction circuit 66v, and W
Since the phase pulse correction circuit 66w has the same configuration, the U-phase pulse correction circuit 66u will be described here to simplify the description.
The configuration will be described below.

The U-phase pulse correction circuit 66 u
A buffer 662u for temporarily storing the control pulse data received from No. 1, a buffer 663u for temporarily storing the control pulse data one pulse generation cycle before, the above-described arithmetic circuit 664u, and a pulse satisfying the minimum on-pulse time It comprises a selector 665u for selecting the change time, the above-mentioned addition circuits 666u and 667u, and a selector 668u for selecting the control pulse data stored in the buffer 663u.

The input terminal of the buffer 662u is connected to the system bus 612, and the output terminal of the buffer 662u is connected to one input terminal of the selector 665u. Output terminals of the selector 665u are added to adders 666u and 667.
u are connected to the other input terminals. The output terminals of the adder selectors 666u and 667u are connected to the system bus 661 and the first terminals of the selector 668u.
And the second input terminal. The output terminal of the selector 668u is connected to the input terminal of the buffer 663u, and the output terminal of the buffer 663u is connected to the arithmetic circuit 66
4u is connected to the third input terminal.

Next, the operation of the U-phase pulse correction circuit 66u will be described. The arithmetic circuit 664u calculates the value obtained by subtracting the pulse generation cycle time of the register 6691 from the value obtained by adding the pulse change time before the one pulse generation cycle stored in the buffer 663u and the minimum on-pulse time of the register 6692, that is, The minimum value of the pulse change time for satisfying the minimum on-pulse time in the pulse generation cycle is calculated and output to the selector 665u.

The selector 665u determines whether the valid flag of the buffer 663u is 0, that is, the gate pulse has not changed in the previous pulse generation cycle, or the valid flag of the buffer 662u is 0, that is, the gate pulse is not changed in the next pulse generation cycle. If there is no change, or if the pulse change time of the buffer 662u is equal to or more than the output value of the arithmetic circuit 664u, that is, if the minimum on-pulse time is satisfied, the pulse change time of the buffer 662u is selected and output to the adder circuits 666u and 667u.
When the valid flags of the buffers 663u and 662u are both 1 and the pulse change time of the buffer 662u is less than the output value of the arithmetic circuit 664u, that is, when the minimum on-pulse time is not satisfied, the output value of the buffer 663u is selected as the pulse change time. And adders 666u and 667
output to u.

The adder circuit 666u adds the dead time of the register 6693 to the pulse change time of the control pulse data when the change flag of the buffer 662u is 1, that is, when the positive gate pulse 22a changes from low level to high level. Output to the system bus 661 and the buffer 6
The change flag of 62u is 0, that is, the gate pulse 2 on the positive side
When 2a changes from the high level to the low level, the control pulse data is output to the bus 661 without adding the dead time of the register 6693 to the pulse change time of the control pulse data.

The adder circuit 667u adds the dead time of the register 6693 to the pulse change time of the control pulse data when the change flag of the buffer 662u is 1, that is, when the negative gate pulse 22b changes from high level to low level. And the change flag of the buffer 662u is 0, that is, when the negative side gate pulse 22a changes from low level to high level, the dead time of the register 6693 is added to the pulse change time of the control pulse data. And outputs it to the system bus 661.

The selector 668u selects the control pulse data of the positive-side gate pulse 22a output from the adding circuit 666u when the change flag of the buffer 662u is 1, that is, when the positive-side gate pulse 22a is in the high level state. 663u, and when the change flag of the buffer 662u is 0, that is, when the negative gate pulse 22b is at a high level, the control pulse data of the negative gate pulse 22b output by the adding circuit 667u is selected and the buffer 663u is output. Output to

The registers 6691, 6692, 66
93 can be written and read by a command from the terminal 80 via the system bus 613.

FIG. 10 is a block diagram showing a configuration of a third embodiment in which the control device of the present invention is applied to a power conversion device. 10, the same components as those of the first embodiment of FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted.

This power conversion apparatus is provided with three sets of the pulse control device 50 and the pulse generation device 60 of the first embodiment shown in FIG. 1, that is, in a triple configuration.
The pulse control devices 50a, 50b, and 50c execute the same processing in synchronization with each other in each control cycle by control cycle start signals 531a, 531b, and 531c generated by the pulse control devices 50a, 50b, and 50c, respectively. Each pulse control device and each pulse generation device are connected by one data transmission line. For example, the pulse generation device 60a includes the pulse control devices 50a, 50b, and 50c.
And data transmission paths 70aa, 70ba, 70c
a. Pulse generator 6
0a, 60b, and 60c are pulse control devices 5 respectively.
A pulse generation period is generated in synchronization with an intermediate time among the reception times of the synchronization symbols transmitted from 0a, 50b, and 50c, and control pulse data transmitted from pulse control devices 50a, 50b, and 50c are compared. Normal control pulse data is selected, and gate pulses 22aa to 22af and 22ba to 22b are selected based on the selected control pulse data.
f, 22ca to 22cf are generated. Then, the majority circuit 90 determines the gate pulses 22aa to 22af, 22ba to 2
Gate pulses 22a to 22f are output from 2bf and 22ca to 22cf by majority of three inputs.

FIG. 11 is a block diagram showing a specific configuration of the pulse control device 50a of this embodiment. In addition,
The pulse control devices 50b and 50c have the same configuration. In FIG. 11, the output signal lines of the sensors 11, 21, 41 are connected to the input terminals of the A / D conversion circuit 51, respectively.
The input terminal of the / D conversion circuit 51 also receives a start signal 571 output from a synchronization circuit 57 for synchronizing the timer 53 with the pulse control devices 50b and 50c for each control cycle. An output terminal of the A / D conversion circuit 51 is connected to an input terminal of the arithmetic circuit 52, and an input / output port of the arithmetic circuit 52 is connected to the system bus 521 and the terminal 80. Control cycle start signals 531a, 531b, 531c are input to the input terminals of the synchronization circuit 57, and a start signal 571 output from the synchronization circuit 57 is input to the timer 53 and the A / D conversion circuit 51. The control start signal 531 output from the timer 53 corresponds to the data transmission path 70aa
, A transmission circuit 54 for transferring digital data to and from the pulse generation device 60a, a transmission circuit 55 for transferring digital data to and from the pulse generation device 60b via a data transmission path 70ab, and a data transmission path 70ac Transmission circuit 56 for transferring digital data to and from pulse generation device 60c, and other pulse control devices 50b and 50c.
c, respectively. Each transmission circuit 54,
The output terminals of 55 and 56 are respectively data transmission lines 70a.
a, 70ab, and 70c.

Next, the operation of the pulse control device 50a will be described. When the count for one control cycle is completed, the timer 53 outputs a control cycle start signal 531a to the pulse control devices 50b and 50c, and simultaneously outputs the control cycle start signal 531a to the synchronization circuit 57 and the transmission circuits 54, 55 and 56 to wait for a count start. become.

The synchronization circuit 57 is provided with a control cycle start signal 531
a, a control cycle start signal 531b output from the pulse control device 50b, and a control cycle start signal 531c output from the pulse control device 50c. Timer 53
And output to When receiving the start signal 571, the timer 53 starts counting the next control cycle.

The A / D conversion circuit 51 operates similarly to the A / D conversion circuit 51 of the first embodiment described with reference to FIG.

The operation circuit 52 operates similarly to the operation circuit 52 of the first embodiment described with reference to FIG. However, the arithmetic circuit 52 according to the present embodiment includes the generated control pulse data and the pulse generation device 60a,
The instructions to 60b and 60c are transmitted to the transmission circuits 54, 55 and 56 via the bus 521, and the transmission circuits 54, 55 and 56 are transmitted.
From the pulse generators 60 a and 60 via a bus 521.
When the response data from b and 60c is transmitted, the transmitted response data is transmitted to the terminal 80.

The transmission circuits 54, 55, and 56 operate in the same manner as the transmission circuit 54 of the first embodiment described with reference to FIG. Upon receiving the control cycle start signal 531a, the transmission circuits 54, 55, and 56 respectively transmit a synchronization symbol indicating the start of the control cycle to each of the data transmission paths 70aa, 70ab, and 70a.
c to the pulse generators 60a, 60b, 60c. The transmission circuits 54, 55, 56 respectively
The control pulse data transferred from the arithmetic circuit 52 and the command to each pulse generator are transmitted to each data transmission line 70aa, 7aa.
0ab, 70ac through the pulse generators 60a, 60a
b, 60c. Also, the transmission circuits 54, 55, 56
Are pulse generators 60a, 60b, 60c, respectively.
Response data from each of the data transmission paths 70aa, 70a
b, when it is received via 70ac, the received response data is transferred to the arithmetic circuit 52.

FIG. 12 is a block diagram showing a specific configuration of the synchronization circuit 57 of the present embodiment and a time chart for explaining the operation. FIG. 12A is a block diagram of the synchronization circuit 57, and FIG. 12B is a time chart for explaining the operation of the synchronization circuit 57.

In FIG. 12A, the synchronization circuit 57
AND gate 572, 573, 574 and OR gate 5
75. The control cycle start signals 531a and 531c are input to the AND gate 572, and
The gate 573 has control cycle start signals 531a and 531
b is input, and the control cycle start signals 531 b and 531 c are input to the AND gate 574. Output terminals of the AND gates 572, 573, and 574 are connected to input terminals of a three-input OR gate 575, respectively, and an output terminal of the OR gate 575 outputs a start signal 571.

Next, the operation of the synchronization circuit 57 will be described. A
The ND gate 572 controls the control cycle start signals 531a and 531.
When both the logical values 1c become the logical value 1, the logical value 1 is output. Similarly, the AND gate 573 outputs the control cycle start signal 5
31a and 531b, and the AND gate 574 outputs a logical value 1 when both of the control cycle start signals 531b and 531c become a logical value 1. OR gate 575 is
When any one of the output signals from the D gates 572, 573, and 574 has a logical value 1, the logical value 1 is output as a start signal 571 when the logical value is 0. That is, the synchronization circuit 57 outputs the control cycle start signals 531a and 531
When any two of the three inputs b and 531c have a logical value of 1, a start signal 571 is output as a result of majority decision.

In FIG. 12B, at time t1, the control cycle start signals 531a, 531
Although the timings of 1b and 531c are shifted, the synchronization circuit 57 outputs the start signal 571 in accordance with the control cycle start signal 531a whose input timing is intermediate by majority decision. This is performed in the same manner in all the synchronous circuits of the pulse control devices 50a, 50b, and 50c. Therefore, all the pulse control devices perform sampling of voltage and current values of a DC power supply and the like, analog-digital conversion, generation of control pulse data,
And transmitting the control pulse data and the synchronization symbol to all the pulse generation devices at the same timing. Further, since the timer 53 of each pulse control device starts counting the next control cycle in response to the start signal 571, all the pulse control devices are controlled at the start of the next control cycle (time t2) as long as the timer operates normally. The cycle start signal is output simultaneously. Further, even when the timer of one of the pulse control devices fails to output the control cycle start signal as in the case of time t3, the timer is controlled by the control cycle start signal output by the other two pulse control devices. All pulse controllers, including the failed pulse controller, output the activation signal 571 simultaneously.

FIG. 13 is a block diagram showing a specific configuration of the pulse generation device 60a of the present embodiment. The pulse generators 60b and 60c have the same configuration.
The pulse generating device 60a transfers digital data between the pulse control device 50b via the data transmission line 70aa and the transmission circuit 61a which transfers digital data to / from the pulse control device 50a via the data transmission line 70aa. A transmission circuit 61b, a transmission circuit 61c for transferring digital data between the pulse control device 50c via a data transmission path 70ca, a timer 62, and a pulse generation circuit 63
, A pulse correction circuit 64, and pulse control devices 50a, 50
A synchronization circuit 67 for synchronizing the timer 62 with an intermediate time among the reception times of the synchronization symbols transmitted from the communication symbols 0b and 50c.
And a selection circuit 68 for comparing control pulse data transmitted from the pulse control devices 50a, 50b, and 50c to select normal control pulse data.

The input terminals of the transmission circuits 61a, 61b, 61c are connected to the data transmission lines 70aa, 70ba,
70ca is connected, and the transmission circuits 61a, 61b, 61c
The input / output ports on the inner side of the pulse generator 60a are connected to the system bus 613, respectively. The transmission circuits 61a, 61b, 61c are respectively connected to the system bus 6
12a, 612b, and 612c are connected to the input terminal of the selection circuit 68, and the transmission circuits 61a, 61b,
Synchronization signals 611a and 61 output from 61c, respectively.
1b and 611c are input to the synchronization circuit 67, respectively.
The selection circuit 68 is connected to the system bus 613 and at the same time to the pulse generation circuit 63 via the system bus 681. The timer 62 is connected to the system bus 613 and receives an activation signal 671 from the synchronization circuit 67. The time 621 output from the timer 62 is input to the pulse generation circuit 63, and the control pulses 631u, 631v, and 631w output from the pulse generation circuit 63 are input to the pulse correction circuit 64. The pulse correction circuit 64 is connected to the system bus 613 and outputs gate pulses 22aa to 22af.

Next, the operation of the pulse generator 60a will be described. The transmission circuits 61a, 61b, and 61c operate similarly to the transmission circuit 61 of the first embodiment described with reference to FIG. The transmission circuits 61a, 61b, 61c are respectively
When the synchronization symbols are received from the pulse control devices 50a, 50b, and 50c via the data transmission lines 70aa, 70ba, and 70ca, the synchronization signals 611a and 611 are transmitted to the synchronization circuit 67.
11b and 611c are output. The transmission circuits 61a, 61
1b and 61c are pulse control devices 50a and 50c, respectively.
0b, 50c to the respective data transmission lines 70aa, 70ba,
When the control pulse data is received via 70ca, the received control pulse data is transferred to each system bus 612a, 61b.
The data is transferred to the selection circuit 68 via 2b and 612c. The transmission circuits 61a, 61b, and 61c respectively transmit the data transmission lines 7 from the pulse control devices 50a, 50b, and 50c.
When a command from the terminal 80 is received via Oaa, 70ba, 70ca, the received command is transferred to the timer 62 or the pulse correction circuit 64 via the system bus 613.
When the transmission circuits 61a, 61b, and 61c receive response data from the timer 62 or the pulse correction circuit 64 and abnormality detection information from the selection circuit 68 via the system bus 613, the transmission circuits 61a, 61b, and 61c transmit the received response data to the respective data transmission units. The signals are transmitted to the pulse control devices 50a, 50b, and 50c via the paths 70aa, 70ba, and 70ca.

The synchronization circuit 67 has synchronization signals 611a, 61
1b and 611c, the pulse controller 50
The activation signal 671 is output at an intermediate timing among the reception timings of the synchronization symbols transmitted from a, 50b, and 50c. The synchronization circuit 67 is realized by the same configuration as the synchronization circuit 57 of the pulse control device 50a shown in FIG.

The timer 62 operates in the same manner as the timer 62 according to the first embodiment described with reference to FIG. However, in the first embodiment, the synchronization signal 611 is input to the timer 62, but in the present embodiment, a start signal 671 of the synchronization circuit 67 is input instead of the synchronization signal 611.

The pulse generating circuit 63 operates similarly to the pulse generating circuit 63 of the first embodiment described with reference to FIG.

The pulse correction circuit 64 operates similarly to the pulse correction circuit 64 of the first embodiment described with reference to FIG.

FIG. 14 is a block diagram showing the configuration of the selection circuit 68 of this embodiment and a table for explaining a method of selecting control pulse data. FIG. 14A is a block diagram of the selection circuit 68, and FIG. 14B is a table for explaining a method of selecting control pulse data.

In FIG. 14A, the selection circuit 68
Buffers 684, 685, 686 for temporarily storing control pulse data transferred from the transmission circuits 61a, 61b, 61c via the system buses 612a, 612b, 612c, respectively, and buffers 684, 685
A comparison circuit 68 for comparing the control pulse data stored in 686 with each other and selecting normal control pulse data.
2 and a selector 683 for outputting the control pulse data selected by the comparison circuit 682.

The input terminal of the buffer 684 is connected to the system bus 612a, and the output terminal of the buffer 684 is connected to the respective input terminals of the comparison circuit 682 and the selection circuit 683. The input terminal of the buffer 685 is connected to the system bus 612b, and the output terminal of the buffer 685 is connected to the respective input terminals of the comparison circuit 682 and the selection circuit 683. An input terminal of the buffer 686 is connected to the system bus 612c, and an output terminal of the buffer 685 is connected to respective input terminals of the comparison circuit 682 and the selection circuit 683. The output terminal of the comparison circuit 682 is connected to the system bus 613 and the selection circuit 683. The output terminal of the selection circuit 683 is the system bus 68
1 connected.

Next, the operation of the selection circuit 68 will be described. The comparison circuit 682 stores the buffer 6 in each pulse generation cycle.
The control pulse data stored in 84, 685, and 686 are compared with each other, and the control pulse data determined to be normal is instructed to the selection circuit 683. The selection circuit 683 transmits the control pulse data specified by the comparison circuit 682 to the system bus 6.
The signal is transferred to the pulse generating circuit 63 via 81.

When the comparison circuit 682 determines that at least one control pulse data is abnormal by comparing and checking the control pulse data, the comparison circuit 682 instructs another normal control pulse data to the selection circuit 683, The data abnormality detection information is transferred to the transmission circuits 61a, 61b, 61c via the system bus 613. The transmission circuits 61a, 61b, and 61c respectively transmit the control pulse data abnormality detection information to the pulse control devices 50a, 50b.
b, 50c and the pulse control devices 50a, 50b,
50c respectively transfers control pulse data abnormality detection information to the terminal 80. The control pulse data abnormality detection information specifies the source (pulse control device) of the control pulse data determined to be abnormal and the contents of the control pulse data.

The table of FIG. 14B shows the selection of control pulse data and the judgment of abnormality in the comparison circuit 682. Here, da, db, and dc represent control pulse data transmitted from the pulse control devices 50a, 50b, and 50c, respectively.

As shown in the table of FIG. 14B, the comparison circuit 682 makes three comparisons of control pulse data da and db, db and dc, and da and dc, and two or more control pulse data are normal. If so, the priority is selected as da, db, dc. That is, if all three comparisons match, then d
Since a, db, and dc are all normal, da is selected. If the two comparisons do not match, the control pulse data included in both of the two mismatched comparisons is abnormal, and the other two control pulse data Is determined to be normal, and a selection is made based on the above-mentioned priorities. If the comparison results in a mismatch only in one comparison, it cannot be caused by an abnormality in the change point data, so that it is determined that there is an abnormality in the comparison circuit, and one control pulse data not included in the mismatched comparison is included. That is, control pulse data determined to be normal is selected.

FIG. 15 shows a majority decision circuit 90 of the present embodiment.
1 is a block diagram showing the configuration of the first embodiment and a time chart for explaining the operation. FIG. 15A is a block diagram of the majority decision circuit 90, and FIG. 15B is a time chart for explaining the operation.

In FIG. 15A, the majority circuit 90 is constituted by majority circuits 90a to 90f which output the respective gate pulses 22a to 22f. Here, the configuration of the majority circuit 90a will be described for the sake of simplicity, but the majority circuits 90b to 90f have the same configuration.

The majority circuit 90a includes an AND gate 91,
92 and 93, and an OR gate 94. AN
Gate pulses 22aa and 22ca are input to the input terminal of the D gate 91, and its output terminal is connected to the input terminal of the three-input OR circuit 94. Gate pulses 22aa and 22ba are input to the input terminal of the AND gate 92, and its output terminal is connected to the input terminal of the three-input OR circuit 94. The input terminal of the AND gate 93
The gate pulses 22ba and 22ca are input, and the output terminals are connected to the input terminal of the three-input OR circuit 94.

Next, the operation of the majority circuit 90a will be described. The AND gate 91 outputs gate pulses 22aa and 2aa.
When both 2ca have the logical value 1, the logical value 1 is output. Similarly, the AND gate 92 outputs the gate pulse 22a.
a and 22ba indicate that the AND gate 93 has the gate pulse 2
When both 2ba and 22ca have the logical value 1, the logical value 1 is output. The OR gate 94 is connected to the AND gate 9
When any one of the output signals 1, 92, and 93 becomes a logical value 1, the logical value 1 is output as a gate pulse 22a.

In FIG. 15B, the pulse generator 6
The gate pulses 22aa, 22ba, 22c due to variations in processing time in the respective devices 0a, 60b, 60c.
Although there is a time lag in a, synchronization can be achieved again by taking the majority decision of the gate pulses 22aa, 22ba, 22ca in the majority circuit 90. Further, even if one of the pulse generators fails and no longer outputs a gate pulse as in the case of time t3, or if the gate pulse is output at an improper timing, the majority decision circuit 90 takes a majority vote to make it normal. A gate pulse can be output.

In this embodiment, the multiplexed pulse control devices 50a, 50b, and 50c also use the pulse generation devices 60a and 60 in which the control pulse data is multiplexed.
b, 60c, the multiplexed pulse controllers 50a, 50b, 50c transmit the operation command to the data transmission paths 70aa, 70ab, 70ac, 70ba, 70b.
pulse generators 60a, 60b, 60c multiplexed via bb, 70bc, 70ca, 70cb, 70cc
And the multiplexed pulse generators 60a and 60
b, 60c transmit the information of the operating state to the data transmission line 70aa,
70ab, 70ac, 70ba, 70bb, 70bc,
The multiplexed pulse control devices 50a, 50b, 50c are notified via 70ca, 70cb, 70cc.

In the above description, the control device of the three-phase power conversion circuit has been described. However, the control device of the multi-phase power conversion circuit other than the single-phase or three-phase power conversion device and the control device of the circuit device other than the power conversion device are also described. It is clear that the invention can be applied.

In the above description, a control device having a pulse control device and a pulse generation device each having a single configuration or a triple configuration has been described. However, a control device having a duplex or quadruple or more multiplex configuration has been described. Obviously, the present invention can be applied to the present invention.

[0107]

According to the present invention, a pulse control device for controlling a pulse signal and a pulse generating device for generating a pulse signal in accordance with an instruction from the pulse control device are connected by a data transmission line, and a reference time for pulse signal generation is provided. And notification of control pulse data, and furthermore, instructions from the terminal and notification of the operation state of the pulse generation device are executed through the same data transmission line, so that the pulse control device can be controlled with a smaller data transmission line regardless of the number of pulse signals. And a pulse generator, and redundant connection means for transmitting information other than the pulse signal is not required. Thus, the number of signal lines for connecting the multiplexed pulse control device and the pulse generation device can be reduced. Furthermore, since the accuracy of the pulse signal is independent of the number of pulse signals, the accuracy of the pulse signal does not change even if the number of pulse signals increases, and the change timing of the pulse signal is determined by the value of the pulse data. May be transferred in a range in time for the start time of the corresponding pulse generation period, and no error in the pulse signal occurs even when a general data transfer method such as packet transfer is used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment in which a control device according to the present invention is applied to a power converter.

FIG. 2 is a diagram showing a format of control pulse data of the power converter of FIG. 1 and a time chart showing a relationship between control pulse data and actual control pulses.

3 is a block diagram showing a configuration of a timer of the power converter of FIG. 1 and a time chart for explaining the operation thereof.

FIG. 4 is a block diagram showing a specific configuration of a pulse generation circuit of the power conversion device of FIG.

FIG. 5 is a time chart showing operations of the pulse control device and the pulse generation device of the power conversion device of FIG.

FIG. 6 is a block diagram showing a specific configuration of a pulse correction circuit of the power conversion device of FIG.

FIG. 7 is a time chart illustrating an operation of the pulse correction circuit of FIG. 6;

FIG. 8 is a block diagram showing a configuration of a second embodiment in which the control device according to the present invention is applied to a power converter.

9 is a block diagram illustrating a specific configuration of a pulse correction circuit of the power conversion device of FIG.

FIG. 10 is a block diagram showing a configuration of a third embodiment in which the control device according to the present invention is applied to a power converter.

11 is a block diagram showing a specific configuration of a pulse control device of the power conversion device in FIG.

12 is a block diagram showing a specific configuration of a synchronization circuit of the power conversion device in FIG. 10 and a time chart for explaining its operation.

FIG. 13 is a block diagram showing a specific configuration of a pulse control device of the power conversion device of FIG.

14 is a block diagram showing a specific configuration of a selection circuit of the pulse control device of FIG. 13 and a table for explaining a method of selecting control pulse data of a comparison circuit thereof.

15 is a block diagram showing a specific configuration of a majority circuit of the power converter of FIG. 10 and a time chart showing its operation.

[Explanation of symbols]

50, 50a, 50b, 50c Pulse controller 52 Operation circuit 53, 62 Timer 54, 55, 56, 61, 61a, 61b, 61c Transmission circuit 57, 67 Synchronous circuit 60, 60 ', 60a, 60b, 60c Pulse generator 63, 65 pulse generation circuit 64, 66 pulse correction circuit 68, 683 selection circuit 70, 70aa, 70ab, 70ac, 70ba, 70
bb, 70bc, 70ca, 70cb, 70cc Data transmission line 90 majority circuit 682 comparison circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Hotta 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory, Ltd. (72) Inventor Seiji Tanaka 3-chome, Sachimachi, Hitachi City, Ibaraki No. 1 Hitachi, Ltd. Hitachi Plant (72) Inventor Shigeta Ueda 2-1-1 Omika-cho, Hitachi City, Ibaraki Pref. Hitachi, Ltd. Power and Electricity Development Division (72) Inventor Akira Bando Ibaraki 5-2-1, Omika-cho, Hitachi City, Japan Inside the Omika Plant of Hitachi, Ltd.

Claims (10)

[Claims] 1. A control device comprising: a pulse control device that controls generation of a pulse signal; and a pulse generation device that generates the pulse signal in accordance with an instruction from the pulse control device. A reference timer that notifies the pulse generation device of a reference time that is a reference for the pulse generation device, and a pulse change time indicating a time from the reference time to a time when the pulse signal changes, and determines the pulse generation time to the pulse generation device. An arithmetic circuit for notifying, the pulse generation device is a synchronization timer that operates in synchronization with the reference time notified from the pulse control device, and temporarily changes the pulse change time notified from the pulse control device. And a pulse generation circuit that changes the pulse signal when the time indicated by the synchronization timer matches the pulse change time. Control apparatus characterized by comprising. 2. The pulse control device and the pulse generation device are connected by at least one data transmission path for transmitting a digital code, and the pulse control device transmits the reference time and the pulse change time in the same data. The control device according to claim 1, wherein the control unit notifies the pulse generation device via a road. 3. The arithmetic circuit of the pulse control device,
The pulse change time of each of the plurality of pulse signals is determined, and the pulse change time of each of the plurality of pulse signals is notified to the pulse generation device via the same data transmission path. The control device according to claim 2. 4. When the pulse control device does not notify the pulse generation device of the reference time or the pulse change time, the pulse control device issues an operation command to the pulse generation device via the data transmission path. The control device according to any one of claims 1 to 3, wherein the control unit notifies the pulse control device of the operation state or the abnormality detection to the pulse control device via the data transmission path. 5. The pulse generator further includes a pulse adjusting circuit that corrects the pulse change time according to a predetermined rule, adjusts a pulse width of the pulse signal, and supplies the adjusted pulse width to the pulse generating circuit. The control device according to any one of claims 1 to 4, wherein: 6. A control device comprising: a multiplexed pulse control device for controlling generation of a pulse signal; and a multiplexed pulse generation device for generating the pulse signal in accordance with an instruction from the pulse control device. The multiplexed pulse control devices perform the same operation in synchronization with each other, and each of them notifies a reference time serving as a reference of the pulse signal generation to all of the multiplexed pulse generation devices at regular intervals. A reference timer, and an arithmetic circuit that determines a pulse change time indicating a time from the reference time to a time at which the pulse signal changes, and notifies all of the multiplexed pulse generation devices, Pulse generators, each of which
Comparison of a synchronization timer that operates in synchronization with the intermediate time of the reference time notified from all of the multiplexed pulse control devices and the pulse change time notified from all of the multiplexed pulse control devices. A selection circuit that performs a comparison to select a normal pulse change time, and temporarily holds the pulse change time selected by the selection circuit, and sets the pulse when the time indicated by the synchronization timer matches the pulse change time. A control device, comprising: a pulse generation circuit that changes a signal. 7. The multiplexed pulse control device, wherein each of the multiplexed pulse control devices and each of the multiplexed pulse generation devices are connected by at least one data transmission line for transmitting a digital code. 7. The control according to claim 6, wherein each of the devices notifies the reference time and the pulse change time to all of the multiplexed pulse generation devices via the same data transmission path. apparatus. 8. The arithmetic circuit of the multiplexed pulse control device, wherein each of the arithmetic circuits determines a pulse change time of each of the plurality of pulse signals, and sets the same pulse change time of each of the plurality of pulse signals. The control device according to claim 6, wherein the notification is made to all of the multiplexed pulse generation devices via the data transmission path. 9. The multiplexed pulse control device issues an operation command when the multiplexed pulse control device has not notified the reference time or the pulse change time to the multiplexed pulse generation device. The multiplexed pulse generator notifies the multiplexed pulse generator via the data transmission path, and the multiplexed pulse generator notifies the multiplexed pulse controller via the data transmission path. Further, the selection circuit of the multiplexed pulse generation device, when each of them detects a mismatch by comparison and comparison of the pulse change time, the multiplexed pulse via the digital data transmission path The control device according to any one of claims 6 to 8, wherein the control device is notified of the mismatch detection of the pulse change times. 10. The multiplexed pulse generator,
The apparatus further includes a pulse adjustment circuit that corrects the pulse change time notified from the multiplexed pulse control device according to a predetermined rule, adjusts the pulse width of the pulse signal, and supplies the pulse width to the pulse generation circuit. The control device according to claim 6, wherein: