JPH10283781A - Multiport memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed multiport memory system having high data identity by suppressing excessive reading-out operations caused by data being written by using a timing control circuit which controls the activating timing of a writing word line and the activating timing of a reading-out word line in one machine cycle. SOLUTION: The accessing speed to a multiport memory is increased by securing the identity between writing data and reading-out data by suppressing the potential fluctuation at an unnecessary bit line by activating the word line of a reading-out system at writing ending timing in a memory cell 101 by providing a timing control circuit ill which controls the writing timing and reading-out timing to and from the memory cell 101 in one machine cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, it relates to a multi-port static random access memory.

[0002]

2. Description of the Related Art FIG. 7 is a schematic diagram showing an embodiment of Japanese Patent Application Laid-Open No. 62-175992. Generally, a multi-port memory as described above (in this example, a dual-port memory having two ports is described) has a plurality of bit line pairs and word lines (two in this example) in each memory cell. It is composed of memory cells. In such a multi-port memory, simultaneous access from two ports respectively connected to two pairs of bit lines and word lines to a memory cell of the same address is called access conflict. To realize data stability when such access contention occurs is disclosed in, for example,
No. 175,992. In this example,
When an access conflict occurs in which a write request from the A port and a read request from the B port occur at the same time, after the write operation from the A port is completed, the B port side is set so that read data is output from the B port. Control the output section.

[0003]

In the above configuration, when an access is requested from two ports to a memory cell having the same address, the fact that the write signal to the port is negated is used as a trigger to output the data to the output section. This is used as a latch control signal to prevent unstable data from being output to the outside during the writing process into the memory cell. Therefore, for the bit line to be read, the bit line potential changes once due to the data stored in the memory cell before rewriting, and then the bit line potential changes due to the rewritten data. Will be implemented. Therefore, when the data in the memory cell is updated, an extra change in the potential of the bit line occurs before and after the writing, and the extra reading time is required as compared with a case where access competition does not occur.

That is, when a write request and a read request to the same memory cell compete with each other, the data in the memory cell being rewritten by the write circuit once drives the read bit line and is read to the bit line. If the read data is different from the rewritten data, it is necessary to read the data on the read bit line again. Since it is necessary to correct the potential change of the bit line with a heavy load in the reverse direction, the reading is delayed as compared with the normal reading timing. In some cases, there is a possibility that data being written is output to the outside.

In a memory system using a sense amplifier circuit for amplifying a potential change of a bit line and outputting the amplified voltage to the outside, the activation timing of the sense amplifier must be changed in order to avoid a malfunction in which amplification occurs in a transient state. Since it is necessary to design in accordance with the timing when the access conflict occurs, the output timing cannot be advanced even when the access conflict does not occur.

An object of the present invention is to provide a multi-port memory capable of shortening a read time when an access conflict occurs, and thus, having an earlier output timing when no access conflict occurs. . Another object of the present invention is to provide a multi-port memory that can prevent data in the middle of writing from being output to the outside and can guarantee the identity of write data and read data.

[0007]

According to a first aspect of the present invention, there is provided a multi-port memory comprising a plurality of ports to which data signals, address signals and control signals can be input independently, and a plurality of independent ports corresponding to the plurality of ports. And a memory for reading and writing data from a plurality of ports, and a machine for reading data from a memory cell after completion of writing data to the memory cell when a write request and a read request occur simultaneously. A timing control circuit is provided which generates a write timing signal and a read timing signal by shifting them in a cycle.

According to this structure, by providing the timing control circuit for controlling the timing of writing to the memory cell and the timing of reading from the memory cell within one machine cycle, the reading is performed at the timing when the writing to the memory cell is completed. The word line corresponding to the port to be used can be activated, and as a result, unnecessary bit line potential changes can be suppressed, and the speed of memory access can be increased while ensuring the sameness of write data and read data. Can be realized.

According to a second aspect of the present invention, in the multiport memory according to the first aspect, the timing control circuit simultaneously generates a data write request to a memory cell and a data read request from a memory cell. A write timing signal, and a write determination circuit that receives the write timing signal and determines whether data has been completely written into a memory cell that stores data. The write determination circuit is equivalent to a memory cell. A write data generating circuit for generating write data for inverting the stored contents of the dummy memory cell in response to a write timing signal and applying the write data to the dummy memory cell, and writing to the dummy memory cell Write data and dummy memory cells A data match detection circuit for detecting the match of the read data, and a write detection circuit for detecting the completion of the writing of the data in the dummy memory cell based on the output of the data match detection circuit. And

According to this configuration, the timing control circuit is composed of the write decision circuit for judging that the data in the dummy memory cell has been rewritten and the reference timing generation circuit. Accurate detection is possible, and it becomes easy to accurately control the write timing to the memory cell and the read timing from the memory cell within one machine cycle.

As described above, according to the present invention, even when reading and writing are simultaneously requested for the same memory cell during one cycle, writing into the memory cell is completed and Since the read operation is performed after the data in the cell is determined, the data can be read at the same timing regardless of which memory area is requested to access (that is, when access conflict occurs). Therefore, the memory cycle time of the multiport memory can be reduced.

Here, the reason why data can be read at the same timing regardless of which memory area is requested to access will be described. When access contention occurs, the memory is usually prevented from operating at high speed. That is, when an access is requested from two ports to a memory cell at the same address, the fact that the write signal to the port is negated is used as a trigger to provide a control signal for the latch of the output section, and during the process of writing into the memory cell, It prevents unstable data from being output to the outside. For this reason, for the bit line to be read, after the bit line potential changes due to the data stored in the memory cell before being rewritten, the change in the bit line potential due to the newly rewritten data is not performed. Will be implemented. Therefore, when the data in the memory cell is updated before and after the writing, an extra change in the potential of the bit line occurs, which requires extra reading time as compared with a case where access competition does not occur. In particular, in a memory system using a sense amplifier circuit that amplifies a potential change of a bit line and outputs the amplified signal to the outside, the activation timing of the sense amplifier circuit is set to avoid a malfunction in which amplification occurs in a transient state. Since it is necessary to design in accordance with the timing when the access conflict occurs, the output timing cannot be advanced even when the access conflict does not occur. Further, when the write data is determined using the output data from the memory cell array, it is necessary to determine the data on a bit line with a heavy load as a criterion, so that the control itself becomes slow.

On the other hand, when the read operation is started after the data in the memory cell is determined, since the timing is controlled without passing through the bit line, the control can be performed at high speed. In addition, the word line on the read side is configured to be activated after writing is detected.
During the write operation, the bit line is driven in the direction opposite to the final data by the remaining data in the memory cell, so that an unnecessary change in the potential of the bit line does not occur. This also has the effect of speeding up.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multi-port memory according to an embodiment of the present invention will be described with reference to the drawings. [First Embodiment: Corresponding to Claim 1] FIG. 1 is a schematic configuration diagram of a multi-port memory according to a first embodiment of the present invention, and FIG. 2 shows a configuration of a memory cell of the multi-port memory. It is shown. For simplicity, in this embodiment, the description will be made using a dual-port memory having two independent ports (A port and B port).

In FIG. 1 and FIG. 2, reference numeral 101 denotes a memory cell array including a large number of memory cells 100 for storing data. Memory cell 100 is a flip-flop configured inverter 100A, 100 for storing data.
Bit line pairs BLa and XBLa for outputting data, comprising input / output gates 100C to 100F formed of N-channel transistors corresponding to two ports independent of B.
And bit line pair BLb, XBLb, memory cell 100
Are connected to a word line WLa and a word line WLb which control input / output of data to / from the memory cell.

Reference numerals 102a and 102b are address registers for storing addresses, and 103a and 103b are row decoders for decoding row address information. Row decoder 10
The output terminals of 3a and 103b are connected to word line control circuits 104a and 104b for controlling the activation timing of word lines. Each bit line pair BLa, XBL
a and a bit line pair BLb, XBLb are a column selection circuit 10 for selecting a bit line corresponding to the corresponding column address information.
6a and 106b. Column selection circuit 106
An input / output circuit for amplifying data data and data read on the bit line during reading and outputting the amplified data to the outside, and writing data data and data into the selected memory cell 100 during writing. 107a and 107b are connected.

Reference numeral 111 denotes a word line control circuit 104
a, 104b, input / output circuits 107a, 107b, a precharge circuit 105a for setting a bit line to a predetermined potential,
The timing control circuit 105b controls the write request signal WE and the read request RE to generate a write timing signal WTS and a read timing signal RTS. An address conflict detection circuit 109 detects that the address signal ADDRa for the A port coincides with the address signal ADDRb for the B port and generates a strong detection signal.

Reference numeral 110 denotes an address conflict detection circuit 10.
9 and the read request signals RREa, RREb, write request signals WRea,
WREb and the write timing signal WTS and the read timing signal RTS generated by the timing control circuit 111 are input and the write enable signal WEEa,
WEEb and read enable signals REEa and RE
This is a control signal generation circuit that generates Eb.

The operation of the multi-port memory configured as described above will be described below with reference to FIGS. 1, 2 and 3. Here, FIG. 3 is a timing chart showing a schematic operation timing of the multiport memory. In this embodiment, an example will be described in which a cycle in which access contention occurs during a three-cycle period and a cycle in which access contention does not occur are included. In this multiport memory, two independent ports, A port and B port
Address signals ADDRa,
ADDRb and read request signals RREa, RRE
b, write request signals WRea and WREb are input. In the initial state in which no access request is received in this multiport memory, each bit line is precharged by precharge circuits 105a and 105b.

At time T0, when a write request WRRe is issued to port A, a read request signal RREb is issued to port B, and an access conflict occurs, it is assumed that the access start address indicates address An. explain. At time T0, a read request signal RREb and a write request signal WRea for the memory area are issued, and at the same time, the address An is input to the A port and the B port, respectively. The address comparison is performed by the address conflict detection circuit 109, and it is detected that an access conflict has occurred. The detection result is input to the control signal generation circuit 110. At this time, it is detected that the access request is writing to port A and reading is requested to port B, and is not a writing request to the same address.

At the same time, the timing control circuit 111 issues a request to access the multiport memory to the timing control circuit 111, and the timing control circuit 111 issues a read timing signal RTS and a write timing signal WT.
S is output to control signal generation circuit 110. The write timing signal WTS is designed to be generated at a time T1 after detecting that the write request signal WRRe has been asserted, and after a lapse of time sufficient to complete decoding of the row address.

When the write timing signal WTS is asserted, the write enable signal WEEa is sent from the control signal generation circuit 110 to the word line control circuit 10 on the A port side.
4a and the input / output circuit 107a. As a result, the bit lines BLa, BL selected by the column selection circuit 106a
Write data is output to the BLa by the input / output circuit 107a, and at the same time, the word line WL corresponding to the A port is output.
a is activated, and data is written to the memory cell.

At timing T2 when the writing of data into the memory cell is completed, the timing control circuit 111 outputs a read timing signal RTS. As a result, the read enable signal REEb is issued from the control signal generation circuit 110 to the word line control circuit 104b and the input / output circuit 107b on the B port side, and at the same time, the word line WL
b is activated, and reading of data from the memory cell is started. At this time, the bit lines BLa,
Since writing from XBLa has been completed, even if data in the memory cell changes before and after writing,
In the bit lines BLb and XBLb on the B port side, no extra potential change occurs in a transient state in the memory cell. That is, a potential change in a phase opposite to that of data in the memory cell, which may cause erroneous reading, does not occur on the read bit line. Therefore, no extra timing margin is required for the read operation. In particular, the input / output circuit 1
In a memory system using a sense amplifier circuit for amplifying the potential change of the bit line at 07a and 107b, the potential change of the opposite phase may cause irreversible data output to an external output, and a large timing margin Therefore, the effect of increasing the speed according to this embodiment is great.

The timing T2 at which the writing of data into the memory cells is completed is set by, for example, a timer. That is, the timing is set by a timer or the like in accordance with the time when the writing is expected to end. Further, the address comparison is performed by the address conflict detection circuit 109, and if a write request to the same address is detected, a write from either port is performed so as to protect data coherency by a system protocol. Is performed with priority.

When only a read request is issued at time T4, only a read timing signal RTS is output from the timing control circuit 101 to the control signal generation circuit 110, and a read enable signal is output from the control signal generation circuit 110 as described above. REEb is issued to the B port, and only reading from the memory cell is performed. Similarly, at time T5
In the case where only a write request is issued, only the write timing signal WTS is output from the timing control circuit 111 to the control signal generation circuit 110, the write enable signal WEEa is issued from the control signal generation circuit 110 to the A port, and the memory cell Is written.

As described above, according to this embodiment,
The read timing signal R is synchronized with the time when the writing to the memory cell is completed by the timing control circuit 111.
TS is output to the control signal generation circuit 110, a read enable signal REEb is issued, and a word line corresponding to a read address is activated in accordance with the read enable signal REEb to start a read operation. In this case, no extra potential change occurs on the bit line. Therefore, it is possible to reduce unnecessary current consumption and to avoid erroneous reading due to a transient bit line potential change. As a result, an extra timing margin for avoiding erroneous reading can be eliminated, so that a high-speed multiport memory can be realized.

[Second Embodiment: Corresponding to Claim 2] A multiport memory according to a second embodiment of the present invention will be described with reference to the drawings. The basic configuration of the entire memory is the same as that of the multi-port memory shown in FIG. 1, and the timing control circuit 111 includes a reference timing generation circuit and a write determination circuit. FIG. 4 is a schematic block diagram of the write determination circuit, and FIG. 5 is a schematic block diagram of a timing control circuit including the reference timing generation circuit and the write determination circuit of FIG. FIG. 6 is a timing chart showing the operation of the timing control circuit. In the drawings, the same reference numerals denote the same parts.

In FIG. 4, reference numeral 410 denotes inverters 402 and 403 for storing data, and an N-channel transistor 4
This is a dummy memory cell composed of 00 and 401. The dummy memory cell 410 includes a dummy bit line pair DBL, XDBL for inputting data, and a dummy memory cell 410.
Word line DW controlling input / output of data to / from
L.

Reference numeral 408 designates a clock CLK and a write timing signal WTS as inputs, and a dummy bit line pair DBL,
XDBL, write bit line pair DW for dummy memory cell
Dummy word line DWL for generating write data to dummy memory cell 410 for BL and XDWBL and controlling write timing to dummy memory cell 410
Is a write data generation circuit that controls

Reference numeral 411 denotes first and second N-channel transistors 406 and 407 whose gates are connected to the dummy memory cell write bit line pair DWBL and XDWBL and whose sources are connected to the ground line, respectively. The drain and the source of each of the transistors 406 and 407 are connected, and the gate is connected to the dummy memory cell 410.
Is a data coincidence detection unit composed of N-channel transistors 404 and 405 connected to respective storage nodes nodeA and nodeB, and having a drain commonly connected to the match line ML. A write detection circuit 409 outputs the write detection signal WES at a high speed with the signal of the match line ML as an input.

Dummy bit line pair DBL and XDBL, dummy memory cell write bit line pair DWBL and XDWB
In L, dummy memory cells 410 are arranged and connected so that the load condition is equal to that of a normal memory cell array. In FIG. 5, reference numeral 501 designates a read request signal RE, a write request signal WE and a clock CLK as inputs, and a write timing signal WTS and a read timing signal RT.
A reference timing generation circuit that outputs S, and 502 is a write determination circuit shown in FIG.

The operation of the multi-port memory configured as described above will be described below with reference to FIGS. 1, 4, 5 and 6. The basic operation is the same as that of the multiport memory of FIG. 1 except that the timing control circuit is constituted by the circuit shown in FIG. At time T0 before the write request is made, the write data generation circuit 40
Reference numeral 8 denotes an inactive state, and the dummy word line DWL is set to a non-selected state (ground level). At this time, the dummy bit line pair DBL, XDBL is precharged to a predetermined precharge level (Vdd level in this example). Also, a dummy write bit line pair DWBL, X
DWBL is set to the ground level. The match line ML is precharged to a predetermined precharge level (Vdd level in this example) by the write detection circuit 409.

When the write request signal WRea is requested, the write request signal WE is supplied to the timing control circuit. By the input of the write request signal WE,
At time T1 when the decoding in the row decoder ends, the dummy word line DWL is activated. At the same time, write data is output to the dummy bit line pair DBL, XDBL and the dummy memory cell write bit line pair DWBL, XDWBL.

In this example, in the initial state, the storage node no
Description will be made assuming that low level is stored in deA and high level is stored in nodeB. From the write data generation circuit 408, the dummy bit line pair DBL, XDB
L, a write bit line pair DWBL for a dummy memory cell,
XDWBL is driven. In this case, the dummy bit line pair DBL, DWBL is driven to a high level, and the dummy memory cell write bit line pair XDBL, XDBL is driven to a low level.

At time T2, the dummy memory cell 41
By rewriting data in 0, a current path by the N-channel transistors 404 and 406 is generated between the match line ML and the ground line. With this, match line M
The potential of L is pulled down. As a result, the write detection circuit 409 detects a slight change in potential of the match line ML and generates a write detection signal WES. This write detection signal WES is output to the control signal generation circuit as a read timing signal RTS, and the read enable signal REEb is issued to the word line control circuit. As a result, the word line for reading is activated, and reading is started. The operation of the memory body at this time is basically the same as that described in the first embodiment.

At time T3, the next cycle is entered and the write request signal WE is negated. Dummy word line D
WL is inactivated and the dummy bit line pair DBL, XDB
L, dummy memory cell write bit line pair DWBL, X
DWBL is precharged / equalized and returned to the initial state. At this time, the potential of the dummy memory cell write bit line pair DWBL and XDWBL is set to the ground level. Thereby, the N-channel transistor 406
Are turned off, and the current path between match line ML and ground line is cut off. At the same time, the match line ML is precharged again by the write detection circuit 408 to prepare for the next write operation.

Time T at which the next write cycle starts
The operation from time 4 is the same as the operation from time T0 to time T3 described above. However, since the data in the dummy memory cell 410 is inverted, the dummy bit line pair DBL,
XDBL, write bit line pair DW for dummy memory cell
Driving of BL and XDWBL is also performed in reverse. This control is all performed in the write data generation circuit 408.

It should be noted that writing to the dummy memory cell 410 only needs to be performed for at least one cell if the timing is aligned with the slowest writing speed among all the memory arrays. Need only be connected as a load to the dummy bit line and the write dummy bit line. When no access conflict occurs, no data coherency problem occurs. Therefore, the write timing signal WTS and the read timing signal RTS can be generated by the reference timing generation circuit 501 without passing through the write determination circuit 408. . In this case, an extra write decision circuit 5
02 is no longer required to operate, so that there is an effect of reducing power consumption.

As described above, according to this embodiment,
When an access conflict occurs, the end of writing to the dummy memory cell is detected by the write detection circuit 409 in the timing control circuit, and thereafter, the read operation is performed by activating the word line corresponding to the read address. Start. Therefore, even when an access conflict occurs, no extra potential change occurs on the bit line. At the same time, unnecessary current consumption can be reduced, and erroneous reading due to a transient change in bit line potential can be avoided. In addition, by detecting writing to the dummy memory cell 410 having the same configuration as that of the memory cell array and synchronizing the same with the timing, it is possible to improve the accuracy of the timing control, and an extra timing for avoiding erroneous reading is obtained. Since the margin can be eliminated, a high-speed multiport memory can be realized.

[0040]

As described above, according to the multiport memory of the present invention, even when an access conflict occurs, an extra potential change does not occur on the bit line as compared with the conventional memory system. At the same time as reducing current consumption,
It is possible to avoid erroneous reading due to a transient bit line potential change. As a result, an extra timing margin for avoiding erroneous reading can be eliminated, so that a high-speed multiport memory can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a multi-port memory according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a memory cell of the multiport memory according to the first embodiment.

FIG. 3 is a timing chart for explaining an operation in the first embodiment.

FIG. 4 is a schematic block diagram of a read determination circuit according to a second embodiment of the present invention.

FIG. 5 is a schematic block diagram of a timing control circuit according to a second embodiment.

FIG. 6 is a timing chart for explaining an operation in the second embodiment.

FIG. 7 is a schematic block diagram of a conventional multiport memory.

[Explanation of symbols]

 Reference Signs List 100 memory cell 101 memory cell array 102 address register 103 row decoder 104 word line control circuit 105 precharge circuit 106 row selection circuit 107 input / output circuit 112 timing control circuit 112 control signal generation circuit 112 address conflict detection circuit

Claims (2)

[Claims] A plurality of ports capable of independently inputting data signals, address signals, and control signals; a plurality of independent input / output circuits corresponding to the plurality of ports; and a memory read / written from the plurality of ports. The write timing signal and the read timing signal are controlled within one machine cycle so that the operation of reading data from the memory cell is performed after the completion of the operation of writing data to the memory cell when the write request and the read request occur simultaneously. Multi-port memory with a timing control circuit that generates a shift. 2. A reference timing generating circuit for generating a write timing signal when a request to write data to a memory cell and a request to read data from the memory cell occur simultaneously, and a timing control circuit which receives the write timing signal as an input. A write determination circuit that determines completion of writing data to the memory cell storing data; the write determination circuit responds to the dummy memory cell having the same configuration as the memory cell and the write timing signal; A write data generating circuit for generating write data for inverting the storage content of the dummy memory cell and applying the write data to the dummy memory cell; and data to be written to the dummy memory cell and data written to the dummy memory cell. Data match detection circuit that detects a match And a write detection circuit for detecting completion of writing of data in the dummy memory cell based on an output of the data match detection circuit, wherein an output of the write detection circuit is used as a read timing signal. 2. The multiport memory according to 1.