JPH10283077A - Hot-line insertion type electronic device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To minimize fluctuations in power supply voltage of other packages in a main unit by minimizing inrush current due to increase in current consumption due to power supply pin connection, and to reduce It is an object of the present invention to provide a hot-line insertion type electronic device that prevents a circuit malfunction of another package. A power supply pin for precharge, a power supply pin, and an electronic circuit that operates based on a clock signal are connected to the power supply pin of the main body device earlier than the power supply pin when inserted into the main body device. In a hot-line insertion type electronic device that is configured to be precharged, the clock signal is output to the electronic circuit at a fixed level until a certain time elapses after the power supply pin is connected to the power supply. And a clock signal control means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hot-line insertion type electronic device, and more particularly to a hot-line insertion type electronic device suitable for use in an electronic device consuming a large amount of current.

[0002]

2. Description of the Related Art In an electronic device such as an electronic exchange, an electronic circuit package in which a semiconductor integrated circuit or the like is mounted on a printed wiring board can be mounted on a main unit such as a communication device by a hot-line insertion method.

FIG. 6 is a diagram showing a conventional hot-line insertion type electronic device. As shown in this figure, the conventional hot-line insertion type electronic device has live lines of a power supply pin Vcc, a signal pin Sig, a ground pin GND, and a precharge power supply pin PCHG connected to the main unit. By inserting these hot wires into the main unit, power is supplied from the main unit to the electronic circuit 2 so that the electronic circuit 2 operates.

Here, the length of each pin is set as GND> PCHG> Vcc> Sig.

When a live line is inserted, first, the longest ground pin GND is connected to the ground of the main unit. Next, the precharge power supply pin PCHG is connected to the power supply of the main unit. As a result, a current flows through the load capacitance 4 connected in parallel with the electronic circuit 2, and electric charges are accumulated.

A current is supplied to the electronic circuit 2 from a power supply unit of the main unit or a capacitance component of another package. The resistor 6 and the load capacitance 4 connected in series to the precharge power supply pin PCHG are connected to the electronic circuit 2. As a result, the voltage of the power supply line rises due to the time constant, thereby preventing an inrush current that affects the power supply level of another package.

[0007] By sufficiently accumulating electric charges in the load capacitance 4 until the power supply pin Vcc is connected to the power supply of the main unit, the rush current when the power supply pin Vcc is connected is suppressed. .

In addition to the above, recently, Japanese Patent Laid-Open No.
As described in Japanese Patent Application Laid-Open No. 138980/138, a method of controlling the operation of an electronic circuit in a package in a stepwise manner at the time of hot insertion of a package to suppress an inrush current is disclosed in JP-A-5-227658. As described, there is a method of suppressing the rush current by stopping the clock supply to the electronic circuit in the package by a switch when the package is hot-plugged.

[0009]

By the way, in the hot-line insertion type electronic device shown in FIG. 6, if the current consumption of the package into which the hot-line is inserted is sufficiently smaller than the current consumption of the main unit, Although there is no problem with the configuration, if the ratio of the current consumption to the current consumption of the main unit is very large,
When the power supply level of the package becomes a sufficient level after the precharge, and at the same time the electronic circuit 2 in the package enters the operation mode, the current consumption sharply increases.

At this time, the power supply pin Vcc of the package is
Is already connected to the power supply of the main unit, and the consumption current that increases sharply is reduced by the power supply pin Vc having a small impedance.
The power is supplied from another package or power supply unit of the main unit through c.

As a result, even if the inrush current is suppressed by using the precharging power supply pin PCHG at the time of hot-line insertion, the current due to a sudden increase in the current consumption cannot be suppressed, and other components in the main unit cannot be controlled. The power supply voltage of one package may fluctuate greatly, causing a malfunction of another package.

In the configuration described in JP-A-6-13890, the operation of the electronic circuit in the package is controlled to be on after the power supply pin is connected, so that the current consumption of the electronic circuit is suppressed. However, when the power supply pins are connected, no measures are taken to reduce the current consumption, so that a draw-in current is generated due to a sudden increase in the current consumption.

Therefore, even in this method, when the current consumption of the package occupies a large proportion of the current consumption of the main unit, the power supply voltage of another package in the main unit may fluctuate greatly, causing a malfunction of the circuit. is there.

In the configuration described in Japanese Patent Application Laid-Open No. Hei 5-227658, supply of a clock to an electronic circuit is started at once after the package is inserted. The power supply voltage of the package may fluctuate greatly, causing a malfunction of the circuit.

As described above, according to the conventional hot-line insertion configuration, when the current consumption of the inserted package accounts for a large proportion of the current consumption of the main unit, the electronic circuits in the package are simultaneously formed when the power supply pins are connected. When the operation mode is entered, a sudden increase in current consumption causes a draw-in current through the power supply pin Vcc from the main unit, which resembles an inrush current at the time of hot plugging, and may cause other packages to malfunction. There is.

In view of the above, the present invention minimizes the inrush current for suppressing the inrush current by using the precharge power supply pin and then increasing the current consumption by connecting the power supply pin to minimize the inrush current. It is an object of the present invention to provide a hot-plug type electronic device capable of suppressing a fluctuation in power supply voltage of another package in the device and preventing a malfunction of a circuit of another package at the time of hot-plug insertion.

[0017]

FIG. 1 is a diagram showing the principle of a hot-plug type electronic device according to the present invention. As shown in this figure, a precharge power supply pin PCHG and a power supply pin Vc
c, and an electronic circuit 18 that operates based on the clock signal CLK. The power supply pin PCHG for precharge is connected to the power supply of the main unit earlier than the power supply pin Vcc when inserted into the main unit, and the resistor 20 is connected to the power supply pin PCHG. In the hot-line insertion type electronic device configured to be precharged to the load capacitor 22 via the power supply pin Vcc, the clock signal CLK is not supplied until a predetermined time elapses after the power supply pin Vcc is connected to the power supply.
Clock signal control means 10 for controlling not to output to the electronic circuit 18.

In the invention configured as described above, the precharge power supply pin PCHG is connected to the power supply of the main unit, a current flows from the main unit through the precharge power supply pin PCHG and the resistor 20, and the load capacitance is changed. 22 is charged.

Since the charging is performed gradually by the time constant of the resistor 20 and the load capacitance 22, the rush current flowing from the power supply of the main unit through the power supply pin PCHG for precharging is suppressed.

Then, when the power supply pin Vcc is connected to the power supply of the main unit, the clock signal is output to the electronic circuit 18 by the clock signal control means 10 until the fixed time elapses, for example, a fixed level. .

The electronic circuit 18 starts operating because the power supply pin Vcc is connected to the power supply and the power supply voltage is supplied. However, the current consumption in the electronic circuit 18 is suppressed because the clock signal CLK is at a fixed level. You.

At the time when the power supply pin Vcc is connected to the power supply of the main unit, the current consumption of the electronic circuit 18 is suppressed, so that the drawing current flowing through the power supply pin Vcc from another electronic circuit mounted on the main unit is used. Is suppressed.

Therefore, the fluctuation of the power supply voltage of another electronic circuit can be suppressed, and the other electronic circuit does not malfunction. Further, the clock signal control means 10 includes a storage means 14 for storing the control signal and a storage means for setting the control signal to the first logic level until a certain time has elapsed from the time when the power supply pin Vcc is connected to the power supply. 14 and after the lapse of the predetermined time, the control means 12 sets the control signal to the second logical level and stores it in the storage means 14, and the clock signal CLK and the control signal are input. If the first logic level, the clock signal is output to the electronic circuit 18 at the fixed level, and if the control signal is the second logic level, the clock signal CLK is output to the electronic circuit 18 as it is. It is desirable to configure.

The clock signal control means 10 has a storage means 14 for storing the control signal, and sets the control signal to the first logic level until a predetermined time has elapsed immediately after the power supply pin Vcc is connected to the power supply. Output to the storage means 14,
After a lapse of a certain time, the control means 12 sets the control signal to the second logic level and outputs the control signal to the storage means, and the clock signal CLK and the control signal are inputted, and the control signal is set to the first level.
If it is a logic level, the fixed-level clock signal CLK
And a gate circuit 16 that outputs the clock signal as it is when the control signal is at the second logic level.

In a hot-insertion type electronic device having an electronic circuit operating in a low current consumption mode when an input signal is at a first logic level and operating in a normal current consumption mode when an input signal is at a second logic level, Until a predetermined time elapses from the time when the pin Vcc is connected to the power supply, a mode control means for setting the input signal to the first logic level and outputting the signal to the electronic circuit 18 may be provided.

Further, it is divided into a plurality of block circuits,
In a hot-line insertion type electronic device having an electronic circuit in which a control signal input to each block circuit is inactive at a first logic level and active at a second logic level, from the time when a power supply pin is connected to the power supply The circuit may include a block circuit control means for sequentially activating the control signals input to the block circuit from the first logic level to the second logic level.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 2 is a configuration diagram of a hot-line insertion type electronic device according to a first embodiment of the present invention.

The electronic device or package 30 of the hot-line insertion system includes a ground pin GND, a power supply pin PCHG for precharge, a power supply pin Vcc, a signal pin Sig, a resistor 32, a load capacitance 34, a processor 36, a register 38,
Clock source 40, MOSFET switch 42, LSI4
4, tri-state buffers 46, 48, 50, 52,
It includes resistors 54, 56, 58, 60 and an SRAM 62.

The ground pin GND is connected to the ground of the main unit at the time of insertion, and is connected to the ground line in the electronic device 30. Power supply pin P for precharge
The CHG is connected to a power supply of the main unit at the time of insertion, and is for precharging the load capacitance 34 from a power supply line in the electronic device 30 to suppress an inrush current.

The power supply pin Vcc is connected to a power supply of the main unit at the time of insertion, and is connected to a power supply line in the electronic device 30. The signal pin Sig is connected to a signal line of the main unit at the time of insertion, and is connected to a signal line in the electronic device 30.

As described above, the length of these pins is set as GND> PCHG> Vcc> Sig.

The resistor 32 is connected to a precharge power supply pin PC
It is provided between the HG and the power supply line, and precharges the load capacitance 34 with a predetermined time constant. Load capacity 3
Reference numeral 4 is provided between the power supply line and the ground line, and is used for precharging.

The processor 36 is connected to a power supply line and a ground line (not shown), is subjected to a power-on reset when the power supply line reaches a power supply potential, and controls a control signal CNT-SRAM and a control signal until a predetermined time elapses. CNT-CLOCK is set to a high level, and after a predetermined time elapses, the CNT-CLOCK is set to a low level. Software for executing these functions is installed.

The register 38 is connected to a power line and a ground line (not shown) and stores control signals CNT-SRAM and CNT-CLOCK from the processor 36. For example, the register 38 is a 2-bit set-type flip-flop. It consists of.

The clock source 40 is connected to a power supply line and a ground line (not shown), and receives a clock signal CL.
K is generated. MOSFET switch 42
Is the control signal CNT-CLO stored in the register 38.
ON / OFF is controlled by CK, for example, turning off at a high level and turning on at a low level.

The LSI 44 is a circuit operated by a clock signal CLK input to a clock terminal CLK.
When the clock signal is at a fixed level, current consumption is reduced.

Tristate buffers 46, 48, 5
0 and 52 are control signals CNT-S input to the control terminal.
When the RAM is at a high level, the output is set to a high impedance state.

The input terminal of the tri-state buffer 46 is connected to an address signal line, and the output terminal is
It is connected to 62 address terminals Address. The input terminal of the tri-state buffer 48 is connected to the chip select signal line, and the output terminal is connected to the chip select terminal CS of the SRAM 62.

The input terminal of the tristate buffer 50 is connected to a write enable signal line, and the output terminal is
It is connected to the write enable terminal WE of the SRAM 62. An input terminal of the tristate buffer 52 is connected to an output enable signal line, and an output terminal
Is connected to the output enable terminal OE.

The input terminals of the tri-state buffers 46 to 52 and the data terminal Data of the SRAM 62 are connected to the signal pin S
ig or a signal line (not shown) in the electronic device 30 from another electronic circuit.

The resistors 54, 56, 58 and 60 are pull-up resistors, for example, those of several KΩ are used. The resistor 54 is connected to the power supply line and the address terminal Addr of the SRAM 62.
Connected to ess. The resistor 56 is connected to the power line and the SR
It is connected to the chip select terminal CS of AM62.

The resistor 58 is connected to the power supply line and the write enable terminal WE of the SRAM 62. Resistance 60
Is the power supply line and the output enable terminal OE of the SRAM 62.
It is connected to the.

The SRAM 62 is a static random access memory which enters a low power consumption mode when a chip select signal, a write enable signal, and an output enable signal are at a high level, and the current consumption at this time is several times that in the operation mode. 1 or less.

Although not shown, the electronic device 30 monitors the voltage of the power supply line, and waits for the power supply voltage V
There is a power supply monitoring circuit that outputs a high-level monitoring signal to the set terminal of the flip-flop of the register 38 until it becomes equal to cc.

FIGS. 3A to 3D are time charts of FIG. 2, and FIG. 3A shows a precharge power supply pin PC.
HG voltage, FIG. 4B shows the clock terminal C of the LSI 44.
LK voltage, and FIG. 3C shows a control signal CNT-CLOCK.
, And the voltage of the CNT-SRAM, and FIG.
It is a figure which shows the consumption current of 0.

The operation of the first embodiment shown in FIG. 2 will be described below with reference to the time chart of FIG. When the electronic device 30 is inserted into the main device, the ground pin GN
D is connected to the ground of the main unit, and at time t = 0, the precharge power pin PCHG is connected to the power supply of the main unit.

Then, from the power supply of the main unit, through the precharge power supply pin PCHG and the resistor 32, the load capacitance 3
4, the voltage of the power supply line becomes EXP due to the time constant determined by the resistor 32 and the load capacitance 34.
(A / t).

The power supply monitoring circuit detects a rise in the voltage of the power supply line at time t0, and changes the monitoring signal to a high level until time t1 when the voltage of the power supply line becomes equal to Vcc, and outputs the signal to the set terminal of the register 38. I do.

At time t0 to t1, the register 38 is set by inputting a high level to the set terminal, and outputs the control signals CNT-CLOCK and CNT-SRAM at a high level.

At time t1, the power supply pin Vcc is connected to the power supply of the main unit, and the voltage of the power supply line is immediately equal to the power supply voltage of the main unit, for example, 5V. This power supply voltage is supplied to the processor 36 and the processor 3
6 is power-on reset, and the software is started.

At this time t1, the software is executed, the time is measured by a timer, and the control signals CNT-CLOCK and CNT are maintained until a certain time elapses.
-Make the SRAM high level and output it to the register 38.

The register 38 outputs the control signal CNT-CLOCK to the MOSF until a predetermined time elapses from the time t1.
It outputs the control signal CNT-SRAM to the ET switch 42 and the tri-state buffers 46 to 52 at high level, respectively.

The MOSFET switch 42 receives a high level and is turned off until a predetermined time elapses from the time t1, and outputs a low level to the clock terminal CLK of the LSI 44.

The clock terminal CLK of the LSI 44 is fixed at a low level until a certain time elapses from the time t1, and the current consumption of the LSI 44 is small. On the other hand, the tri-state buffers 46 to 52 control the control signal CNT input to the control terminal until a certain time elapses from the time t1.
Since the SRAM is at a high level, its output is in a high impedance state.

The resistances of the resistors 54 to 60 are pulled up by the power supply line because the outputs of the tri-state buffers 46 to 52 are in a high impedance state until a predetermined time has elapsed from the time t1, and the address terminals Adre of the SRAM 62.
ss, chip select terminal CS, write enable terminal WE,
And the output enable terminal OE becomes high level.

The SRAM 62 enters the low power consumption mode because the address terminal Address, the chip select terminal CS, the write enable terminal WE, and the output enable terminal OE are at high level.
The current consumption of AM62 is small.

As shown in FIG. 3D, until the fixed time elapses from the time t1, as shown in FIG.
The current consumption icc1 of the RAM 62 is reduced, and the drawn current does not suddenly flow from the power supply or the power supply line of the main unit through the power supply pin Vcc.

Then, when a certain time has elapsed from the time t1, the processor 36 sets the control signals CNT-CLOCK and CNT-SRAM to low level. Register 38
Are control signals CNT-CLOCK and CNT-SRAM
At a low level to the MOSFET switch 42 and the tri-state buffers 46 to 52.

The MOSFET switch 42 receives the control signal C
Since NT-CLOCK is at a low level, the switch is turned on, and the clock signal CLK from the clock source 40 is switched to LS.
It outputs to the clock terminal CLK of I44. LSI44
Operate in synchronization with a clock signal CLK, for example, in synchronization with a rising edge.

The tri-state buffers 46 to 52
Since the control signal CNT-SRAM input to the control terminal is at a low level, the input signal is output as it is. At this time, if the input signal is at a low level, a current flows from the power supply line to the ground through the resistors 54 to 60. However, since the resistance value of the resistors 54 to 60 is several KΩ, the flowing current is small and causes no problem.

The SRAM 62 operates normally because the tri-state buffers 46 to 52 output the input signals as they are. As a result, after a lapse of a certain time from the time t1, the LSI 44 and the SRAM 62 operate normally, and
Although the current consumption icc flows, the current consumption flows through the power supply pin Vcc when the clock is stopped or during the low power consumption mode of the SRAM 62. Therefore, the draw-in current does not suddenly flow, and the power supply voltage of the power supply line of the main unit is reduced. It does not fluctuate significantly.

According to the first embodiment described above, even when the current consumption of the inserted electronic device accounts for a large proportion of the current consumption of the device body, the power supply unit supplies the power supply pin Vcc.
It is also possible to suppress a current drawn through the device to a small value, suppress a power supply fluctuation of the entire device, and prevent a malfunction of another electronic circuit when a hot wire is inserted.

Second Embodiment FIG. 4 is a configuration diagram of a hot-line insertion type electronic device according to a second embodiment of the present invention. The electronic device or package 70 of the hot-line insertion system includes a ground pin GND, a precharge power supply pin PCHG, a power supply pin Vcc, and a signal pin Si.
g, resistor 72, load capacity 74, processor 76, register 78, and N block circuits 80-i (i = 1 to
N).

The ground pin GND, the power supply pin PCHG for precharge, the power supply pin Vcc, and the signal pin Sig
It is the same as that of the same code in FIG. The resistance 72 and the load capacitance 74 are the same as the resistance 32 and the load capacitance 34 in FIG.

The processor 76 is connected to a power supply line and a ground line (not shown). When the power supply line reaches a power supply potential, a power-on reset is performed, and the block circuit 80-i (i = 1 to
In order to make N) transition to the operation mode, the value of the control signal CNTi for controlling the transition of the operation mode is gradually raised to a high level, and a program for executing these functions is installed. .

The register 78 is for storing the control signal CTLi, and is constituted by an N-bit set type flip-flop or the like. Block circuit 80-i (i = 1
-N), the electronic circuit mounted on the electronic device 70 is divided into N blocks, and the block division method and the number of divisions N are gradually changed to the operation mode, and the overall consumption is controlled stepwise. By doing so, it is only necessary to suppress the drawn current.

Each block circuit 80-i receives a control signal CN
When Ti is at a low level, a low current consumption mode or an inactive mode is set. When control signal CNTi is at a high level, an operation mode is set.

For example, when the block circuit 80-i operates in synchronization with the clock and enters the low current consumption mode when the clock is stopped, the logical product of the control signal CNTi and the clock signal at the input side of the block circuit 80-i. Is used as a clock signal.

Although not shown, the electronic device 70 monitors the voltage of the power supply line, and waits for the power supply voltage V
It has a power supply monitoring circuit that outputs a high-level monitoring signal to the set terminal of the flip-flop of the register 78 until it becomes equal to cc.

FIGS. 5A to 5D are time charts of FIG. 4. FIG. 5A shows a precharge power supply pin PC.
HG voltage, FIG. 4B shows a precharge power supply pin PC.
HG, the current flowing through the power supply pin Vcc when only the precharge power supply pin PCHG is used, FIG.
FIG. 4D is a diagram showing a current flowing to the power supply pin Vcc in FIG.

The operation of the second embodiment shown in FIG. 4 will be described below with reference to the time chart of FIG. When the electronic device 70 is inserted into the main device, the ground pin GN
D is connected to the ground of the main unit. At time t = 0, the precharge power supply pin PCHG is connected to the power supply of the main unit, and the precharge power supply pin PCHG,
Since the load capacitance 74 is charged with electric charge through the resistor 72 and the load 72, the voltage of the power supply line is increased by EXP (A / t) by a time constant determined by the resistance 72 and the load capacitance 74.

The power supply monitoring circuit sets the register 78 by setting the monitor signal to a high level during a period from time t0 when the power supply line voltage rise is detected to time t1 when the power supply line voltage becomes equal to Vcc. Output to terminal.

The register 78 is set at the time t0 to t1 because the set terminal is at the high level, and outputs the control signal CNTi (i = 1 to N) at the high level. At time t1, the power supply pin Vcc is connected to the power supply of the main unit, and the voltage of the power supply line is immediately equal to the power supply voltage VCC of the main unit, for example, 5V.

Conventionally, as shown in FIG. 5C, after the power supply pin Vcc is connected, initially, the charge accumulated in the load capacitor 74 by the precharge supplies the current consumption of the electronic circuit. Since a current consumption is supplied through the power supply pin Vcc, a large current is drawn from the power supply unit.

On the other hand, in the present embodiment, the power supply voltage is supplied to the processor 76, the processor 76 is power-on reset, and the software is started. At this time t1, the software is executed, and the control signal CNTi is sequentially set to the high level from i = 1 to N at a constant interval by the control of the timer.
The control signal CNTi that has once been at a high level maintains the high level. For example, when CNTi goes high, CNTj (j = 1 to i-1) goes high and CNTj (j = i + 1 to N) remains low.

The register 78 outputs the control signal CNTi at high levels in the order of i = 1 to N at a fixed interval from time t1. When the control signal CNTi goes high, the block circuit 80-i operates in the operation mode.

At this time, the block circuits 80-j (j = 1 to
i-1) operates in the operation mode because the control signal CNTj is at the high level, and as shown in FIG. 5D, the block circuit 80-i starts operating at certain intervals, and the current consumption is reduced. Increases stepwise.

As a result, the drawn current flowing to the power supply pin Vcc increases stepwise and does not increase rapidly, so that the power supply voltage of the main unit does not fluctuate significantly. According to the second embodiment described above, even when the current consumption of the inserted electronic device accounts for a large proportion of the current consumption of the device main body, the current drawn from the power supply unit through the power supply pin Vcc can be suppressed to be small. Thus, power supply fluctuations of the entire device can be suppressed, and malfunction of other electronic circuits during hot-line insertion can be prevented.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following. In the second embodiment, the control signal CTLi is generated by the processor 76. However, the control signal CTLi is configured by an n-bit counter that is power-on reset and N selectors that output a high level or a low level using the counter value as a selection signal. May be.

For example, the selector that outputs the control signal CNT1 outputs a high level regardless of the value of the counter, and the selector that outputs the control signal CNT2 outputs a low level when the value of the counter is 0, Otherwise, it may be configured to output a high level.

[0081]

As described above, according to the first and second aspects of the present invention, a clock signal is not output until a predetermined time has elapsed since the power supply pin was connected to the apparatus main body. Therefore, the current consumption of the electronic circuit is reduced, and the current drawn through the power supply pin when the power supply pin is connected to the device main body can be suppressed. For this reason, it is possible to suppress the fluctuation of the power supply voltage of the power supply line of the electronic circuit of the apparatus main body, and to suppress the malfunction.

According to the third and fourth aspects of the present invention, the electronic circuit is set in the low current consumption mode until a predetermined time elapses after the power supply pin is connected to the apparatus main body.
The current consumption of the electronic circuit is reduced, and the current drawn through the power supply pin can be suppressed by connecting the power supply pin to the apparatus main body. Therefore, it is possible to suppress the fluctuation of the power supply voltage of the power supply line of the electronic circuit of the apparatus main body, and to prevent malfunction.

According to the fifth aspect of the present invention, a plurality of block circuits are sequentially activated until a predetermined time elapses immediately after the power supply pin is connected to the device main body, so that the current consumption of the electronic circuit is reduced. Is increased step by step, and a sudden change in the drawn current flowing through the power supply pin can be suppressed by connecting the power supply pin to the apparatus main body. Therefore, it is possible to suppress the fluctuation of the power supply voltage of the power supply line of the electronic circuit of the apparatus main body, and to prevent malfunction.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a hot-line insertion type electronic device of the present invention.

FIG. 2 is a configuration diagram of a hot-line insertion type electronic device according to the first embodiment of the present invention.

FIG. 3 is a time chart of FIG. 2;

FIG. 4 is a configuration diagram of a hot-line insertion type electronic device according to a second embodiment of the present invention.

FIG. 5 is a time chart of FIG. 4;

FIG. 6 is a configuration diagram of a conventional hot-line insertion type electronic device.

[Explanation of symbols]

 PCHG Precharge power supply pin Vcc power supply pin 10 Clock control means 12 Control means 14 Storage means 16 Gate circuit 18 Electronic circuit

Claims (5)

[Claims] 1. A power supply pin for precharging, a power supply pin, and an electronic circuit that operates based on a clock signal, wherein the power supply pin for precharging is inserted into the main unit earlier than the power supply pin. In a hot-line insertion type electronic device configured to be connected to a power supply and precharged, the clock signal is supplied to the electronic device until a predetermined time has elapsed from the time when the power supply pin is connected to the power supply. An electronic apparatus of a hot-line insertion type, comprising: a clock signal control means for controlling output to a circuit. 2. The clock signal control unit includes: a storage unit configured to store a control signal; and a control unit that controls the control signal to a first logic level until a predetermined time elapses from a time point when the power supply pin is connected to the power supply. And after the lapse of the predetermined time,
A control unit for setting the control signal to a second logic level and storing the control signal in the storage unit; and inputting the clock signal and the control signal. 2. The hot-line insertion method according to claim 1, further comprising: a gate circuit that outputs the clock signal to the electronic circuit as it is when the control signal is at the second logic level without outputting to the circuit. Electronic devices. 3. A power supply pin for precharge, a power supply pin, and an electronic circuit that operates in a low current consumption mode when an input signal is at a first logic level and operates in a normal current consumption mode when an input signal is at a second logic level. In a hot-line insertion type electronic device, the power supply pin for precharging is connected to the power supply of the main body device and precharged earlier than the power supply pin when inserted into the main body device. A mode control means for setting the input signal to the first logic level and outputting the signal to the electronic circuit until a predetermined time elapses from the time when the power supply is connected to the power supply. Electronic devices. 4. The mode control means includes: storage means for storing a control signal; and setting the control signal to a third logic level until a predetermined time has elapsed since the power supply pin was connected to the power supply. And after the lapse of the predetermined time,
A control means for setting the control signal to a fourth logic level and storing the control signal in the storage means; and if the control signal is a third logic level, the input signal is set to a first logic level and output to the electronic circuit; 4. The electronic apparatus according to claim 3, further comprising: a gate circuit that outputs the input signal to the electronic circuit as it is when the control signal is at a fourth logic level. 5. An electronic circuit divided into a precharge power supply pin, a power supply pin, and a plurality of block circuits, wherein a control signal input to each block circuit is inactive at a first logic level and active at a second logic level. In a hot-line insertion type electronic device configured such that the power supply pin for precharge is connected to the power supply of the main body device earlier than the power supply pin when inserted into the main body device, A live circuit insertion unit comprising block circuit control means for sequentially activating the control signal input to the block circuit from the time of connection to the power supply from the first logic level to the second logic level and activating the control signal. Electronic device.