JPH1028040A - Input circuit - Google Patents

Abstract

[PROBLEMS] To provide an input circuit capable of preventing a decrease in operation speed while reducing the influence of power supply noise. An input signal IN is input to a front stage 14 of a two-stage inverter circuit connected in series, and an input signal IN is output from a next-stage inverter circuit 2 to an internal circuit. A feedback circuit 15 which operates between the input / output terminals of the next-stage inverter circuit 2 based on the output signal OUT of the next-stage inverter circuit 2 and maintains the input / output level of the next-stage inverter circuit 2 at a complementary level. Is provided. Input signal I
At the time of the inverting operation of the preceding inverter circuit 14 based on the switching of N, a switch circuit 16 is provided which interrupts the supply of the power supply V1 to the feedback circuit 15 based on the control signal φ and stops the operation of the feedback circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit mounted on a semiconductor memory device or the like. 2. Description of the Related Art In recent years, semiconductor memory devices have been increasing in capacity and number of bits, and accordingly, power supply noise during simultaneous switching operation of output circuits has become extremely large. In addition, the power supply noise has caused a malfunction of the input circuit.
Therefore, in such a semiconductor memory device, there is a demand for an input circuit that reduces the influence of power supply noise and that prevents malfunction.

[0002]

2. Description of the Related Art An input circuit of a conventional semiconductor memory device includes:
As a measure for preventing malfunction due to power supply noise, a feedback circuit is provided as shown in FIG.

The input circuit comprises an input pad 1 of the semiconductor memory device and a CMOS comprising a P-channel MOS transistor Tr1 and an N-channel MOS transistor Tr2.
It comprises an inverter circuit, a next-stage inverter circuit 2, and a P-channel MOS transistor Tr3 forming a feedback circuit.

The pad 1 is connected to the transistor Tr
1 and Tr2. The source of the transistor Tr1 is connected to the power supply Vcc, and the source of the transistor Tr2 is connected to the ground GND. The drains of the transistors Tr1 and Tr2 are connected to each other and serve as a node N1.

[0005] The node N1 is connected to the input terminal of the inverter circuit 2, and the output terminal of the inverter circuit 2 is connected to the gate of the transistor Tr3.
The source of the transistor Tr3 is connected to the power supply Vcc, and the drain is connected to the input terminal of the inverter circuit 2 to form a feedback circuit.

In the input circuit configured as described above, when an H-level input signal IN is input to the gates of the transistors Tr1 and Tr2 via the pad 1, the transistor Tr1 is turned off and the transistor Tr1 is turned off. Tr2 is turned on, and the node N1 is connected to the ground GN.
D level, that is, L level. An L-level input signal IN is applied to the transistors Tr1 and Tr1 via the pad 1.
When input to the gate of Tr2, the transistor Tr
1 is turned on, the transistor Tr2 is turned off, and the node N1 is at the power supply Vcc level, ie, H level.
Level.

When the node N1 is at H level, L level is output from the inverter circuit 2, and the transistor Tr3 is turned on. At this time, the drain of the transistor Tr3 is at the power supply Vcc level, that is, H level.
And output to the inverter circuit 2.
The inverter circuit 2 outputs an L level signal to an internal circuit.

[0008] The above-mentioned input circuit comprises an input signal IN of L level.
Is input, even if many output circuits output H-level signals at the same time and the voltage of the power supply Vcc drops instantaneously, since the transistors Tr1 and Tr3 operate in parallel, the instant at the node N1 Voltage drop is suppressed.

Therefore, this input circuit can reduce the influence of power supply noise.

[0010]

However, in the conventional input circuit, since the transistor Tr3 is turned on when the input signal IN shifts from the L level to the H level, the drain current of the transistor Tr3 is reduced by the load of the transistor Tr2. As a result, the prompt transition of the node N1 to the L level is inhibited, and the sensitivity to the rising of the input signal IN decreases.

Therefore, the operating speed is reduced, and
A malfunction may occur in the internal circuit due to the decrease in the operation speed. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an input circuit capable of preventing an operation speed from decreasing while reducing the influence of the power supply noise.

[0012]

FIG. 1 is a diagram illustrating the principle of the present invention. That is, the input signal IN is input to the front stage 14 of the two-stage inverter circuit connected in series, and the input signal IN is output from the next-stage inverter circuit 2 to the internal circuit. The input / output terminal of the next-stage inverter circuit 2 operates based on the output signal OUT of the next-stage inverter circuit 2 to maintain the input / output level of the next-stage inverter circuit 2 at a complementary level. A feedback circuit 15 is provided. At the time of the inverting operation of the preceding inverter circuit 14 based on the switching of the input signal IN, the power supply V1 to the feedback circuit 15 is controlled based on the control signal φ.
And a switch circuit 16 for interrupting the supply of the feedback signal and stopping the operation of the feedback circuit 15.

According to a second aspect of the present invention, in the feedback circuit, a P-channel MOS transistor whose output signal from the next-stage inverter circuit is input to a gate and whose drain is connected to an input terminal of the next-stage inverter circuit The switch circuit is provided between the source of the P-channel MOS transistor and a high-potential-side power supply, and has a P-channel MOS transistor whose gate receives the control signal.

According to a third aspect of the present invention, in the feedback circuit, an output signal of the next-stage inverter circuit is input to a gate, and a drain thereof is connected to an input terminal of the next-stage inverter circuit. The switch circuit is provided between the source of the N-channel MOS transistor and the low-potential-side power supply, and has an N-channel MOS transistor whose gate receives the control signal.

According to a fourth aspect of the present invention, in the feedback circuit, a P-channel MOS transistor having an output signal of the next-stage inverter circuit input to a gate and a drain connected to an input terminal of the next-stage inverter circuit And an N-channel MOS transistor whose output signal is input to the gate of the next-stage inverter circuit and whose drain is connected to the input terminal of the next-stage inverter circuit. A P-channel MOS transistor interposed between the source of the P-channel MOS transistor and a high-potential-side power supply, the gate of which receives the control signal;
An N-channel MOS transistor is interposed between the source of the S transistor and the low-potential-side power supply and has the gate to which the control signal is input. The P-channel MOS transistor and the N-channel MOS transistor forming the switch circuit are turned on immediately after the switching of the input signal based on the control signal. (Operation) According to the first aspect of the present invention, the supply of power to the feedback circuit is interrupted by the operation of the switch circuit during the inversion operation of the preceding inverter circuit based on the switching of the input signal.

According to the second aspect of the present invention, when the input signal goes to L level, the P-channel MOS transistors forming the feedback circuit and the switch circuit are turned on. When the input signal switches, the P-channel MOS transistor forming the switch circuit is turned off.

According to the third aspect of the present invention, when the input signal becomes H level, the N-channel MOS transistors forming the feedback circuit and the switch circuit are turned on. When the input signal switches, the N-channel MOS transistor forming the switch circuit is turned off.

According to the fourth aspect of the invention, when the input signal is switched, each switch circuit is turned off and each feedback circuit is deactivated. Each switch circuit is turned on immediately after the switching of the input signal, the respective feedback circuits are activated, and the influence of noise included in the input signal is reduced.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 shows a first embodiment in which the present invention is embodied in an input circuit of a semiconductor memory device. The input signal IN input to the input pad 1 is a P-channel MOS
The signal is input to the gates of the transistor Tr1 and the N-channel MOS transistor Tr2.

The source of the transistor Tr1 is a power supply V
cc, and the source of the transistor Tr2 is connected to the ground GND. The transistor Tr
The drains of Tr1 and Tr2 are connected to each other to form a node N1.

The node N1 is connected to the input terminal of the inverter circuit 2, and the output terminal of the inverter circuit 2 is connected to the gate of the P-channel MOS transistor Tr3.

The source of the transistor Tr3 is connected to a power supply Vcc via a P-channel MOS transistor Tr4, and the drain of the transistor Tr3 is connected to the input terminal of the inverter circuit 2 to form a feedback circuit.

The output control circuit 3 controls the output circuit of the semiconductor memory device.
And the output signal φ0 of the activation pulse generation circuit 4
Is input to the gate of the transistor Tr4.

The output signal OUT of the inverter circuit 2 goes low, the output signal φ0 of the activation pulse generation circuit 4 goes low, and the transistors Tr3 and Tr
When both are turned on, the feedback circuit is activated.

The output signal OUT of the inverter circuit 2 is output to an internal circuit. FIG. 3 shows a specific configuration of the activation pulse generation circuit 4. The output control circuit 3 is activated based on an L level output control signal OE, and outputs complementary control signals Pu and Pd based on data RD output from an internal circuit. When the output control circuit 3 is inactive, the control signals Pu and Pd are both at the L level.

The control signal Pu is output to the gate of the output transistor Tr5 on the pull-up side.
d is output to the gate of the pull-down output transistor Tr6. The output transistors Tr5 and Tr6 are N
It is composed of a channel MOS transistor.

The connection point between the transistors Tr5 and Tr6 is connected to the output pad DQP. The control signal P
When u becomes H level and the control signal Pd becomes L level,
The transistor Tr5 is turned on and the transistor Tr6 is turned off, and the output data at the H level is output from the pad DQP. Also, the control signal Pu
Becomes low level and the control signal Pd becomes high level, the transistor Tr6 is turned on and the transistor Tr5 is turned off, and the L level output data is output from the pad DQP.

When the control signals Pu and Pd both become L level, the transistors Tr5 and Tr6 are both turned off, and the pad DQP becomes high impedance. The signals Pu and Pd are input to a NOR circuit 5 constituting the activation pulse generating circuit 4. The output signal of the NOR circuit 5 is input to one input terminal of the NOR circuit 6 and is input to the other input terminal via the three-stage inverter circuit 8. The connection point of the inverter circuit 8 is connected to the ground GND via the capacitor C, and the inverter circuit 8 and the capacitor C constitute a delay circuit.

Further, the output signal of the NOR circuit 6 is output via the inverter circuit 7 as the output signal φ0. When the control signals Pu and Pd are both at the L level and one of them is at the H level, the activation pulse generation circuit 4 configured as described above has the L level with a pulse width corresponding to the delay time of the delay circuit. Is output.

The sizes of the transistors Tr5 and Tr6 are set large in order to ensure a sufficient load driving capability. Therefore, as shown in FIG. 4, prior to output of output data DQ based on control signals Pu and Pd,
Output signal φ0 falls to L level.

The operation of the semiconductor memory device configured as described above will be described with reference to FIG. In this semiconductor memory device, when the control signals RAS, CAS, and OE go low and WE goes high, the read mode is set. In the read mode, cell information is read from the memory cell selected based on the address signal, and the control signals Pu and Pd output from the output control circuit 3 based on the cell information are complementary signals. Then, the output signal φ0 of the activation pulse generating circuit 4 goes low before the output data DQ is output, and the transistors Tr3 and Tr4 are turned on in the input circuit shown in FIG.

While the control signal RAS at the L level is being input to the pad 1 of the input circuit, H level output signals are simultaneously output from many output circuits, and the voltage level of the power supply Vcc is temporarily reduced. Node N
1 is supplied with current from the power supply Vcc via the transistor Tr1 and the transistors Tr3 and Tr4, so that the size of the transistor Tr1 is substantially increased, and the decrease in the node N1 accompanying the decrease in the power supply Vcc is reduced. Can be suppressed.

When the control signal RAS returns to the H level, the output signal .phi.0 of the activation pulse generating circuit 4 has already reached the H level after a lapse of a predetermined time.
The transistor Tr4 is off.

Therefore, the transistor Tr is connected to the node N1.
3, no current is supplied via Tr4. Therefore, the transistors Tr3 and Tr4 are connected to the transistor Tr2.
, The load on the node N1 is quickly changed to L.
Move to level.

That is, the operation speed with respect to the transition of the input signal IN from the L level to the H level can be improved, and malfunction of the internal circuit can be prevented. FIG. 5 is a circuit diagram of a specific example in which the configuration of the activation pulse generating circuit 4 and the configuration of the output control circuit 3 are different from each other. The activation pulse generating circuit 10 is connected to the output control circuit 9 at the preceding stage of the output control circuit 3.
It operates based on signals from

The output control circuit 9 includes the output control circuit 3
Output the data signal D. On the other hand, the output control circuit 9 outputs a Low-Z signal LZ to the output control circuit 3.

The signal LZ is supplied to the activation pulse generation circuit 10.
And input to the other input terminal via the three-stage inverter circuit 8.

The connection point of the inverter circuit 8 is connected to the ground GND via the capacitor C, and the inverter circuit 8 and the capacitor C constitute a delay circuit. An output signal of the NAND circuit 11 is output as the output signal φ0.

In the activation pulse generating circuit 10 thus configured, when the signal LZ changes from the L level to the H level, the output signal which changes to the L level with a pulse width corresponding to the delay time of the delay circuit. Outputs φ0.

Therefore, the same effects as those of the first embodiment can be obtained. (Second Embodiment) FIG. 6 shows an input circuit according to a second embodiment of the present invention. In this embodiment, the feedback circuit on the power supply Vcc side of the first embodiment is provided on the ground GND side, and the components denoted by the same reference numerals perform the same operation, and description thereof will be omitted. I do.

The drains of the transistors Tr1 and Tr2 are connected to each other and form a node N2. The node N2 is connected to the input terminal of the inverter circuit 2, and the output terminal of the inverter circuit 2 is connected to the gate of the N-channel MOS transistor Tr7.

The source of the transistor Tr7 is connected to the ground GND via an N-channel MOS transistor Tr8.
, And the drain of the transistor Tr7 is connected to the input terminal of the inverter circuit 2 to form a feedback circuit.

The activation pulse generation circuit 11 is controlled based on the output signal of an output control circuit (not shown), and the output signal φ1 of the activation pulse generation circuit 11 is input to the gate of the transistor Tr8.

The output signal OUT of the inverter circuit 2 goes high, the output signal φ1 of the activation pulse generation circuit 11 goes high, and the transistors Tr7, T
When both r8 are turned on, the feedback circuit is activated.

The activation pulse generation circuit 11 operates in the same manner as in the first embodiment when an H-level input signal IN is input to this input circuit, such as a control signal WE in a read mode. The output signal φ1 rises to the H level prior to the output of the output data DQ.

That is, even if the L level output data DQ is simultaneously output from many output circuits and the ground GND level temporarily rises, current flows from the node N2 to the ground GND via the transistor Tr2 and the transistors Tr7 and Tr8. Flows substantially, so that the transistor T
Since the size of r2 has been increased, the node N2 immediately transitions to the L level.

When the input signal IN changes from H level to L level, the activation pulse generation circuit 1
1 is at the L level after a certain period of time, and the transistor Tr8 is turned off.

Therefore, the transistors Tr7 and Tr8 do not become the load of the transistor Tr1, and the node N2
Quickly shifts to the H level. That is, the input signal IN
, The sensitivity of the operation speed to the transition from H level to L level can be improved, and malfunction of the internal circuit can be prevented. (Third Embodiment) FIG. 7 shows an input circuit according to a third embodiment of the present invention. The input circuit of this embodiment is provided with both the feedback circuits of the first embodiment and the second embodiment, and performs the same operation for components denoted by the same reference numerals. And the description is omitted.

In the input circuit of FIG. 7, it is assumed that the activation pulse generating circuit 12 outputs an output signal φ2 which is at the L level for a certain time as the input signal IN shifts to the L level. The activation pulse generating circuit 13 outputs the input waveform I
It is assumed that an output signal φ3 that becomes H level for a certain period of time is output as N shifts to H level.

The operation of the input circuit will be described with reference to FIG. When the load driving capability of the external circuit supplying the input signal is too high when the input signal IN shifts from the H level to the L level, the input signal INr actually input to the pad 1 has an overshoot followed by an undershoot. Va is generated. When the input signal IN shifts from the L level to the H level, an undershoot Vb occurs in the actually input signal INr following the overshoot.

Before the overshoot Va occurs, the feedback circuit activation time φ2 turns on the transistor Tr4 to activate the feedback circuit, thereby suppressing a change in the potential of the node N3 due to the undershoot Va. be able to.

Before the occurrence of the undershoot Vb, the feedback circuit activation time φ3 turns on the transistor Tr8 to activate the feedback circuit, thereby suppressing a change in the potential of the node N3 due to the undershoot Vb. be able to.

Therefore, in this input circuit, in addition to the functions and effects of the first and second embodiments, malfunctions due to the undershoots Va and Vb following the overshoot of the input waveform are prevented, and the input circuit is based on the ideal input signal IN. The operation is equivalent to the operation.

The present invention is not limited to the above embodiment, but may be implemented as follows. (1) The activation pulse generation circuits 4 and 9 output the output signal DQ
Is output, any configuration may be used as long as the transistor Tr4 can be turned on.

(2) The activation pulse generation circuit 11 may have any configuration as long as it can turn on the transistor Tr8 when the output signal DQ is output.

(3) The activation pulse generation circuits 12, 1
No. 3 may have any configuration as long as it can output the output signals φ2 and φ3 before the occurrence of the undershoots Va and Vb after the transition of the input signal IN.

[0057]

As described in detail above, the present invention can provide an input circuit capable of preventing a decrease in operation speed while reducing the influence of power supply noise.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is a circuit diagram showing a specific configuration of an activation pulse generation circuit.

FIG. 4 is a timing waveform chart showing the operation of the first embodiment.

FIG. 5 is a circuit diagram showing another example of the activation pulse generation circuit.

FIG. 6 is a circuit diagram showing a second embodiment.

FIG. 7 is a circuit diagram showing a third embodiment.

FIG. 8 is a timing waveform chart showing the operation of the third embodiment.

FIG. 9 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 Secondary inverter circuit 14 Previous inverter circuit 15 Feedback circuit 16 Switch circuit IN Input signal OUT Output signal V1 Power supply φ Control signal

Claims (4)

[Claims] An input signal is input to a preceding stage of a two-stage inverter circuit connected in series, an input signal is output from a next-stage inverter circuit to an internal circuit, and an input / output terminal of the next-stage inverter circuit is provided. An input circuit including a feedback circuit that operates based on an output signal of the next-stage inverter circuit to maintain an input / output level of the next-stage inverter circuit at a complementary level. A switching circuit that shuts off the supply of power to the feedback circuit based on a control signal and stops the operation of the feedback circuit during the inversion operation of the preceding inverter circuit based on the switching of Input circuit. 2. The feedback circuit includes a P-channel MOS transistor having an output signal of the next-stage inverter circuit input to a gate and a drain connected to an input terminal of the next-stage inverter circuit. ,
2. The switch circuit according to claim 1, wherein the switch circuit is comprised of a P-channel MOS transistor interposed between a source of the P-channel MOS transistor and a high-potential-side power supply, the gate of which receives the control signal. Input circuit as described. 3. The feedback circuit is configured by an N-channel MOS transistor having an output signal of the next-stage inverter circuit input to a gate and a drain connected to an input terminal of the next-stage inverter circuit. ,
2. The switch circuit according to claim 1, wherein the switch circuit is constituted by an N-channel MOS transistor interposed between a source of the N-channel MOS transistor and a low-potential-side power supply and having the gate to which the control signal is input. Input circuit as described. 4. The P-channel MOS transistor having a gate to which an output signal of the next-stage inverter circuit is input and a drain connected to an input terminal of the next-stage inverter circuit, An output signal of the next-stage inverter circuit is input to a gate, and a drain of the N-channel MOS transistor is connected to an input terminal of the next-stage inverter circuit. A P-channel MOS interposed between the source of the transistor and the high-potential-side power supply, the gate of which receives the control signal
A P-channel MOS transistor interposed between a transistor and a source of the N-channel MOS transistor and a low-potential-side power supply, the gate of which receives the control signal;
2. The input circuit according to claim 1, wherein the OS transistor and the N-channel MOS transistor are turned on immediately after the switching of the input signal based on the control signal.