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JPH1027869A - Circuit board for semiconductor device and composite semiconductor device provided therewith - Google Patents

Circuit board for semiconductor device and composite semiconductor device provided therewith

Info

Publication number
JPH1027869A
JPH1027869A JP8197092A JP19709296A JPH1027869A JP H1027869 A JPH1027869 A JP H1027869A JP 8197092 A JP8197092 A JP 8197092A JP 19709296 A JP19709296 A JP 19709296A JP H1027869 A JPH1027869 A JP H1027869A
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
metal plate
circuit pattern
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8197092A
Other languages
Japanese (ja)
Inventor
Eigo Fukuda
永吾 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nihon Inter Electronics Corp
Original Assignee
Nihon Inter Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nihon Inter Electronics Corp filed Critical Nihon Inter Electronics Corp
Priority to JP8197092A priority Critical patent/JPH1027869A/en
Publication of JPH1027869A publication Critical patent/JPH1027869A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To lessen a circuit board and a semiconductor device in size by a method wherein a signal circuit pattern is set to be 1.0mm or below in minimum width. SOLUTION: A semiconductor device circuit board 3 is equipped with an aluminum nitride board 31 possessed of a conductor pattern 4 of metal plate and a signal circuit pattern 60 of metallized layer mixedly bonded to its one primary surface and a metal plate bonded to all its other primary surface. Or, a composite semiconductor device 1 is equipped with an aluminum nitride board 31 possessed of a conductor pattern 4 of metal plate and a signal circuit pattern 60 of metallized layer mixedly bonded to its one primary surface, where semiconductor chips 5 are mounted on the conductor pattern 4 of metal plate, and the signal circuit pattern 60 of metallized layer is made to serve as the signal circuit wiring of a semiconductor chip 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、窒化アルミニウム
基板を使用して小型化した回路基板と、この回路基板を
使用した複合半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a miniaturized circuit board using an aluminum nitride substrate and a composite semiconductor device using the circuit board.

【0002】[0002]

【従来の技術】この種の複合半導体装置の概略構造を図
2に示す。図において、1は複合半導体装置の全体を示
している。2は放熱板であり、この放熱板2上には半導
体装置用回路基板3が搭載・固着されている。
2. Description of the Related Art FIG. 2 shows a schematic structure of a composite semiconductor device of this kind. In the figure, reference numeral 1 denotes the entire composite semiconductor device. Reference numeral 2 denotes a heat sink on which a circuit board 3 for a semiconductor device is mounted and fixed.

【0003】上記回路基板3上には、導体パターン4が
形成され、この導体パターン4上に半導体チップ5が搭
載・固着され、この半導体チップ5と信号回路パターン
6とがボンディングワイヤ7により接続されている。ま
た、導体パターン4の所定の位置には複数の外部導出端
子8の下端が固着され、その他端は絶縁ケース9の開口
部を閉塞する蓋体10から外部に導出されている。な
お、絶縁ケース9の下端は放熱板2の外周に固定されて
いる。
[0003] A conductor pattern 4 is formed on the circuit board 3, a semiconductor chip 5 is mounted and fixed on the conductor pattern 4, and the semiconductor chip 5 and the signal circuit pattern 6 are connected by bonding wires 7. ing. The lower ends of the plurality of external lead-out terminals 8 are fixed to predetermined positions of the conductor pattern 4, and the other ends are led out from a lid 10 that closes an opening of the insulating case 9. The lower end of the insulating case 9 is fixed to the outer periphery of the heat sink 2.

【0004】次に、図3に半導体装置用回路基板3の平
面図を示し、その詳細を説明する。該回路基板3は、約
0.6mm厚の窒化アルミニウム基板31を有し、この
窒化アルミニウム基板31の裏面側にはその全面に、例
えば0.3mm厚の銅板等の金属板が固着されている。
上記回路基板3の表面側には、上記同様に、例えば0.
3mm厚の銅板等からなる金属板により導体パターン4
が形成されている。この導体パターン4中の斜線の施し
た部分は、外部導出端子固着部32である。
Next, FIG. 3 shows a plan view of the circuit board 3 for a semiconductor device, and details thereof will be described. The circuit board 3 has an aluminum nitride substrate 31 having a thickness of about 0.6 mm, and a metal plate such as a copper plate having a thickness of 0.3 mm is fixed on the entire back surface of the aluminum nitride substrate 31. .
On the front side of the circuit board 3, for example,
Conductor pattern 4 made of a metal plate such as a 3 mm thick copper plate
Are formed. The hatched portion in the conductor pattern 4 is the external lead terminal fixing portion 32.

【0005】上記窒化アルミニウム基板31の中央部、
すなわち略コ字型に形成された導体パターン4の凹部内
に一端が細く伸びる信号回路パターン6が形成されてい
る。この信号回路パターン6も例えば0.3mm厚の銅
板等からなる金属板から形成され、その幅Wは約1.0
mm程度である。これは、該幅Wが1.0mm以下にな
ると銅板等の金属板のプレス加工が難しくなるためであ
る。なお、信号回路パターン6中の斜線を施した部分
は、信号端子固着部33である。
A central portion of the aluminum nitride substrate 31,
That is, the signal circuit pattern 6 whose one end extends thinly is formed in the concave portion of the conductor pattern 4 formed in a substantially U-shape. This signal circuit pattern 6 is also formed of a metal plate made of, for example, a copper plate having a thickness of 0.3 mm, and has a width W of about 1.0 mm.
mm. This is because when the width W is less than 1.0 mm, it is difficult to press a metal plate such as a copper plate. The hatched portion in the signal circuit pattern 6 is the signal terminal fixing portion 33.

【0006】[0006]

【発明が解決しようとする課題】従来の信号回路パター
ン6は、上記のように導体パターン4と同様に銅板等か
らなる金属板を使用しているために、その加工の困難性
から最小幅でもW=約1.0mm程度にしなければなら
ない。一方、装置の小型化のためには回路基板3自体の
小型化も当然要求されるが、上記のような加工上の制約
があるため、結果的に十分装置の小型化に寄与できない
という解決すべき課題があった。
As described above, the conventional signal circuit pattern 6 uses a metal plate made of a copper plate or the like as in the case of the conductor pattern 4 as described above. W must be about 1.0 mm. On the other hand, in order to reduce the size of the device, the size of the circuit board 3 itself must be reduced. However, due to the above-described processing restrictions, it is impossible to sufficiently reduce the size of the device. There were issues to be addressed.

【0007】[0007]

【発明の目的】本発明は、上記のような課題を解決する
ためになされたもので、信号回路パターンの最小幅を
1.0mm以下とすることができ、回路基板の小型化を
実現可能として、以て装置自体の小型化に十分寄与し得
る半導体装置用回路基板及びそれを使用した複合半導体
装置を提供することを目的とするものである。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and can reduce the minimum width of a signal circuit pattern to 1.0 mm or less, thereby realizing a miniaturization of a circuit board. Accordingly, it is an object of the present invention to provide a circuit board for a semiconductor device which can sufficiently contribute to miniaturization of the device itself, and a composite semiconductor device using the same.

【0008】[0008]

【課題を解決するための手段】第1の発明の半導体装置
用回路基板は、窒化アルミニウム基板の一方の主面には
金属板を固着した第1の回路パターンと、メタライズ層
からなる第2の回路パターンとが混在し、他方の主面は
全面に金属板が固着されたことを特徴とするものであ
る。第2の発明の複合半導体装置は、窒化アルミニウム
基板の一方の主面には金属板を固着した第1回路パター
ンと、メタライズ層からなる第2の回路パターンとが混
在し、該金属板からなる第1の回路パターン上には半導
体チップを搭載し、メタライズ層からなる第2の回路パ
ターンは、前記半導体チップの信号回路の配線として使
用したことを特徴とするものである。
According to a first aspect of the present invention, there is provided a circuit board for a semiconductor device, comprising: a first circuit pattern having a metal plate fixed to one main surface of an aluminum nitride substrate; The circuit pattern is mixed, and a metal plate is fixed on the entire other main surface. A composite semiconductor device according to a second aspect of the present invention includes a first circuit pattern in which a metal plate is fixed to one main surface of an aluminum nitride substrate, and a second circuit pattern formed of a metallized layer, which is formed of the metal plate. A semiconductor chip is mounted on the first circuit pattern, and a second circuit pattern formed of a metallization layer is used as a wiring of a signal circuit of the semiconductor chip.

【0009】[0009]

【発明の実施の形態】以下に、本発明の実施の形態を図
1を参照して説明する。まず、本発明は、装置自体の小
型化の要請からそれに使用される半導体装置用回路基板
自体についても当然小型化が要求されるので、これに応
えるべくなされたものである。すなわち、信号回路パタ
ーンに流れる電流は小さいことに着目し、あえて加工の
困難性のある金属板を使用しなくても良いのではないか
という考えに基づいている。付言すれば、金属板を使用
することなく信号回路パターンの最小幅Wを1.0mm
以下にできれば、回路基板全体の外形も小さくすること
ができ、最終的に装置の小型化に寄与できるということ
である。
Embodiments of the present invention will be described below with reference to FIG. First, the present invention has been made in response to the demand for miniaturization of the device itself, which naturally also requires miniaturization of the circuit board for semiconductor device used therein. In other words, focusing on the fact that the current flowing in the signal circuit pattern is small, it is based on the idea that it is not necessary to use a metal plate that is difficult to process. In addition, the minimum width W of the signal circuit pattern is set to 1.0 mm without using a metal plate.
If it can be made below, the outer shape of the entire circuit board can be reduced, which can ultimately contribute to miniaturization of the device.

【0010】そこで、半導体装置用回路基板3中の第2
の回路パターンである信号回路パターン60について
は、従来のように銅板等からなる金属板を使用すること
なく、メタライズ層によって形成することを特徴とする
ものである。第1の回路パターンである他の導体パター
ン4の部分については、従来通り銅板等からなる金属板
を使用して形成する。以下に、本発明の一実施例を示
す。
Therefore, the second semiconductor device circuit board 3
The signal circuit pattern 60, which is a circuit pattern of the above, is characterized by being formed by a metallized layer without using a metal plate made of a copper plate or the like as in the related art. The portion of the other conductor pattern 4 that is the first circuit pattern is formed using a metal plate made of a copper plate or the like as in the related art. An embodiment of the present invention will be described below.

【0011】[0011]

【実施例】図1において、窒化アルミニウム基板31の
表面側に、信号回路パターン60として約30μm厚の
メタライズ層を公知の方法で形成する。一方、他の導体
パターン4の部分は、従来通り、例えば0.3mm厚の
銅板等からなる金属板を用いて形成する。以上により信
号回路パターン60はメタライズ層によって形成されて
いるので、従来のように金属板の加工の困難性に左右さ
れることなく、最小幅Wを容易に1.0mm以下とする
ことができる。このため、導体パターン4の凹部4aの
寸法W1も小さくすることができ、最終的には半導体装
置用回路基板3自体の外形寸法W2も小さくすることが
可能となる。なお、上記の信号回路パターン60のメタ
ライズ層の形成は、導体パターン4の金属板を固着する
ためのメタライズ層の形成と同時に行うことができるた
め、特に製造工程を増加させることもない。
1, a metallized layer having a thickness of about 30 .mu.m is formed as a signal circuit pattern 60 on the surface of an aluminum nitride substrate 31 by a known method. On the other hand, the other portions of the conductor pattern 4 are formed using a metal plate made of, for example, a copper plate having a thickness of 0.3 mm as in the related art. As described above, since the signal circuit pattern 60 is formed of the metallized layer, the minimum width W can be easily reduced to 1.0 mm or less without being affected by the difficulty of processing the metal plate as in the related art. For this reason, the dimension W1 of the concave portion 4a of the conductor pattern 4 can be reduced, and finally, the outer dimension W2 of the semiconductor device circuit board 3 itself can also be reduced. The formation of the metallized layer of the signal circuit pattern 60 can be performed simultaneously with the formation of the metallized layer for fixing the metal plate of the conductor pattern 4, so that the number of manufacturing steps is not particularly increased.

【0012】上記の結果、小型化された半導体装置用回
路基板3を使用して、図2に示したような複合半導体装
置を組み立てる場合、該回路基板3を多数必要とするも
のほど装置全体の小型化への寄与率が大きくなり、その
効果が絶大となる。
As a result, when assembling the composite semiconductor device as shown in FIG. 2 using the miniaturized circuit board 3 for a semiconductor device, the larger the number of the circuit boards 3 is, the more the overall device becomes. The contribution rate to miniaturization is large, and the effect is enormous.

【0013】[0013]

【発明の効果】以上のように、本発明の半導体装置回路
基板は、メタライズ層によって第2の回路パターンの部
分を形成するようにしたので、金属板の加工の困難性に
起因する最小幅の制約が緩和され、従来に比較して相対
的に小型化した回路基板を製作することができ、コスト
の低減に寄与し得る。また、上記回路基板を使用した複
合半導体装置においても装置全体の小型化が実現できる
などの利点が生じる。
As described above, in the semiconductor device circuit board of the present invention, the second circuit pattern portion is formed by the metallized layer, so that the minimum width due to the difficulty in processing the metal plate is obtained. Restrictions are relaxed, and a circuit board that is relatively small compared to the related art can be manufactured, which can contribute to cost reduction. Further, even in a composite semiconductor device using the above-described circuit board, there is an advantage that the size of the entire device can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置用回路基板の平面図であ
る。
FIG. 1 is a plan view of a circuit board for a semiconductor device of the present invention.

【図2】従来及び本発明の半導体装置用回路基板を使用
して組み立てた複合半導体装置の概略構造を示す断面図
である。
FIG. 2 is a cross-sectional view showing a schematic structure of a composite semiconductor device assembled using conventional and semiconductor device circuit boards.

【図3】従来の半導体装置用回路基板の平面図である。FIG. 3 is a plan view of a conventional circuit board for a semiconductor device.

【符号の説明】[Explanation of symbols]

1 複合半導体装置 2 放熱板 3 半導体装置用回路基板 4 導体パターン 5 半導体チップ 6,60 信号回路パターン 31 窒化アルミニウム基板 DESCRIPTION OF SYMBOLS 1 Composite semiconductor device 2 Heat sink 3 Circuit board for semiconductor devices 4 Conductor pattern 5 Semiconductor chip 6,60 Signal circuit pattern 31 Aluminum nitride substrate

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 窒化アルミニウム基板の一方の主面には
金属板を固着した第1の回路パターンと、メタライズ層
からなる第2の回路パターンとが混在し、他方の主面は
全面に金属板が固着されたことを特徴とする半導体装置
用回路基板。
1. A first circuit pattern having a metal plate fixed thereto and a second circuit pattern comprising a metallized layer are mixed on one main surface of the aluminum nitride substrate, and the other main surface is formed on the entire surface of the metal plate. A circuit board for a semiconductor device, wherein the circuit board is fixed.
【請求項2】 前記第1の回路パターン間に、前記第2
の回路パターンの一部が入り組んで配置されていること
を特徴とする請求項1に記載の半導体装置用回路基板。
2. The method according to claim 1, wherein the second circuit pattern is provided between the first circuit patterns.
2. The circuit board for a semiconductor device according to claim 1, wherein a part of the circuit pattern is arranged in a complicated manner.
【請求項3】 窒化アルミニウム基板の一方の主面には
金属板を固着した第1回路パターンと、メタライズ層か
らなる第2の回路パターンとが混在し、該金属板からな
る第1の回路パターン上には半導体チップを搭載し、メ
タライズ層からなる第2の回路パターンは、前記半導体
チップの信号回路の配線として使用したことを特徴とす
る複合半導体装置。
3. A first circuit pattern comprising a metal plate and a second circuit pattern comprising a metallized layer mixed on one main surface of an aluminum nitride substrate. A composite semiconductor device having a semiconductor chip mounted thereon and a second circuit pattern formed of a metallization layer used as a wiring of a signal circuit of the semiconductor chip.
JP8197092A 1996-07-08 1996-07-08 Circuit board for semiconductor device and composite semiconductor device provided therewith Pending JPH1027869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8197092A JPH1027869A (en) 1996-07-08 1996-07-08 Circuit board for semiconductor device and composite semiconductor device provided therewith

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8197092A JPH1027869A (en) 1996-07-08 1996-07-08 Circuit board for semiconductor device and composite semiconductor device provided therewith

Publications (1)

Publication Number Publication Date
JPH1027869A true JPH1027869A (en) 1998-01-27

Family

ID=16368601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8197092A Pending JPH1027869A (en) 1996-07-08 1996-07-08 Circuit board for semiconductor device and composite semiconductor device provided therewith

Country Status (1)

Country Link
JP (1) JPH1027869A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100726922B1 (en) * 2000-12-19 2007-06-14 히다찌 케이블 리미티드 Manufacturing method of LGA type semiconductor device wiring board, LGA type semiconductor device and LGA type semiconductor device wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100726922B1 (en) * 2000-12-19 2007-06-14 히다찌 케이블 리미티드 Manufacturing method of LGA type semiconductor device wiring board, LGA type semiconductor device and LGA type semiconductor device wiring board

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