JPH10275464A - Synchronous dynamic semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous dynamic semiconductor memory in which plotting can be performed without being conscious of the time required for pre-charge and a plotting performance is improved. SOLUTION: A command and data externally inputted is temporarily accumulated in a command delay FIFO 103 and a data delay FIFO 102, a command pre-fetch control section 101 discriminates whether a command and data are accumulated in the command delay FIFO 103 and the data delay FIFO 102 or not based on a signal outputted from a mode register 107. And a command and data being not accumulated are outputted to a logic circuit section 108, when a command and data is started to accumulate temporarily, a 'Busy' signal 116 is outputted to the outside, and a CS control section 104 controls a CS signal based on a signal from the command pre-fetch control section 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronous dynamic semiconductor memory device capable of high-speed reading / writing, and more particularly to a synchronous dynamic semiconductor memory device capable of performing writing without considering a precharge period.

[0002]

2. Description of the Related Art Conventionally, in order to display an image on an image display device used in a personal computer or the like, a dynamic semiconductor memory device is widely used as a semiconductor memory device for storing image data representing an image to be displayed. Have been.

However, due to its characteristics, the dynamic semiconductor memory device requires an operation of accessing all different memory addresses at least once within a certain time, that is, a refresh operation. Further, in the case where access to completely different address spaces, that is, random access is continuously performed, a setup time for a next access called a precharge time is required every time one access is completed. Since the refresh cycle and the precharge time for repeating the refresh operation lower the rewriting performance of the pixel data in the image system, various methods for constructing the system without considering them are being studied.

In order to prevent a decrease in the rewriting performance of pixel data in an image system due to the above-described refresh cycle and precharge time, Japanese Patent Laid-Open No. 1-16 / 1994
Japanese Patent Application Publication No. 1454 discloses a dynamic semiconductor memory device capable of performing an access operation without being conscious of a refresh cycle on an image system.

In the invention described in Japanese Patent Application Laid-Open No. 1-161454, a FIFO memory (First In) located between a memory cell array and an external memory controller is disclosed.
(First Out memory), a certain partial area on the memory cell is accessed in a predetermined order regardless of the refresh operation. Here, access to the memory is based on block access, and in a read cycle, a plurality of words are continuously read from a memory cell array and stored in a FIFO memory. If you transfer the necessary data to the FIFO memory,
Since the memory cell array is in an idle state, refreshing can be freely performed. Regarding the write operation, even if the memory cell array is being refreshed, the FIFO
Since the write data can be temporarily stored in the O memory, there is no need to be conscious of refreshing the memory from the external memory controller.

On the other hand, there is a bank interleaving method as a technical method that does not consider the precharge time, which is another characteristic of the dynamic semiconductor memory device. This means that the memory array in the system is
This is a method in which one or more blocks (banks) are divided, and one bank accesses another bank during a precharge period, and is used not only in image systems but also in various other systems.

There is a synchronous dynamic semiconductor memory device which realizes the bank interleaving method inside the semiconductor memory device. The synchronous dynamic semiconductor memory device has two banks inside, and one bank can access the other bank during precharge. A conventional dynamic semiconductor memory device operates in synchronization with an operation control signal such as a RAS signal and a CAS signal separately from the operation clock of the system. However, the synchronous dynamic semiconductor memory device operates in synchronization with the operation clock of the system. Synchronous operation is possible.

Therefore, device activation and address fetching based on the level of the RAS signal and CAS signal, and designation of write / read operation based on the level of the WE signal and OE signal, which are performed in the conventional dynamic semiconductor memory device, are performed. Unlike the method, in the synchronous dynamic semiconductor memory device, the CS signal, the RAS signal, and the CAS signal are used.
A command method is adopted in which the meaning of the operation is defined by a combination of the logic of the signal and the WE signal, that is, the command is defined, and the command is input in synchronization with the clock signal to execute the read / write operation.

For example, (CS, RAS, CAS, WE)
The combination of = (0, 0, 1, 1) means a row active command which is a falling edge of the RAS signal of the conventional dynamic semiconductor memory device, that is, a row address fetch and device activation. Also, (CS, R
AS, CAS, WE) = (0, 1, 0, 0)
Command, (CS, RAS, CAS, WE) =
(0, 1, 0, 1) means a read command, which means fetching of a column address of a conventional dynamic semiconductor memory device and determination of a read / write operation.

Further, (CS, RAS, CAS, WE)
= (0, 0, 1, 0) is defined as a precharge command, and the rising of the conventional RAS signal requires a precharge time thereafter. As can be understood from the logic of these commands, all commands are accepted only when the CS signal is "0", that is, at the low level. Regarding the designation of the bank inside the semiconductor memory device, it is designated by the most significant address signal among the addresses input in accordance with the above command. These commands are input in synchronization with a clock signal, and the use of a clock signal of the system as the clock signal facilitates synchronization with the outside of the semiconductor memory device.

On the other hand, in a synchronous dynamic type semiconductor memory device, the definition of CAS latency is used to define data after n clocks from a read command depending on the frequency of an input clock signal. , Which is expressed as CAS latency n. The value of n can be set by a mode register built in the synchronous dynamic semiconductor memory device. Further, the CAS latency n defines not only the delay of the read data as described above, but also the interval from each command to each command. For example, if n = 2, the interval from the active command to the read command is defined. Becomes 2.

In a synchronous dynamic semiconductor memory device, m words of burst access can be executed after a read or write command is input. The burst access length m can be set by a mode register. As with the read and write commands, a mode register setting command is prepared for setting in the mode register, and the operation mode can be set freely within a range specified by the command.

On the other hand, in an image system, a general CRT is used.
The scan line map method is known as an address management method at the time of displaying a screen in. In this scan line map method, the scan lines of the CRT and the row addresses of the dynamic semiconductor memory device are made to correspond one-to-one or one-to-many, and as many row addresses of the dynamic semiconductor memory device as possible on the same scan line. This is a way to arrange data.

However, according to this method, when pixel data is rewritten, there is a difference in operation characteristics between rewriting in the scan line direction and rewriting in the direction perpendicular to the scan line. That is, rewriting in the scan line direction can be performed at a high speed by an access method for continuously accessing data on the same row address in a high-speed page mode access of a dynamic semiconductor memory device or a burst access mode of a synchronous dynamic semiconductor memory device. However, if the scan line is rewritten in the vertical direction, the access method for continuously accessing data on the same row address by high-speed page mode access or burst access cannot be used. Access.

In the case of this random access, a word line precharge time unique to a dynamic semiconductor memory device or a synchronous dynamic semiconductor memory device is required in each cycle, so that the pixel data rewriting performance ( Hereinafter, the drawing performance is also significantly reduced as compared with the rewriting performance in the scan line direction.

As a method for preventing the deterioration of the drawing performance, there is a tile map technique as one of the address management methods in screen display. In this tile map technique, the inside of a CRT screen is divided into squares of X lines × Y dots, and address management is performed so that data in one tile is constituted by data in a set of row addresses of a semiconductor memory device. In the same tile, an access method of continuously accessing data on the same row address by high-speed page mode access or burst access can be used for drawing in any of the vertical, horizontal, and diagonal directions, Therefore, uniform and high-speed drawing can be realized in any direction.

By consciously allocating address areas of different banks to adjacent tiles, it is possible to make apparent the precharge time of the dynamic semiconductor memory device with respect to access that crosses the boundary between tiles. This method is suitable for a synchronous dynamic type semiconductor memory device having two banks inside.

[0018]

However, in the case of drawing in a rectangular area of an image 901 which straddles a plurality of tiles 1 to 4 as shown in FIG. 9, for example, the continuous access length on each row address of each bank is limited. On the other hand, access on the tile boundary is based on random access.

Therefore, as described above, when drawing in a rectangular area of the image 901 as shown in FIG. 9 using the synchronous dynamic semiconductor memory device in the image system, even if the tile map method is used, the scan is performed. There is a problem that the write burst length when drawing in the line direction differs in each write cycle, and drawing cannot be performed by uniform burst access, and random access must be performed. In addition, since the access ratio to the same bank in the synchronous dynamic semiconductor memory device is increased, the precharge time inherent in the dynamic semiconductor memory device cannot be neglected, and the drawing performance deteriorates significantly.

In order to solve the above problems, Japanese Patent Laid-Open Publication No. 1-1
As disclosed in Japanese Patent No. 61454, FI
There is a method in which an FO memory is internally provided in a semiconductor memory device, and write data at the time of random access is temporarily stored, and an external write operation is performed in a shortest time even when a write operation or a precharge operation is performed in the memory. Proposed.

However, in a simple FIFO memory, it takes 50 ns to several hundred ns until the first written data can be read, and it is not possible to read immediately after the temporarily stored data or command is stored. Even if the operation inside the apparatus is to be minimized, there is a problem that a weight must be inserted more than necessary. In addition, since the delay length of commands and data reflected inside is completely different due to the difference in CAS latency inherent in the synchronous dynamic type semiconductor memory device, it is difficult to temporarily store commands and data using a simple FIFO memory. Is a problem.

The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a synchronous dynamic semiconductor memory device which enables writing without being aware of the time required for precharging and which can improve writing performance.

[0023]

According to the first aspect of the present invention,
A command delay FIFO for temporarily storing a command input from the outside, a data delay FIFO for temporarily storing data input from the outside, and the command delay FIFO based on a signal output from a mode register.
It is determined whether or not to store a command in the FIFO and whether or not to store data in the data delay FIFO, and outputs a command and data not to be stored to the logic circuit unit, and temporarily stores the command and data. A command prefetch control unit that outputs a Busy signal to the outside when started, and a CS control unit that controls an internal CS signal based on a signal output from the command prefetch control unit.

According to a second aspect of the present invention, in the first aspect, the command delay FIFO has a plurality of D flip-flops for storing commands and a shift register for selecting the stored commands. It is characterized by.

According to a third aspect of the present invention, in the first or second aspect of the invention, the command prefetch control unit sets an initial value of a counter according to CAS latency based on a signal output from a mode register. A hexadecimal counter, a first D flip-flop for outputting an Int pref signal, a second D flip-flop for outputting a Busy signal, and loading the count value output from the hexadecimal counter, and decrementing to an offset value And a decrement counter.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a synchronous dynamic semiconductor memory device according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a synchronous dynamic semiconductor memory device according to the present invention.

As shown in FIG. 1, the synchronous dynamic semiconductor memory device according to the present embodiment has a CL
K signal 123, CS signal 117, RAS signal 118, C
AS signal 119, WE signal 120, bank address 12
1 and the timing generation circuit 1 to which the address 122 is input
09, a mode register 107 to which an address 122 and an output signal from the command prefetch control unit 101 are input, and a C that outputs a CS signal to the logic circuit 108
The command prefetch control unit 1 which receives the S control unit 104, the output signal from the mode register 107, the pref signal 115, and the output signal from the data input buffer 105, and outputs the Busy signal 116 to the outside
01, a data output buffer 106 to which an output signal from the logic circuit 108 is input, and a data input buffer 10 to which a signal output from the external data bus 104 is input and which outputs a signal to the command prefetch control unit 101
5, a command delay FIFO 103 to which a signal is input via the data bus 113, a data delay FIFO 102 to which a signal is input via the data bus 113, and C
The signal output from the S control unit 104 and the data bus 11 from the command prefetch control unit 101
2, a command delay FIFO
103 and data delay FIFO output from 103
Circuit 108 to which the signal output from the logic circuit 108 is input, and the bank A110 to which the signal output from the timing generation circuit 109 and the signal output from the logic circuit 108 are input
And a bank B to which a signal output from the timing generation circuit 109 and a signal output from the logic circuit 108 are input.
111.

The synchronous dynamic type semiconductor memory device shown in FIG.
3 and has two memory banks A110 and B111 in the semiconductor memory device. The operation method is the command format described above, and the device is activated (active) and read by the logic of the CS signal 117, the RAS signal 118, the CAS signal 119, and the WE signal 120 externally supplied in synchronization with the CLK signal 123. / Write operation and precharge operation are instructed. The bank address 121 is input to the timing generation circuit 109 at the same time as the above-mentioned command in order to distinguish whether the input command is for the memory bank A110 or the memory bank B111.

The mode register 107 determines the CAS latency and the burst length. Like the other commands, the CS register 117, the RAS signal 118, and the CAS signal 119
When the mode register setting command defined by the logic of the WE signal 120 is input, these values are determined based on the logic given to the address signal 122. In the present embodiment, the CAS latency is expressed by a combination of data input as (A6, A5, A4), as shown in FIG. 2 described later, and (0, 0, 1) indicates CAS latency 1, (0, 1). , 0) means CAS latency 2 and (0, 1, 1) means CAS latency 3. The burst length is set to 1 during a write operation, especially from the high frequency of random access during drawing.

Command prefetch control unit 10
1 is a signal A (not shown) from the mode register 107.
6, A5 and A4, and a pref signal 115 from the outside, and the command and write data from the outside are transferred to the command delay FIFO 103 and the data delay FIFO 10
Then, it is determined whether or not to temporarily store the data, and when the data is stored, the command and the write data are output to the command delay FIFO 103 and the data delay FIFO 102 via the command bus and the data bus 113. If the data is not accumulated, the command and the write data are output to the logic circuit unit 108 via the command bus and the data bus 112.

The above-mentioned distribution of the command and write data to each FIFO and the logic circuit 108 is performed by pr
This is performed based on the ef signal 115. In other words, when the pref signal 115 input to the command prefetch control unit 101 goes low when a command is input from the outside, the command delay F
Commands and write data are stored in the FIFO 103 and the data delay FIFO 102. In the present embodiment, a maximum of 15 commands and data can be stored during the period in which the pref signal 115 is at the low level. pr
When the ef signal 115 is at a high level, all commands and data are input directly to the logic circuit unit 108 via the data bus 112.

As soon as the pref signal 115 goes low, the command prefetch control unit 101 outputs a high-level Busy signal 116. This high-level Busy signal 116 is maintained at a high level until the write operation in the semiconductor memory device ends, and is output as a normal low level after the write operation ends.

Next, FIG. 2 shows an internal circuit of the command prefetch control unit 101. This internal circuit is Bu
Control of sy signal 116 and Int pr as internal signal
3 shows a circuit for controlling the ef signal 209. The main components of this circuit are a hexadecimal counter 201 and a decrement counter 202. Hexadecimal counter 201
Is the A6 signal 20 from the mode register 107 shown in FIG.
6, upon receiving the A5 signal 207 and the A4 signal 208, sets the initial value of the counter in accordance with the CAS latency.

In this embodiment, as the output of the hexadecimal counter 201, the initial value is 2 when the CAS latency is 1, and the initial value is 1 when the CAS latency is 2 and the CAS latency is 3. When the pref signal 115 becomes low level, an initial value is loaded and CLK
The counting is started according to the signal. The hexadecimal counter 201 manages how many commands and data have been input to each FIFO since the pref signal 115 was input. Further, the hexadecimal counter 201 outputs the count value to the decrement counter 202, and the decrement counter 202 loads the value and decrements to the offset value.

When the result of the decrement becomes the offset value, the decrement counter 202 outputs a carry signal. As a result, the hexadecimal counter 201, the D flip-flop 203 and the D flip-flop 205 are reset. The D flip-flop 203 outputs the pref signal 115
Until the reset by the decrement counter 202 is input, the CS control unit 104, the command delay FIFO 103, and the data delay FIFO 102 shown in FIG.
And output to

The D flip-flop 205 outputs a pref signal 115 and an internal CS signal Int CS CLK.
NOR circuit 20 that performs a NOR operation based on signal 702
4 until the reset by the decrement counter 202 is input.
16 is output.

FIG. 3 shows the command delay FI shown in FIG.
FIG. 3 is a block diagram illustrating a delay line related to a RAS signal inside the FO103. The main components are 37-stage D flip-flops D1 to D37 and a data selector 3
01 and shift registers 302, 303 and 304. In this embodiment, in order to optimize internal command and data processing, a delay line with a D flip-flop for minimizing the delay time is constructed.
In addition, a data selector 301 is provided for extracting data from necessary delay bits and selecting data in accordance with CAS latency so that the data is transmitted internally at an optimal time interval in accordance with CAS latency. .

For example, a case in which an 8-word random write operation is performed on the same bank at a CAS latency of 1 will be described with reference to FIGS. FIG. 4 is a diagram showing an operation time chart of the synchronous dynamic semiconductor memory device according to the present invention. As shown in the “CL1 operation mode” of FIG.
The ref signal is set to the high level, the external command is transmitted to the logic circuit unit 108 as it is, and the commands from cycle 3 to cycle 16 are stored in the command delay FIFO 103 and the data delay FIFO 108.

Here, "A" in the external command means an activation (active) command for the memory bank A110, and "Wn" means a write command for the bank activated in the preceding stage and write data given simultaneously with the write command. doing. Since the cycle being executed here is a random write cycle, the write burst length = 1, and when the write is completed, an auto precharge function for automatically starting precharge without inputting a precharge command is provided. I'm using This function is employed in a conventional synchronous dynamic semiconductor memory device. D1 and D7 displayed in the “CL1 operation mode” of FIG.
Are the outputs of the D flip-flops 1 and 7 shown in FIG. Further, the Int CS signal means a CS signal inside the semiconductor memory device, and the Ct signal shown in FIG.
Output from S control section 104.

In the case of CAS latency 1, the latency from the active command to the write command is 1, whereas the latency from the write command to the active command is 2, so "A" and "W"
"2" is taken in continuously from D1 in cycles 4 and 5, and "A" and "W3" are subsequently taken from D2 in cycles 7 and 8.
"A" and "W4" are taken in accordance with the low-level pulse of the Int CS signal from D3 at cycles 10 and 11, and "A" and "W8" are taken from D7 at cycles 22 and 23. To end.

When the temporarily stored data of “W8” is captured at the rising clock of cycle 23, Bu
The sy signal 116 returns to low level, and the Int pref signal returns to high level. Therefore, in the case of the CAS latency 1, by using the outputs of the D flip-flops “1” to “7” as the delay line, it is possible to temporarily store the random write operation for the same 8-word bank.

Therefore, the data selector 30 shown in FIG.
1 is an output DQ1 of D flip-flops "1" to "7"
7 are output to the shift register 302. Also, the signals A6, A5, and A4 output from the mode register 107 input to the data selector 301 are decoded, and if the CAS latency is 1, only OE1 is activated and output to the shift register 302, and OE2 and OE3 are inactive. Keep the state. The shift register 302 receives the activated OE1 and starts outputting data of the D flip-flops “1” to “7” to the internal RAS signal in order in synchronization with the CL1 shift clock 402.

The case of CAS latency 2 and CAS latency 3 is also as shown in FIG. The case where the “CL2 operation mode” is CAS latency 2 is the case where the “CL3 operation mode” is CAS latency 3. CAS
In the case of the latency 2 and the CAS latency 3, unlike the case of the CAS latency 1, the latency from the active command to the write command is 2 in the case of the CAS latency 2 and 3 in the case of the CAS latency 3, and the latency from the write command to the active command. Is 3 for a CAS latency of 2 and 4 for a CAS latency of 3. That is, since the active command and the write command cannot be received with a continuous clock, a low-level pulse of the Int CS signal is required for each command. For the same reason, "W
The command "1" must also be temporarily stored in the command delay FIFO and the data delay FIFO.

In the “CL2 operation mode” of FIG. 4, a 4-word random write cycle is taken as an example, but “1, 3, 2” of D flip-flops “1” to “22” are used.
4, 6, 7, 9, 10, 12, 13, 15, 16, 1
8, 19, 21, 22 ", a random write cycle of 8 words can be executed. The reason why four words are used is to show a flow for controlling random writing of an arbitrary number of words up to eight.

On the other hand, as shown in FIG. 2, the Int pref signal 2 output from the D flip-flop 203
The active width of 09 is variable because it is controlled by the hexadecimal counter 201. Thus, referring to FIG.
“W4” is fetched in cycle 18, while an 8-word random write cycle “W8” is fetched in cycle 38. In the “CL3 operation mode”, a 4-word random write cycle is taken as an example, but “1, 3, 4,...” Of D flip-flops “1” to “37” are used.
6, 7, 9, 10, 12, 13, 15, 16, 18, 1
By using "9, 21, 22", an 8-word random write cycle can be executed.

This example shows that the synchronous dynamic semiconductor memory device according to the present invention is capable of continuous random access of four words to different banks. Since this is a random access to an originally independent bank, an interval for a random access command to the same bank can be automatically secured internally in the present embodiment. Can be satisfied. That is, even if accesses to other banks are mixed, processing can be performed in the same time as random access to the same bank. In this case, “W4” is captured in cycle 25, but an 8-word random write cycle “W8” is captured in cycle 53.

The shift registers 303 and 304 shown in FIG. 3 use a signal A from the mode register input to the data selector as in the case of CAS latency 1.
6, OE2 or OE3 decoded from A5 and A4
, The output of the internal RAS signal is started sequentially in synchronization with the CL2 shift clock 502 or the CL3 shift clock 602.

In FIG. 3, the RAS shown in FIG.
Although a delay line related to the signal 118 is shown, a circuit similar to this circuit is a CAS signal 119 shown in FIG.
The E signal 120, the address signal 122 and the bank address signal 121 correspond to the command delay FIFO 103
For each input data line, the data delay FI
The FO 102 is provided.

On the other hand, the CS control unit 10 shown in FIG.
4 is provided with the circuits shown in FIGS. FIG. 5 shows Int CS at CAS latency 1
1 signal, CL1 shift clock signal, Int CSC
This is a circuit for generating the LK CS1 signal. Similarly, FIG. 6 shows an Int CS2 signal, CL at the time of CAS latency 2.
FIG. 7 is a circuit for generating an Int CS3 signal and a CL3 shift clock signal when the CAS latency is 3;

As described above, since the active pulse of the Int CS signal at the CAS latency of 1 is two clock cycles, it cannot be counted by the decrement counter 202 in FIG. 2 based on this signal. Therefore, the CL1 shift clock signal and C
Int CS which is the result of performing an OR operation with the LK signal
The CLK CS1 signal is counted by the decrement counter 202. FIG. 8 shows the data selector 3 of FIG.
01, OE1 (305), OE2 (306),
Using OE3 (307), the internal CS signal Int
This circuit generates a CS signal 701 and a clock Int CS CLK signal 702 input to the decrement counter 202.

[0051]

As is apparent from the above description, according to the synchronous dynamic type semiconductor memory device of the present invention, the delay between the time when data constituted by using a D flip-flop is written and the time when it can be read is reached. Data delay FIFO and command delay FIFO to minimize time
O, so that a random write operation from outside the device can be executed without interruption. As a result, the random write performance is improved for each CAS latency as follows.

In the case of CAS latency 1: Conventional required number of clock cycles: 23 cycles for 8 words, 11 cycles for 4 words 11 external clock cycles of the synchronous dynamic semiconductor memory device according to the present invention: 16 words for 16 words Cycle, 4 words 8 cycles 8 words random write cycle execution: 23/16 =
1.44 When 4-word random write cycle is executed: 11/8 =
1.37

In the case of CAS latency 2: Conventional required number of clock cycles: 38 cycles for 8 words, 18 cycles for 4 words 18 external clock cycles of the synchronous dynamic semiconductor memory device according to the present invention: 16 words for 16 words Cycle, 4 words 8 cycles 8 words random write cycle execution: 38/16 =
2.37 When 4-word random write cycle is executed: 18/8 =
2.25

In case of CAS latency 3: Conventional required number of clock cycles: 53 cycles for 8 words, 25 cycles for 4 words 25 clock cycles external to the synchronous dynamic semiconductor memory device according to the present invention: 16 words for 16 words Cycle, 4 words 8 cycles 8 words random write cycle execution: 53/16 =
3.31 When 4-word random write cycle is executed: 25/8 =
3.12

Therefore, in the image display device, if the ratio of random write access to the entire cycle of accessing the semiconductor memory device used for the frame memory is 10% as in the present invention, the performance of the entire system is reduced. Can be provided from 13% to 33%.

In addition, since a command can be continuously input only for the capacity of the FIFO memory at the time of a random write cycle without depending on the CAS latency, a synchronous dynamic semiconductor device which can easily control an external device can be used. A storage device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a synchronous dynamic semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram of a command prefetch control unit included in the synchronous dynamic semiconductor memory device shown in FIG.

FIG. 3 is a circuit diagram of a command delay FIFO included in the synchronous dynamic semiconductor memory device shown in FIG.

4 is an operation timing chart of the synchronous dynamic semiconductor memory device shown in FIG.

5 is a circuit diagram of a circuit included in a CS control circuit included in the synchronous dynamic semiconductor memory device shown in FIG.

6 is a circuit diagram of a circuit included in a CS control circuit included in the synchronous dynamic semiconductor memory device shown in FIG.

7 is a circuit diagram of a circuit included in a CS control circuit included in the synchronous dynamic semiconductor memory device shown in FIG.

8 is a diagram illustrating a C corresponding to each CAS latency of the synchronous dynamic semiconductor memory device shown in FIG.
FIG. 3 is a circuit diagram illustrating an S control circuit.

FIG. 9 is a diagram illustrating a drawing example of a rectangular area by a tile map technique;

[Explanation of symbols]

 101 Command Prefetch Control Unit 102 Data Delay FIFO 103 Command Delay FIFO 104 CS Control Unit 105 Data Input Buffer 106 Data Output Buffer 107 Mode Register 108 Logic Circuit 109 Timing Generation Circuit 110 Memory Bank A 111 Memory Bank B 112 Command / Data Bus 113 Command / Data bus 114 External data bus 115 Pref signal 116 Busy signal 117 CS signal 118 RAS signal 119 CAS signal 120 WE signal 121 Bank address signal 122 Address signal 123 Clock signal 201 Hexadecimal counter 202 Decrement counter 203 D flip-flop 204 NOR circuit 205 D flip-flop 206 mode register A6 207 signal from mode register A5 208 signal from mode register A4 209 Int pref signal 301 data selector 302 shift register 303 shift register 304 shift register 305 OE1 306 OE2 307 OE3 401 Int CS1 signal 402 CL1 shift clock 403 Int CS CLK CS1 signal 501 Int CS2 signal 502 CL2 shift clock 601 Int CS3 signal 602 CL3 shift clock 701 Int CS signal 702 Int CS CLK signal 901 Image

Claims (3)

[Claims] A command delay FIFO for temporarily storing a command input from the outside; a data delay FIFO for temporarily storing data input from the outside; and a command delay FIFO based on a signal output from a mode register. Whether to store commands in the FIFO,
And determining whether or not to store data in the data delay FIFO, outputting a command and data not to be stored to the logic circuit unit, and outputting a Busy signal to the outside when the temporary storage of the command and data is started. A synchronous dynamic semiconductor memory device, comprising: a command prefetch control unit for controlling the internal CS signal based on a signal output from the command prefetch control unit. 2. The synchronous dynamic type as claimed in claim 1, wherein said command delay FIFO has a plurality of D flip-flops for storing commands, and a shift register for selecting the stored commands. Semiconductor storage device. 3. A command prefetch control unit comprising: a hexadecimal counter for setting an initial value of a counter corresponding to CAS latency based on a signal output from a mode register; and a first D flip-flop for outputting an Int pref signal. And a second D flip-flop that outputs a Busy signal; and a decrement counter that loads a count value output from the hexadecimal counter and decrements the offset value to an offset value. The synchronous dynamic semiconductor memory device according to the above.