JPH10271180A - Offset correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an offset correction circuit that always corrects an offset of a received base band signal accurately even when a recovered clock signal is unstable. SOLUTION: A reception base band signal detected and obtained by a detection circuit 800 is given to an offset detection circuit 110 and an offset subtractor circuit 810. The offset detection circuit 110 applies integration or moving average processing to a signal with a periodicity in the received base band signal to detect an offset being a DC component of the reception base band signal. The offset subtractor circuit 810 subtracts an offset correction signal outputted from the offset detection circuit 110 from the reception base band signal to correct the offset of the reception base band signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an offset correction circuit provided for correcting an offset of a received baseband signal in a receiver used in the field of wireless communication.

[0002]

2. Description of the Related Art A conventional offset correction circuit includes:
For example, it is described in JP-A-8-130568. Hereinafter, the related art will be described with reference to the drawings.

FIG. 22 is a circuit block diagram of a digital demodulator having a conventional offset correction circuit. In the figure, 800 is a detection circuit, 810 is an offset subtraction circuit, 820 is an analog / digital conversion circuit, and 830 is a demodulation circuit. Circuit, 840 is an offset detection circuit, 850 is an addition circuit for adding identification data, 860 is a digital / analog conversion circuit, 870 is a register for storing and holding added data, 880 is an averaging circuit, and 920 is a reproduction clock.

Next, the operation will be described. In FIG. 22, a received signal is input to a detection circuit 800. Detection circuit 800 outputs a signal obtained by detecting the received signal as a received baseband signal. This received baseband signal is input to the offset subtraction circuit 810. The offset correction signal output from the offset detection circuit 840 is also input to the offset subtraction circuit 810. The offset subtraction circuit 810 subtracts the offset correction signal output from the offset detection circuit 840 from the reception baseband signal output from the detection circuit 800, and outputs the result of the subtraction as an offset-corrected baseband signal. The baseband signal after the offset correction is input to the analog / digital conversion circuit 820. Also, the reproduction clock 920
Is also input to the analog / digital conversion circuit 820. The analog / digital conversion circuit 820 converts the offset-corrected baseband signal output from the offset subtraction circuit 810 into a digital signal in synchronization with the reproduction clock 920, and outputs the conversion result as identification data. This identification data is input to the demodulation circuit 830 and the offset detection circuit 840. The demodulation circuit 830 performs predetermined logic processing on the identification data output from the analog / digital conversion circuit 820, and outputs demodulated data synchronized with the reproduction clock 920. Offset detection circuit 84
0 detects an offset correction value from the identification data output from the analog / digital conversion circuit 820, and outputs the detection result as an offset correction signal.

Next, the operation of the offset detection circuit 840 will be described. In FIG. 22, the identification data input to the offset detection circuit 840 is input to the addition circuit 850. Further, addition data output from the register 870 before one sampling timing is also input to the addition circuit 850. The adder circuit 850 stores the identification data output from the analog / digital conversion circuit 820 and the register 870.
Are added together, and the result of addition is output as added data. This addition data is input to the register 870 and the digital / analog conversion circuit 860. The register 870 stores the addition data output from the addition circuit 850 and outputs the addition data stored one sampling timing earlier. The digital / analog conversion circuit 860 converts the addition data output from the addition circuit 850 into an analog signal, and outputs the conversion result as an analog addition signal. This analog addition signal is input to the averaging circuit 880. Averaging circuit 880 averages the analog addition signal output from the digital-to-analog conversion circuit, and outputs the result as an analog addition average signal. The offset detection circuit 840 outputs the analog average signal output from the averaging circuit 880 as an offset correction signal.

Now, for example, it is assumed that a reception baseband signal as shown in FIG. The received baseband signal is converted by the analog-to-digital conversion circuit 820 as shown in FIG.
, T3, t4,... Are sampled and converted into 4-bit identification data. For example, at time t1
Is converted to "1" by using the hexadecimal notation shown in the figure, and is converted to "E" at time t2.

In the addition circuit 850 of the offset detection circuit 840, the analog / digital conversion circuit 82
The identification data output from 0 and the addition data one sampling timing earlier read from the register 870 are added. For example, the identification data “1” output from the analog / digital conversion circuit 820 at time t1 is
It is added to the added data “0” one sampling timing earlier, and as a result, “1” is output as the added data. Further, the identification data “E” output from the analog / digital conversion circuit 820 at time t2 is added to the added data “1” one sampling timing earlier (time t1), and as a result, “F” is output as added data. Is done. Similarly, in the addition circuit 850, the identification data output from the analog / digital conversion circuit 820 and the addition data one sampling timing earlier are added at each sampling timing t3, t4,.

The addition data output from the addition circuit 850 at each sampling timing is converted into an analog signal by the digital / analog conversion circuit 860 and output as an analog addition signal. Averaging circuit 8
80 averages the analog addition signal output from the digital / analog conversion circuit 860 and outputs the result as an analog addition average signal. Offset detection circuit 840
In, the analog averaging signal output from the averaging circuit 880 is output as an offset correction signal.

As described above, in the conventional example, the identification data output from the analog-to-digital conversion circuit 820 is sequentially added in the addition circuit 850, and the addition data output from the addition circuit 850 is converted into the analog data in the digital-analog conversion circuit 860. Is converted to a digital signal.
The analog addition signal output from analog conversion circuit 860 is averaged in averaging circuit 880. The offset detection circuit 840 feeds back the analog addition average signal output from the averaging circuit 880 to the offset subtraction circuit 810 as an offset correction signal, and the offset subtraction circuit 81
0 corrects the offset of the reception baseband signal by subtracting the offset correction signal output from the offset detection circuit 840 from the reception baseband signal output from the detection circuit 800.

Therefore, according to the conventional example, the offset correction signal has an amplitude average value symmetrical in the amplitude axis direction of the received baseband signal. For this reason, even if the position of the signal point is shifted from the normal position due to amplitude fluctuation or distortion, the shift amount is offset each other, and only the offset of the received baseband signal is obtained.

As described above, in the conventional offset correction circuit, among the identification data output from the analog-to-digital conversion circuit 820, data to be symmetrical in the amplitude direction about the phase axis are added to each other, and the addition is performed. An average value of the output is obtained, an offset correction signal is generated based on the average value, and the offset correction signal is subtracted from the reception baseband signal. The offset of the baseband signal can always be corrected accurately.

[0012]

As described above, the conventional offset correction circuit generates an offset correction signal based on the average value of the identification data. However, the conventional offset correction circuit operates on the premise that the reproduction clock 920 is stable. For this reason, if the reproduction clock 920 is unstable, it is not possible to identify a signal that should be symmetrical in the amplitude direction about the phase axis. There is a problem that a variable element is added, and as a result, the offset of the received baseband signal cannot be properly corrected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an offset correction circuit capable of always accurately correcting an offset of a received baseband signal even when a reproduced clock is unstable. The purpose is to provide.

[0014]

According to the present invention, there is provided an offset correction circuit for detecting a received signal in an offset correction circuit used in a receiver for receiving and demodulating a predetermined modulated wave; An average of a signal having periodicity in the received baseband signal output from the detection unit is obtained, and an offset detection unit that detects an offset that is a DC component of the reception baseband signal, and an offset output from the offset detection unit Offset subtracting means for subtracting an offset correction signal from the received baseband signal.

The offset correction circuit according to a second aspect of the present invention is the offset correction circuit, wherein the offset detection means includes a time averaging means for averaging the periodic signal for a time that is an integral multiple of the cycle,
Holding means for holding an average signal output from the time averaging means.

According to a third aspect of the present invention, in the offset correction circuit, the offset detecting means outputs a moving average value for calculating the moving average value of the periodic signal over a period of an integral multiple of the period, and the moving average means outputs the moving average value. Holding means for holding the moving average signal.

According to a fourth aspect of the present invention, in the offset correction circuit, the offset detection means includes a filtering means for removing a high frequency component of a signal output from the holding means.

An offset correction circuit according to a fifth aspect of the present invention comprises:
The moving averaging means includes two or more averaging means for averaging the periodic signal for an integral multiple of the period, and multiplexing means for multiplexing the average signal output from the averaging means. Is provided.

According to a sixth aspect of the present invention, an offset correction circuit comprises:
The offset detecting means includes a periodic signal offset subtracting means for subtracting an offset which is a DC component of the periodic signal from the output signal.

According to a seventh aspect of the present invention, an offset correction circuit comprises:
Received signal strength detecting means for detecting the strength of the received signal, and offset detection control means for generating an offset detection control signal for controlling the offset detecting means based on the received signal strength output from the received signal strength detecting means, Prepare.

An offset correction circuit according to an eighth aspect of the present invention
Demodulation means for demodulating the offset-corrected received baseband signal output from the offset subtraction means,
UW detection means for detecting a unique word signal, which is a slot reception timing signal, from demodulated data output from the demodulation means, and the offset detection means using a UW detection signal output from the UW detection means. And an offset detection control means for generating an offset detection control signal for controlling

According to a ninth aspect of the present invention, an offset correction circuit comprises:
Received signal strength detection means for detecting the strength of the received signal, demodulation means for demodulating the offset-corrected reception baseband signal output from the offset subtraction means, and demodulated data output from the demodulation means, UW detection means for detecting a unique word signal which is a slot reception timing signal, and a reception signal strength output from the reception signal strength detection means and a UW detection signal output from the UW detection means, Offset detection control means for generating an offset detection control signal for controlling the offset detection means.

According to a tenth aspect of the present invention, there is provided an offset correction circuit, comprising: a reception signal strength detection means for detecting the strength of the reception signal; and a demodulation for demodulating the offset corrected reception baseband signal output from the offset subtraction means. Means, UW detection means for detecting a unique word signal, which is a slot reception timing signal, from the demodulated data output from the demodulation means, and the reception signal strength output from the reception signal strength detection means and the UW And an offset detection control unit for generating an offset detection control signal for controlling the offset detection unit using a UW detection signal output from the detection unit.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a configuration diagram showing a configuration of an embodiment showing the present invention. In the figure, reference numeral 110 denotes an offset detection circuit. The same or corresponding parts as in the conventional example are denoted by the same reference numerals.

Next, the operation will be described. In FIG. 1, a received signal is input to a detection circuit 800. Detection circuit 800 detects the received signal and outputs a received baseband signal. The received baseband signal is offset detection circuit 1
10 and input to the offset subtraction circuit 810. The offset detection circuit 110 calculates a time average of an integral multiple of the period of the periodic signal or a moving average of a time of an integral multiple of the period of the periodic signal of the signal having periodicity in the received baseband signal, And an offset correction signal is generated. The offset subtraction circuit 810 subtracts the offset correction signal from the received baseband signal to correct the offset of the received baseband signal.

Here, the received baseband signal is defined as g (t), and g (t) is a constant offset period T satisfying the equation (1).
, The offset detection circuit 110 outputs nT (n is an integer of 1 or more) of the received baseband signal g (t).
The offset correction signal r (nT) obtained by calculating the time average or the nT time moving average of the received baseband signal g (t) is calculated by the equation (2) ) And a signal indicating the offset DC of the received baseband signal as shown in equation (3). g (t) = f (t) + DC = f (t−T) + DC (1) where T: cycle, t: time, DC: offset f (t): average value is 0, and periodic function of cycle T It is.

[0027]

(Equation 1)

FIG. 2 shows the offset detection circuit 1 shown in FIG.
FIG. 3 is a diagram illustrating an example of an offset correction signal generated by the control unit 10; In the figure, the average signal r (t) is a periodic signal f (t) having a period T in the received baseband signal g (t).
+ Shows the average DC, an offset DC received baseband signal for each nT time (t = t _a -T in _{FIG, t a, t a + T} ). Further, the moving average signal m (t) is equal to the received baseband signal g.
(T) is a signal obtained by performing a moving average of a periodic signal f (t) + DC of a period T in (t), and is always offset from the reception baseband signal g (t) after T time from the moving average calculation time t = ta-T. Shows DC voltage. That is, in the offset subtraction circuit 810, the offset correction signal r (nT) or m
Subtracting (t) from the received baseband signal g (t) gives g
(t) -r (nT) = (f (t) + DC) -DC = f (t) or g (t) -m (t) = {f (t)
+ DC} −DC = f (t), which is equivalent to performing the operation of FIG. 2, so that as shown in FIG. 2, nT of the periodic signal f (t) having the cycle T in the received baseband signal g (t) It is possible to correct the offset of the received baseband signal using the offset correction signal obtained by calculating the time average or the moving average. Further, since the offset of the received baseband signal is detected by averaging or moving average the received baseband signal without depending on the reproduced clock, the offset of the received baseband signal can be detected even when the reproduced clock is unstable. Correction can always be made accurately.

Embodiment 2 FIG. 3 is a configuration diagram showing a configuration of an embodiment of the offset detection circuit 110 of FIG. 1. In FIG. 3, reference numeral 210 denotes an averaging circuit, and 220 denotes a holding circuit.

Next, the operation will be described. In FIG. 3, the received baseband signal input to offset detection circuit 110 is input to averaging circuit 210. Average circuit 2
10 outputs the average value of the received baseband signal as an average signal. However, the averaging circuit 210 is reset at every integral multiple of the synchronization of the periodic signal in the received baseband signal. The holding circuit 220 outputs the averaged signal output from the averaging circuit 210 immediately before resetting the averaging circuit 210, as an offset correction signal, after holding.

FIG. 4 is a diagram showing an example of the relationship between the received baseband signal and the average signal generated by the averaging circuit 210. As shown in FIG. 4, the average signal output from the averaging circuit 210 is every nT time,
Immediately before the reset of 10, the offset value DC of the received baseband signal is shown. Therefore, in the holding circuit 220,
By holding the average signal immediately before the reset of the averaging circuit 210, nT of the periodic signal having the period T in the received baseband signal is obtained.
A time average can be obtained.

Embodiment 3 FIG. FIG. 5 is a configuration diagram showing a configuration of an embodiment of the offset detection circuit 110 in FIG. 1. In the drawing, reference numeral 230 denotes a filtering circuit.
The same or corresponding parts as those in FIG. 3 showing the configuration of the offset detection circuit 110 according to the second embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Next, the operation will be described. In FIG. 5, the average signal after holding output from the holding circuit 220 is input to the filtering circuit 230. Filtering circuit 230 outputs the filtered average signal from which the high-frequency components of the retained average signal have been removed as an offset correction signal.

FIG. 6 shows an offset-corrected received baseband signal when the held average signal output from the holding circuit 220 is used as an offset correction signal and a filtered average signal output from the filtering circuit 230 as an offset correction signal. FIG. 9 is a diagram illustrating an example of a received baseband signal after offset correction in the case where the correction is performed. As shown in FIG.
At the time of holding switching of the average signal in the holding circuit 220, the average signal after holding includes a high-frequency component. If the offset correction signal contains a high-frequency component, distortion occurs in the received baseband signal after offset correction. That is, by outputting the filtered average signal from which the high-frequency component of the average signal after holding is removed by the filtering circuit 230 as an offset correction signal, the offset correction generated when the holding circuit 220 switches the holding of the average signal as compared with the second embodiment. The distortion of the post-reception baseband signal can be reduced.

Embodiment 4 FIG. FIG. 7 is a configuration diagram showing a configuration of an embodiment of the offset detection circuit 110 of FIG. 1, and in the figure, 240 is a moving average circuit. The same or corresponding portions as those in FIG. 3 showing the configuration of offset detecting circuit 110 according to the second embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Next, the operation will be described. In FIG. 7, the received baseband signal input to offset detection circuit 110 is input to moving average circuit 240. The moving average circuit 240 calculates a moving average of a signal having periodicity in the received baseband signal for a time period that is an integral multiple of the period, and outputs the result as a moving average signal.

FIG. 8 shows the received baseband signal, the average signal after holding output from the holding circuit 220 shown in FIG. 2, and the output from the moving average circuit 240 when the offset of the received baseband signal changes rapidly. It is a figure showing an example of a moving average signal. As shown in FIG. 8, when the offset of the received baseband signal changes rapidly, simply
Rather than generating an offset correction signal based on the nT time average of the received baseband signal,
When the offset correction signal is generated based on the moving average value of time, the offset correction signal is generated more accurately.

FIG. 9 shows a received baseband signal after offset correction when the moving average signal output from the moving average circuit 240 shown in FIG. 7 is used as an offset correction signal, and a moving average signal after holding output from the holding circuit 220. FIG. 5 is a diagram illustrating an example of a received baseband signal after offset correction when is an offset correction signal. As shown in FIG. 9, the moving average signal output from moving average circuit 240 is distorted due to noise included in the received baseband signal. That is, when the moving average signal output from the moving average circuit in the offset detection circuit shown in FIG. 7 is output as the offset correction signal, distortion occurs in the offset-corrected received baseband signal. When the variation of the offset of the received baseband signal is small, the offset detection circuit shown in FIG. 7 holds the holding average held by the holding circuit 220 rather than outputting the moving average signal output from the moving average circuit 240 as the offset correction signal. When the post-moving average signal is output as the offset correction signal, an offset-corrected reception baseband signal with less distortion can be obtained. Furthermore, since the offset correction signal is generated based on the nT time moving average value of the received baseband signal, even if the offset of the received baseband signal changes rapidly, it is more accurate than in the second or third embodiment. The offset of the received baseband signal can be corrected.

Embodiment 5 FIG. 10 is a configuration diagram showing a configuration of an embodiment of the offset detection circuit 110 in FIG. 1, and 250 is a filtering circuit. The same or corresponding parts as those in FIG. 7 showing the configuration of the offset detection circuit 110 according to the fourth embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Next, the operation will be described. In FIG. 10, the moving average signal after holding output from the holding circuit 220 is input to the filtering circuit 250. The filtering circuit 250 outputs the filtered moving average signal from which the high frequency component of the held moving average signal has been removed as an offset correction signal.

Similarly to the description in the third embodiment, when the holding circuit 220 switches the holding of the moving average signal, the moving average signal after holding contains a high-frequency component. If the offset correction signal contains a high-frequency component, distortion occurs in the received baseband signal after offset correction. That is, by outputting the filtered moving average signal from which the high frequency component of the moving average signal after holding is removed by the filtering circuit 250 as the offset correction signal, the offset corrected signal generated at the time of holding switching in the holding circuit 220 is compared with the fourth embodiment. The distortion of the received baseband signal can be reduced.

Embodiment 6 FIG. FIG. 11 corresponds to FIG.
FIG. 2 is a configuration diagram showing a configuration of an embodiment of a moving average circuit 240 indicated by
, 210L are first, second to Lth (L is an integer of 2 or more) averaging circuits, and 270 is L output from the first, second to Lth averaging circuits 210A, 210B,. Multiplexing circuit for multiplexing the average signal of

Next, the operation will be described. In FIG. 11, the received baseband signal input to the moving average circuit 240 includes first, second to L-th average circuits 210A and 210A.
OB,..., 210L. The first, second to L-th averaging circuits 210A, 210B,..., 210L start averaging operations at different times, respectively.
The second to L-th average signals are output. Multiplexing circuit 27
0 multiplexes the first, second to L-th average signals, and outputs the result as a multiplex average signal. In the moving average circuit 240 in FIG. 11, the multiplexed average signal output from the multiplexing circuit 270 is output as a moving average signal.

FIG. 12 is a diagram showing an operation example of the configuration of one embodiment of the moving average circuit 240 shown in FIG. As shown in FIG. 12, the first averaging circuit 210A
The average operation start time is x1, and the second averaging circuit 210B
The average operation start time of (x1 + nT / L) to the third averaging circuit 2
The average operation start time of 10C is (x1 + 2nT / L), and the average operation start time of the L-th averaging circuit 210L is (x1 + (L-1) × nT / L).
And However, n and L are both integers of 1 or more. That is, the first averaging circuit 210 at time (x1 + nT)
A outputs the average value of the received baseband signal for the time nT from the time x1 to the time (x1 + nT), and the time (x1 + nT / L + nT)
At the time (x1 + nT / L)
To the time (x1 + nT / L + nT), and outputs the average value of the received baseband signal for the time nT from the time (x1 + nT / L + nT). The average value of the received baseband signal for nT time from 2nT / L) to time (x1 + 2nT / L + nT) is output, and the L-th average at time (x1 + (L-1) nT / L + nT) The circuit L outputs the average value of the received baseband signal for nT time from the time (x1 + (L-1) nT / L) to the time (x1 + (L-1) nT / L + nT).

The multiplexing circuit 270 calculates the time (x1 + a × nT / L)
, So that the average value of the nT time of the received baseband signal is always output.
10A, 210B,..., 210L,
The second to L-th average signals are multiplexed. Where a is 1
Is an integer greater than or equal to. That is, as shown in FIG. 12, the multiplexing circuit 270 outputs the first signal at the time (x1 + nT).
Select the first average signal output from the averaging circuit 210A of the second averaging circuit 21A at time (x1 + nT + nT / L).
0B, and selects the second average signal output at time (x1
+ nT + 2nT / L) to select the third average signal output from the third averaging circuit 210C, and to output at time (x1 + a × nT / L) from the (a mod L) averaging circuit. (A
mod L), and outputs the result as a multiplexed average signal. Where (a modL) is the remainder of a on L. Therefore, as shown above, FIG.
The moving average circuit 240 denoted by 1 can calculate a moving average of the received baseband signal for nT time.

Embodiment 7 FIG. FIG. 13 is a configuration diagram showing a configuration of an embodiment of the offset detection circuit 110 of FIG. 1, and reference numeral 260 denotes a periodic signal offset subtraction circuit. The same or corresponding portions as those in FIG. 5 showing the configuration of offset detecting circuit 110 according to the third embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Heretofore, as shown in the equation (1), when the signal f (t) having periodicity in the received baseband signal g (t) is a periodic function having an average value of 0 and a period of T, The embodiment has been described. Here, as shown in equation (4), f (t) is the average value D (D
Is a real number, D ≠ 0), and a periodic function of the period T, the offset detection circuit 110 according to the first, second, third, fourth, fifth, or sixth embodiment performs the operation of (offset of received baseband signal +
Since D) is output as an offset correction signal, the offset of the received baseband signal cannot be accurately corrected. However, D is a value known on the communication system used. The periodic signal offset subtraction circuit 260 subtracts D, which is the average value of the periodic signal f (t), from the filtered average signal output from the filtering circuit 250, and outputs the result of the subtraction as an offset-subtracted average signal. In offset detection circuit 110 in FIG. 13, the average signal after offset subtraction output from periodic signal offset subtraction circuit 260 is output as an offset correction signal. g (t) = f (t) + DC = f (t−T) + DC (4) where T: cycle, t: time, DC: offset, f (t): average value is D (≠ 0), Periodic function of period T

FIG. 14 is a diagram showing an example of a periodic signal f (t) in the received baseband signal g (t). That is, when the average value of f (t) is D (≠ 0) as shown in FIG. 14, in the periodic signal offset subtraction circuit 260 shown in FIG. By subtracting D which is the average value of the periodic signal f (t) from the offset detection circuit 110, the offset of the reception baseband signal can be accurately detected by the offset detection circuit 110, and the offset subtraction circuit 810 detects the offset of the reception baseband signal. The offset can be correctly corrected.

Embodiment 8 FIG. FIG. 15 is a configuration diagram showing a configuration of an embodiment of the offset correction circuit according to the eighth embodiment, where 300 is a reception signal strength detection circuit that detects the strength of the reception signal, and 310 is the reception signal strength detection circuit. And an offset detection control circuit for generating an offset detection control signal signal for controlling the offset detection circuit using the received signal strength output from the controller. FIG. 1 shows the configuration of the offset correction circuit according to the first embodiment.
The same or corresponding parts have the same reference characters allotted, and description thereof will not be repeated.

Next, the operation will be described. In FIG. 15, a received signal is input to a received signal strength detection circuit 300. The received signal strength detection circuit 300 detects the strength of the received signal, and outputs the detection result as the received signal strength. The received signal strength is input to the offset detection control circuit 310. The offset detection control circuit 310 detects the slot reception timing from the received signal strength, generates an offset detection control signal for controlling the offset detection circuit 110, and outputs it.

FIG. 16 is a diagram showing an example of a slot reception timing detecting operation in the offset correction circuit shown in FIG. As shown in FIG. 16, in a radio communication system using a modulated wave having a slot configuration, the offset of a received baseband signal in a slot may be different from the offset of a received baseband signal outside a slot. In an offset correction circuit used in a wireless communication system, it is desirable that the offset detection circuit 110 operates only in a slot. Accordingly, the received signal strength detection circuit 300 detects the strength of the received signal, and the offset detection control circuit 310 detects the slot reception timing based on the received signal strength detected by the received signal strength detection circuit 300, thereby providing an offset. The detection control signal can be generated, and the offset detection circuit 110 can be operated only in the slot.

Embodiment 9 FIG. FIG. 17 is a configuration diagram showing the configuration of the ninth embodiment of the offset correction circuit.
Is a demodulation circuit for demodulating a received baseband signal after offset correction, and 320 is a UW detection circuit for detecting a unique word signal which is a slot reception timing signal based on demodulated data output from the demodulation circuit 830.
The same or corresponding portions as those in FIG. 15 showing the configuration of the offset correction circuit according to the eighth embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Next, the operation will be described. In FIG. 17, demodulated data output from demodulation circuit 830 is input to UW detection circuit 320. UW detection circuit 320 detects a unique word signal based on the demodulated data and outputs a UW detection signal. The UW detection signal is input to the offset detection control circuit 310. The offset detection control circuit 310 detects the slot reception timing from the UW detection signal, generates an offset detection control signal for controlling the offset detection circuit 110, and outputs this.

FIG. 18 is a diagram showing an example of a slot reception timing detecting operation in the offset correction circuit shown in FIG. As described in the eighth embodiment, in an offset correction circuit used in a wireless communication system using a modulated wave having a slot configuration, it is desirable that the offset detection circuit 110 operates only within a slot.
Therefore, as shown in FIG.
At 20, a unique word signal indicating the slot reception timing is detected, and an offset detection control circuit 310
, The offset detection control signal can be generated by detecting the slot reception timing based on the UW detection signal output from the UW detection circuit 320, and the offset detection circuit 110 can be operated only in the slot. .

Embodiment 10 FIG. FIG. 19 is a configuration diagram showing a configuration of the tenth embodiment of the offset correction circuit.
Reference numeral 20 denotes a UW detection circuit for detecting a unique word signal. The same or corresponding parts as those in FIG. 17 showing the configuration of the offset correction circuit according to the ninth embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Next, the operation will be described. In FIG. 19, a received signal is input to a received signal strength detection circuit 300. The received signal strength detection circuit 300 detects the strength of the received signal, and outputs the detection result as the received signal strength. The received signal strength is input to the offset detection control circuit 310. The demodulated data output from the demodulation circuit 830 is input to the UW detection circuit 320. The UW detection circuit 320 detects a unique word signal that is a slot reception timing based on the demodulated data, and outputs a UW detection signal. The UW detection signal is input to the offset detection control circuit 310. In the offset detection control circuit 310,
The reception timing of the slot is detected from the received signal strength and the UW detection signal, and an offset detection control signal for controlling the offset detection circuit 110 is generated and output.

That is, in a radio communication system using a modulated wave having a slot configuration, the offset of a received baseband signal inside and outside a slot may be different from each other. In the offset correction circuit used in the above, it is desirable that the offset detection circuit 110 operates only in the slot. Therefore, the reception signal strength detection circuit 300 detects the reception signal strength indicating the reception timing of the slot, and the UW detection circuit 320 detects the unique word signal indicating the reception timing of the slot,
The offset detection control circuit 310 generates an offset detection control signal by detecting the slot reception timing based on the received signal strength output from the received signal strength detection circuit 300 and the UW detection signal output from the UW detection circuit 320. Offset detection circuit 1
10 can only operate in slots.

FIG. 20 is a diagram showing an example of an erroneous detection operation of the slot reception timing in the offset correction circuit shown in FIG. 15 and an erroneous detection operation of the slot reception timing in the offset correction circuit shown in FIG. For example, in the eighth embodiment, when there is a strong interference wave outside the slot, the offset detection control circuit 310 erroneously detects that the signal is inside the slot despite the fact that the interference wave is outside the slot. In the ninth embodiment,
If the received baseband signal power to noise power ratio is small,
The UW detection rate becomes low, and the offset detection control circuit 310 does not detect that it is out of the slot even though it is in the slot. In the tenth embodiment, since the offset detection control circuit 310 generates an offset detection control signal based on the received signal strength and the UW detection signal,
The slot reception timing can be detected more accurately than in the eighth or ninth embodiment.

Embodiment 11 FIG. FIG. 21 shows a detection circuit 80.
It is configured to detect and correct the offset of the received baseband signal from the received baseband signal output from 0, but as shown in FIG.
The offset of the received signal is corrected by subtracting the offset correction signal from the received baseband signal output from 00, and from the received baseband signal after the offset correction,
It may be configured to detect an offset of the received baseband signal.

[0060]

According to the first aspect of the present invention, there is provided an offset correction circuit used in a receiver for receiving and demodulating a predetermined modulated wave, comprising: a detecting means for detecting a received signal; Offset detection means for calculating an average of a periodic signal of the detected reception baseband signal to detect an offset, and subtracting the offset correction signal output from the offset detection means from the reception baseband signal to obtain the reception signal. Since the apparatus is provided with the offset subtraction means for correcting the offset of the baseband signal, the offset can always be accurately corrected.

According to a second aspect of the present invention, the offset detecting means includes an averaging means for averaging the periodic signal according to the first aspect, and a holding means for holding the average signal output from the averaging means. Therefore, it is possible to calculate a time average value of an integer multiple of the period of a signal having periodicity in the received baseband signal.

Further, the offset detecting means according to claim 3 holds a moving average means for calculating a moving average value of the periodic signal according to claim 1, and a moving average signal output from the moving average means. And a holding unit for the offset correction circuit that can always correct the offset accurately even when the offset changes rapidly, and furthermore, the offset of the received baseband signal is small. Even in such a case, it is possible to obtain an offset correction circuit that can reduce distortion generated in the received baseband signal after offset correction.

Further, the offset detecting means according to claim 4 includes a filtering means for removing a high-frequency component of the post-holding signal output from the holding means according to claim 3 or 4, so that the offset detecting means is provided with a filter. It is possible to obtain an offset correction circuit that can reduce distortion of the received baseband signal after offset correction that occurs at the time of holding switching in the means.

Further, the moving averaging means according to claim 5 comprises:
Claims 1 and 2 comprising at least two averaging means for averaging a periodic signal according to claim 1 and multiplexing means for multiplexing an average signal output from the averaging means. A moving average can be calculated.

Further, the offset detecting means according to the present invention is characterized in that the average signal after holding outputted from the holding means according to claim 2 or the average signal after filtering outputted from the filtering means according to claim 3 or the mean signal after filtering. A period for subtracting the offset of the periodic signal according to claim 1 from the moving average signal after holding output from the holding means according to claim 4 or the moving average signal after filtering output from the filtering means according to claim 5. Since the signal offset subtraction means is provided, an offset correction circuit capable of always accurately correcting the offset of the received baseband signal even when the offset of the periodic signal in the received baseband signal is other than 0 Can be.

The offset correction circuit according to claim 7 is:
An offset correction circuit used in a receiver for receiving and demodulating a modulated wave having a slot configuration, comprising: a reception signal strength detection means for detecting the strength of the reception signal; and a reception signal output from the reception signal strength detection means. Since it has an offset detection control means for generating an offset detection control signal for controlling the offset detection means using the signal strength, even under a wireless communication system using a modulated wave of the slot configuration, always It is possible to accurately correct the offset of the received baseband signal.

The offset correction circuit according to claim 8 is:
An offset correction circuit used in a receiver that receives and demodulates a modulated wave having a slot configuration, comprising: a demodulation circuit for demodulating a received baseband signal after offset correction according to claim 1; and an output from the demodulation circuit. UW detection means for detecting a unique word signal that is a slot reception timing signal from demodulated data to be received, and offset detection for controlling the offset detection means using a UW detection signal output from the UW detection means Since the apparatus includes the offset detection control means for generating the means control signal, the offset of the received baseband signal can always be accurately corrected even in a wireless communication system using a modulated wave having a slot configuration.

The offset correction circuit according to claim 9 is:
An offset correction circuit used in a receiver for receiving and demodulating a modulated wave having a slot configuration, wherein the offset correction circuit outputs a received signal strength detecting means for detecting the strength of the received signal, and is output from a demodulation circuit according to claim 9. UW detection means for detecting a unique word signal, which is a slot reception timing signal, from the demodulated data, and a reception signal strength output from the reception signal strength detection means and a UW detection signal output from the UW detection means. And an offset detection control means for generating an offset detection control signal for controlling the offset detection circuit, so that even in a wireless communication system using a modulated wave having a slot configuration, the offset detection control means is provided. , The offset of the received baseband signal can be corrected more accurately.

An offset correction circuit according to a tenth aspect is an offset correction circuit used in a receiver that receives and demodulates a predetermined modulated wave, wherein a detection means for detecting the received signal; Offset subtraction means for subtracting the offset correction signal from the reception baseband signal output from the means, and averaging or moving average the periodic signal in the reception baseband signal output from the offset correction means. And an offset detecting means for detecting the offset of the received baseband signal and outputting the offset corrected signal to the offset correcting means, so that the offset of the received baseband signal can always be accurately corrected. it can.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an offset correction circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an offset correction signal generated by an offset detection circuit 110 shown in FIG.

FIG. 3 is a configuration diagram showing a configuration of an offset detection circuit 110 of the offset correction circuit according to one embodiment of the present invention.

4 is a diagram illustrating an example of a relationship between an average signal generated by an averaging circuit 210 illustrated in FIG. 3 and a received baseband signal.

FIG. 5 is a configuration diagram showing a configuration of an offset detection circuit 110 according to another embodiment of the offset correction circuit of the present invention.

FIG. 6 is a diagram showing an offset correction circuit according to an embodiment of the present invention, in which an offset-corrected reception baseband signal when an average signal after holding output from a holding circuit 220 is used as an offset correction signal, and a filtering circuit 23;
FIG. 7 is a diagram illustrating an example of a received baseband signal after offset correction when a filtered average signal output from 0 is used as an offset correction signal.

FIG. 7 is a configuration diagram showing a configuration of an embodiment of an offset detection circuit 110;

8 is a diagram showing an example in which the moving average signal output from the moving average circuit 240 shown in FIG. 7 is used as an offset correction signal, and the received baseband signal after offset correction and the moving average signal after holding output from the holding circuit 220 are offset corrected. FIG. 4 is a diagram illustrating an example of a reception baseband signal after offset correction when the signal is a signal.

9 shows a received baseband signal, an average signal after holding output from a holding circuit 220 shown in FIG. 2, and an output from a moving average circuit 240 according to claim 4, when the offset of the received baseband signal changes rapidly. FIG. 4 is a diagram showing an example of a moving average signal to be performed.

FIG. 10 is a configuration diagram showing a configuration of an embodiment of an offset detection circuit 110;

11 is a moving average circuit 240 shown in FIG. 7 or FIG.
1 is a configuration diagram showing a configuration of one embodiment.

12 is a diagram illustrating an example of an operation of the moving average circuit 240 illustrated in FIG.

FIG. 13 is a configuration diagram illustrating a configuration of an embodiment of an offset detection circuit 110;

FIG. 14 is a diagram illustrating an example of a signal having periodicity in a received baseband signal.

FIG. 15 is a configuration diagram illustrating a configuration of an embodiment of an offset correction circuit.

16 is a diagram illustrating an example of a slot reception timing detection operation in the offset correction circuit illustrated in FIG. 15;

FIG. 17 is a configuration diagram illustrating a configuration of an embodiment of an offset correction circuit.

18 is a diagram illustrating an example of a slot reception timing detection operation in the offset correction circuit illustrated in FIG. 17;

FIG. 19 is a configuration diagram illustrating a configuration of an embodiment of an offset correction circuit.

20 is a diagram illustrating an example of an erroneous detection operation of a slot reception timing in the offset correction circuit illustrated in FIG. 15 and an erroneous detection operation of a slot reception timing in the offset correction circuit illustrated in FIG. 17;

FIG. 21 is a configuration diagram illustrating an embodiment of an offset correction circuit.

FIG. 22 is a configuration diagram illustrating a configuration of a conventional offset correction circuit.

FIG. 23 is a diagram showing an offset correction operation of a received baseband signal by a conventional offset correction circuit.

[Explanation of symbols]

110 offset detection circuit, 210 averaging circuit,
210A average circuit, 210B average circuit, 210L
Averaging circuit, 220 holding circuit, 230 filtering circuit, 240 moving average circuit, 260 periodic signal offset subtraction circuit, 270 multiplexing circuit, 80
0 detection circuit, 810 offset subtraction circuit, 82
0 analog / digital conversion circuit, 830 demodulation circuit, 840 offset detection circuit, 850 identification data addition addition circuit, 860 digital / analog conversion circuit, 870 addition data storage / hold register, 8
80 Averaging circuit.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Nobuhisa Kataoka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (10)

[Claims] 1. An offset correction circuit used in a receiver for receiving and demodulating a predetermined modulated wave, comprising: a detection unit for detecting a received signal; and a reception baseband signal output from the detection unit. Find the average of the periodic signal inside,
An offset detection unit for detecting an offset which is a DC component of the reception baseband signal, and an offset subtraction unit for subtracting an offset correction signal output from the offset detection unit from the reception baseband signal. Offset correction circuit. 2. The time averaging means for averaging the periodic signal for an integral multiple of the period, and a holding means for holding an average signal output from the time averaging means. The offset correction circuit according to claim 1, further comprising: 3. The moving average means for calculating a moving average value of the periodic signal for an integral multiple of the period, and an offset detecting means for holding a moving average signal output from the moving average means. The offset correction circuit according to claim 1, further comprising a holding unit. 4. The offset correction circuit according to claim 2, wherein said offset detecting means includes a filtering means for removing a high frequency component of a signal output from said holding means. 5. The moving averaging means according to claim 1, wherein
4. The apparatus according to claim 3, further comprising: two or more averaging means for averaging for an integral multiple of the period, and multiplexing means for multiplexing an average signal output from the averaging means. 4. The offset correction circuit according to 4. 6. The apparatus according to claim 2, wherein said offset detecting means includes a periodic signal offset subtracting means for subtracting an offset which is a DC component of the periodic signal from said output signal. Offset correction circuit. 7. A received signal strength detecting means for detecting the strength of the received signal, and an offset for generating an offset detection control signal for controlling the offset detecting means based on the received signal strength outputted from the received signal strength detecting means. The offset correction circuit according to claim 1, further comprising a detection control unit. 8. A demodulator for demodulating the offset-corrected received baseband signal output from the offset subtractor, and a unique word signal as a slot reception timing signal from demodulated data output from the demodulator. UW detection means for detecting an offset detection control means for generating an offset detection control signal for controlling the offset detection means using a UW detection signal output from the UW detection means, The offset correction circuit according to any one of claims 1 to 6. 9. A received signal strength detecting means for detecting the strength of the received signal, a demodulating means for demodulating the offset-corrected received baseband signal outputted from the offset subtracting means, and a signal outputted from the demodulating means. UW detection means for detecting a unique word signal, which is a slot reception timing signal, from demodulated data to be received, the reception signal strength output from the reception signal strength detection means,
4. An offset detection control means for generating an offset detection control signal for controlling said offset detection means using a UW detection signal output from said W detection means. 6. The offset correction circuit according to any one of 6. 10. A reception signal strength detection means for detecting the strength of the reception signal, a demodulation means for demodulating the offset-corrected reception baseband signal output from the offset subtraction means, and an output signal from the demodulation means. UW detection means for detecting a unique word signal as a slot reception timing signal from demodulated data to be received, a reception signal strength output from the reception signal strength detection means, and a UW detection signal output from the UW detection means And an offset detection control means for generating an offset detection control signal for controlling the offset detection means using the offset correction circuit.