JPH10270699A - Thin film transistor, liquid crystal display device and CMOS circuit using the same - Google Patents

Abstract

(57) Abstract: A TFT capable of suppressing a local temperature rise due to self-heating and improving reliability without increasing the number of manufacturing steps, and an active matrix using the TFT in a drive circuit and the like. An object of the present invention is to provide a liquid crystal display device including a substrate. SOLUTION: An offset region 7 is formed between a source / drain region 8 of the TFT and a channel region 5 (a portion facing an end of a gate electrode 4). A boundary portion 70 between the offset region 7 and the high-concentration source / drain region 8 has a source / drain region at the center in the channel width direction.
Since the offset region 7 extends toward the drain region 8, the offset region 7 has a structure in which the offset length Loffc at the central portion in the channel width direction is longer than the offset length offe at the edge portion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter, referred to as TFT) and a liquid crystal display device using an active matrix substrate provided with a driving circuit constituted by using the thin film transistor. For more information,
The present invention relates to a structure technology for suppressing a temperature rise due to self-heating of a TFT.

[0002]

2. Description of the Related Art FIG. 13 shows a plan view of a TFT having a self-aligned structure, which is widely used as an active matrix substrate for a liquid crystal display device.
As shown in FIG. 1C, a cross-sectional view taken along the line C ′ is a source including a channel region 5 facing the gate electrode 4 via the gate insulating film 2 and a high-concentration region connected to the channel region 5. Has a drain region 8; Here, conventionally, the gate electrode 4 is formed so as to have a substantially rectangular planar shape without protruding laterally (in the channel length direction). FIG. 14 shows a TFT having an offset structure.
As shown in FIG. 1A, a cross-sectional view taken along the line AA 'of FIG. 1 shows a gate insulating film on the end of the gate electrode 4 for the purpose of, for example, relaxing the electric field strength at the drain end. There may be a case where an impurity is not introduced, or an offset region 7 into which only the same amount of impurity as that of the channel region 5 is introduced by channel doping, in a portion facing through the second region 2. Even in this case, the boundary between the offset region 7 and the high-concentration source / drain region 8 is linear, and the offset length L in the channel width direction.
off is constant.

[0003]

However, the conventional structure of T
In the FT, if the current flowing through the TFT is increased to improve its characteristics and performance, the temperature rise in the channel region is large due to the self-heating of the TFT, and a local temperature rise is apt to occur. There is a problem that deterioration and reliability decrease occur.

[0004] Therefore, a layer having high thermal conductivity is added between the respective layers constituting the TFT, and this layer is used as a heat dissipation layer to form a TF.
A method of suppressing the temperature rise of T can be considered. However, according to this method, when manufacturing an active matrix substrate or the like, there is a problem that the number of steps of forming a film used as a heat dissipation layer and the step of patterning the film are increased. Such an increase in the number of manufacturing steps is not preferable because it increases the manufacturing cost of the active matrix substrate and the like.

[0005] In view of the above problems, an object of the present invention is to provide:
By improving the structure of the peripheral portion of the channel region, a TF capable of suppressing a local temperature rise due to self-heating and improving reliability without increasing the number of manufacturing steps.
An object of the present invention is to provide a liquid crystal display device including a T and an active matrix substrate using the T and a driving circuit.

[0006]

In order to solve the above-mentioned problems, according to the present invention, the structure around the channel region is improved as follows so that the temperature rise due to self-heating is small without increasing the number of manufacturing steps. TFT is realized. Here, each configuration is represented by taking an example in which an offset gate structure is adopted, but instead of the offset gate structure,
Even when the LDD structure is adopted, the same effect can be obtained with a similar configuration. In the case where such an LDD structure is adopted, in the following description, the offset region is set to L
Replaced with DD region (low concentration source / drain region)
The offset length is replaced with the LDD length.

First, a TFT according to the first type of the present invention
Then, a channel region facing the gate electrode via a gate insulating film, and a source region connected to the channel region.
In a TFT having a drain region and an offset region formed between at least one of the source / drain region and the channel region, the offset region has an offset length at a central portion in a channel width direction of an edge portion. It is characterized by being longer than the offset length.

Next, a TFT according to a second type of the present invention
Then, a channel region facing the gate electrode via a gate insulating film, and a source region connected to the channel region.
In a TFT having a drain region and an offset region formed between at least one of the source / drain region and the channel region, the offset region is formed only in a central portion in a channel width direction. Features.

When current flows in the channel region of the TFT and self-heats, the heat radiation from the edge portion in the channel width direction is large, so that the temperature rise is small, whereas the heat radiation is small in the central portion. Large temperature rise. However, the TFTs according to the first and second types have an offset region in the center portion in the channel width direction, while the edge portion has an extremely short offset length, or the offset length is 0, that is, with respect to the gate electrode. It is self-aligned. Therefore, the current tends to concentrate on the side of the edge portion in the channel width direction, so that the amount of heat generation is large at the edge portion, but the temperature rise is small due to good heat dissipation. On the other hand, the central portion in the channel width direction has poor heat dissipation, but the current flowing therethrough is small,
Since the calorific value is small, the temperature rise is small. Moreover, in order to form such a structure, it is only necessary to change the mask pattern when implanting impurity ions. Therefore, according to the present invention, it is possible to suppress the local temperature rise due to self-heating and increase the reliability of the TFT without increasing the number of manufacturing steps.

In the TFTs according to the first and second types, the boundary between the offset region and the source / drain region adjacent to the offset region is such that the central portion in the channel width direction is closer to the source / drain region. It is preferable to have a planar shape protruding so as to be curved toward. That is, the offset region does not protrude toward the source / drain region in an angular shape.
Therefore, the current distribution in the channel width direction draws a gentle curve, so that the current does not concentrate on a specific portion. Therefore, we suppress local temperature rise by self-heating,
The reliability of the TFT can be improved.

When such a configuration is employed, it is preferable that the width of the channel region is 50 μm or more. In the offset region, the offset length at the central portion in the channel width direction is preferably 2 μm or less, and more preferably in the range of 0.25 μm to 1.0 μm.

Next, a TFT according to a third type of the present invention will be described.
Then, a channel region facing the gate electrode via a gate insulating film, and a source region connected to the channel region.
In a TFT having a drain region and an offset region formed between at least one of the source / drain region and the channel region, a plurality of the offset regions and the source / drain regions are alternately arranged in a channel width direction. It is characterized by having.

With such a configuration, a current path in one TFT is divided in parallel. Therefore, since current does not concentrate on a specific portion, local temperature rise due to self-heating can be suppressed, and the reliability of the TFT can be improved. Moreover, such a structure requires only changing the mask pattern when implanting impurity ions, so that the number of manufacturing steps does not increase.

This configuration is made when the width of the channel region is, for example, 200 μm or less.

On the other hand, when the width dimension of the channel region is, for example, 200 μm or more, the following configuration may be adopted.

For example, the offset region is arranged to be unevenly distributed in a central portion in the channel width direction.
Alternatively, of the plurality of offset regions, the central offset region in the channel width direction may have a wider width than the offset region on the edge side. With this configuration, the first and second types of TF
As in T, the current tends to concentrate at the edges, so that the amount of heat generated is large, but the temperature rise is small due to good heat dissipation. On the other hand, the central portion in the channel width direction has poor heat dissipation, but the current flowing therethrough is small and the calorific value is small, so that the temperature rise is small. Moreover, in order to form such a structure, it is only necessary to change the mask pattern when implanting impurity ions. Therefore, according to the present invention, it is possible to improve the reliability by suppressing a local temperature rise due to self-heating without increasing the number of manufacturing steps.

Here, the offset region is configured such that the offset length is in a range from 0.2 μm to 2 μm, preferably in a range from 0.5 μm to 0.75 μm.

Next, a TFT according to a fourth type of the present invention will be described.
Then, a channel region facing the gate electrode via a gate insulating film, and a source region connected to the channel region.
In the TFT having a drain region, the gate electrode includes a bulging portion that bulges in a central portion in a channel width direction while bending in a channel length direction.

With this structure, the current is substantially the same as that of the first and second types of TFTs. At the edge portion in the channel width direction, the current tends to concentrate due to the short channel length, so that heat is generated. Although the amount is large, the temperature rise is small due to good heat radiation. On the other hand, in the central portion in the channel width direction, the current flowing therethrough is small and the calorific value is small due to the long channel length, so that the temperature rise is small. In addition, in the central portion in the channel width direction, the gate electrode made of a material having high thermal conductivity such as metal and having excellent heat dissipation is expanded. Temperature rise can be suppressed. Further, since the gate electrode has a square shape and does not protrude, the current distribution in the channel width direction draws a gentle curve, so that the current does not concentrate on a specific portion. Moreover, in order to form such a structure, it is only necessary to change a mask pattern when the gate electrode is formed by patterning. Therefore, according to the present invention, it is possible to improve the reliability by suppressing a local temperature rise due to self-heating without increasing the number of manufacturing steps.

The first to fourth types of TFTs configured as described above can be used as follows.

For example, first to fourth type TFTs
In such a case, these TFTs may be respectively configured as TFTs of the opposite conductivity type, and the TFTs of the opposite conductivity type may be interconnected to form a CMOS circuit.

In the first to third types of TFTs, these TFTs are each configured as a TFT of the opposite conductivity type, and the TFTs of the opposite conductivity type are interconnected to form a CMOS circuit. Since each TFT has an offset gate structure, the offset length of the N-type TFT may be longer than the offset length of the P-type TFT among the TFTs of the opposite conductivity type. With this configuration, if the TFTs have the same structure, even if the N-type TFT has a larger on-state current than the P-type TFT, the on-state current of these TFTs can be reduced by optimizing the offset length. You can balance.

In the first to fourth types of TFTs, the driving circuit constituted by them may be formed on an active matrix substrate of a liquid crystal display device.

Further, when a driving circuit composed of the first to third types of TFTs is formed on an active matrix substrate of a liquid crystal display device, each of the TFTs has an offset gate structure. It is preferable that the offset length of the TFT used as the pixel switching element is longer than the offset length of the TFT constituting the driving circuit. With this configuration, T
In the transfer characteristics of the FT, the off-leak current can be reduced for the TFT used as the pixel switching element, and the decrease in the on-current level can be suppressed for the TFT forming the drive circuit.

[0025]

Embodiments of the present invention will be described with reference to the drawings. In the following description, portions having common functions are denoted by the same reference numerals to avoid duplication of description.

[Embodiment 1] FIGS. 1A and 1B show
FIG. 2 is a vertical sectional view of a TFT having an offset gate structure, and FIG. 2 is a plan view of the TFT of the present embodiment. Here, FIG.
AA 'passing through the central portion in the channel width direction in FIG.
1B corresponds to a cross-sectional view taken along a line BB ′ passing through an edge portion in the channel width direction in FIG.

As shown in FIG. 1A, a TFT has a structure in which a gate electrode 4 made of a metal layer containing aluminum, tantalum, molybdenum, titanium, tungsten, or the like is formed on a glass substrate 50; The semiconductor device includes a channel region 5 facing via a gate insulating film 2 made of a silicon oxide film, and source / drain regions 8 connected to the channel region 5. This TFT has a structure in which a wiring layer 40 located on an upper layer side of an interlayer insulating film 52 made of a silicon oxide film is electrically connected to a high-concentration source / drain region 8 via a contact hole 9.
On the front side of the glass substrate 50, a base protective film 51 made of a silicon oxide film is formed.

In the TFT having such a structure, when the TFT is formed as an LDD structure or an offset gate structure, the withstand voltage is improved, so that the channel length can be shortened. The current can be reduced.

Therefore, in the TFT according to this embodiment, first,
No impurity is introduced between the source / drain region 8 and the channel region 5 (the portion facing the end of the gate electrode 4 via the gate insulating film 2), or the channel region is doped by channel doping. The offset region 7 into which only the same impurity as that of the impurity region 5 is introduced is formed.

Further, as shown in FIG. 2, a boundary portion 70 between the offset region 7 and the high-concentration source / drain region 8 adjacent to the offset region 7 has a central portion in the channel width direction at the source / drain region. It has a planar shape that protrudes so as to be curved toward 8.
Therefore, the offset region 7 has a structure in which the offset length Loffc at the center in the channel width direction is longer than the offset length offe at the edge. Therefore, the cross section taken along the line AA 'passing through the central portion in the channel width direction in FIG. 2 appears as shown in FIG. 1A, and the line BB' passing through the edge portion in the channel width direction in FIG. The cross section is shown in Fig. 1.
It appears as shown in (B).

Here, the offset area 7 has a width of 50
Since it is at least μm and relatively wide, a large on-current can flow, and ordinary photolithography technology is sufficient for forming a shape having a different offset length in the channel width direction. The offset length Loffc at the central portion in the channel width direction is set to 2 μm or less from the viewpoint of securing a high on-current. However, from the viewpoint of maximizing the advantage of the offset gate structure, the offset length Loffc is set to 0 μm or less. It is set within a range from .25 μm to 1.0 μm.

In the TFT according to the present embodiment configured as described above, the current tends to concentrate on the side of the edge portion in the channel width direction in the offset region 7 because the offset length offe is short. Although the part generates a large amount of heat, the temperature rise is small due to the good heat dissipation. On the other hand, the central portion in the channel width direction has a poor heat radiation property, but the offset length Loffc is long, the current flowing therethrough is small, and the calorific value is small, so that the temperature rise is small. Moreover, in order to form such a structure, it is only necessary to change a mask pattern when implanting impurity ions for forming the high concentration source / drain regions 8. Therefore, according to the present invention, it is possible to suppress the local temperature rise due to self-heating and increase the reliability of the TFT without increasing the number of manufacturing steps.

Further, in this embodiment, the offset region 7 protrudes so as to bulge toward the source / drain region 8, and does not protrude in an angular shape. Therefore, the current distribution in the channel width direction in the offset region 7 draws a gentle curve, so that the current does not concentrate on a specific portion. Therefore, local temperature rise due to self-heating can be suppressed, and the reliability of the TFT can be improved.

[Embodiment 2] FIGS. 1A and 1C are longitudinal sectional views of a TFT having an offset gate structure and a self-aligned structure, respectively, and FIG. 3 is a plan view of the TFT of the present embodiment. Here, FIG. 1A corresponds to a cross-sectional view taken along the line AA ′ passing through a central portion in the channel width direction in FIG.
FIG. 1C corresponds to a cross-sectional view taken along the line CC ′ in FIG. 3 passing through an edge portion in the channel width direction.

As shown in FIG. 1A, T according to this embodiment
The FT also has no impurity introduced between the source / drain region 8 and the channel region 5 (a portion facing the end of the gate electrode 4 via the gate insulating film 2).
Alternatively, an offset region 7 into which only the same impurity as that of the channel region 5 is introduced by channel doping is formed.

Further, as shown in FIG. 3, a boundary portion 70 between the offset region 7 and the source / drain region 8 adjacent to the offset region 7 has a central portion in the channel width direction closer to the source / drain region 8. And has a planar shape protruding so as to be curved toward. A boundary portion 70 between the offset region 7 and the source / drain region 8 overlaps the edge of the gate electrode 4 at the edge of the offset region 7. For this reason, the offset length is provided only between the source / drain region 8 and the channel region 5 (the portion facing the end of the gate electrode 4 via the gate insulating film 2) only in the central portion in the channel width direction. Is Lof
It has an offset area 7 of fc, and this offset area 7
The offset length is reduced from the central portion toward the edge portion, and the edge portion is self-aligned with the gate electrode 4. Therefore, the cross section taken along the line AA 'passing through the central portion in the channel width direction in FIG.
3, and a cross section taken along the line CC ′ passing through the edge portion in the channel width direction in FIG. 3 appears as shown in FIG.

Also in this case, the offset area 7 has a width of 5
Since the thickness is 0 μm or more and is relatively wide, a large on-current can flow, and ordinary photolithography technology is sufficient for forming a shape having a different offset length in the channel width direction. The offset length Loffc at the central portion in the channel width direction is set to 2 μm or less from the viewpoint of securing a high on-current. However, from the viewpoint of maximizing the advantage of the offset gate structure, the offset length Loffc is set to 0 μm or less. It is set within a range from .25 μm to 1.0 μm.

In the TFT according to the present embodiment having the above-described configuration, the offset region 7 is self-aligned on the side of the edge portion in the channel width direction.
Since the current tends to concentrate, a large amount of heat is generated, but the temperature rise is small due to the good heat dissipation. On the other hand, the central portion in the channel width direction has poor heat dissipation, but the longer the offset length Loffc, the smaller the current flowing therethrough.
Since the calorific value is small, effects similar to those of the first embodiment, such as a small rise in temperature, can be obtained.

[Embodiment 3] FIGS. 1A and 1C are longitudinal sectional views of a TFT having an offset gate structure and a self-aligned structure, respectively, and FIG. 4 is a plan view of the TFT of the present embodiment. Here, FIG. 1A corresponds to a cross-sectional view taken along line AA ′ passing through the offset region in FIG.
Is C passing through a position outside the offset area in FIG.
This corresponds to a cross-sectional view taken along line -C '.

As shown in FIG. 1A, T according to the present embodiment
The FT also has no impurity introduced between the source / drain region 8 and the channel region 5 (a portion facing the end of the gate electrode 4 via the gate insulating film 2).
Alternatively, the offset length in which only the same impurity as that of the channel region 5 is introduced by channel doping is Loff
Offset region 7 is formed.

However, as shown in FIG. 4, in this embodiment, the portion between the source / drain region 8 and the channel region 5 (the portion facing the end of the gate electrode 4 via the gate insulating film 2) And a plurality of offset regions 7 and high-concentration source / drain regions 8 are alternately provided in the channel width direction. In other words, the portion facing the end portion of the gate electrode 4 via the gate insulating film 2 is a source / drain region 8 in which both end portions in the channel width direction are self-aligned with the gate electrode 4, and from there toward the center portion. Thus, the offset regions 7 and the source / drain regions 8 are alternately arranged in parallel. Therefore, the cross section taken along the line AA 'passing through the offset region 7 at the center in the channel width direction in FIG.
4A, a cross section taken along the line CC 'passing through the source / drain region 8 at the edge portion in the channel width direction in FIG. 4, that is, a line CC' passing through a position outside the offset region 7. The cross section appears as shown in FIG.

Here, the channel region 5 has a width of 20
Although it is not more than 0 μm, it is still relatively wide from the viewpoint of the conventional TFT, so that a large on-current can flow, and even if a plurality of offset regions 7 are formed in the channel width direction, ordinary photolithography technology is sufficient. It is. Each of the offset areas 7 has a value of 0.
It is set within the range of 2 μm to 2 μm, but from the viewpoint of securing a high on-current and maximizing the advantages of the offset gate structure, 0.5
It is set in the range from μm to 0.75 μm.

In the TFT configured as described above, one T
The current path is divided in parallel in the FT. Therefore, since current does not concentrate on a specific portion, local temperature rise due to self-heating can be suppressed, and the reliability of the TFT can be improved. In addition, in order to form such a structure, it is only necessary to change the mask pattern when implanting impurity ions for forming the high concentration source / drain regions 8, so that the number of manufacturing steps does not increase.

[Modification of Third Embodiment] In the third embodiment, the width of channel region 5 is, for example, 200 μm.
In the case of m or more, it may be configured as follows.

For example, although not shown, when forming the plurality of offset regions 7, the width of the channel region 5, that is, the width of the source / drain region 8 is set to 20.
Utilizing the fact that the width is as large as 0 μm or more, the offset region 7 may be unevenly distributed in the central portion in the channel width direction.

Alternatively, as shown in a plan view of the TFT in FIG. 5, the width of the offset region 7 at the center in the channel width direction among the plurality of offset regions 7 is Woff1, and this width is the width of the edge region. The offset region 7 is configured to be considerably wider than the width dimension Woff2. here,
Since the channel region 5 has a considerably large width of 200 μm or more, a large on-current can flow and a plurality of offset regions 7 are formed in the channel width direction by ordinary photolithography technology. Each offset area 7 is 0.2 μm
In the range from 0.5 μm to 0.75 μm, from the viewpoint of securing a high ON current and maximizing the advantage of the offset gate structure, the following is set. Is set to

Also in the case of such a configuration, the source / drain region 8 has the same structure as the TFT according to the first and second embodiments.
Since the current tends to concentrate at the edge, the amount of heat generated is large, but the temperature rise is small due to the good heat dissipation. On the other hand, the central portion in the channel width direction has poor heat dissipation, but the current flowing therethrough is small and the calorific value is small, so that the temperature rise is small. Moreover, in order to form such a structure, it is only necessary to change the mask pattern when implanting impurity ions. Therefore, according to the present invention, it is possible to suppress a local temperature rise due to self-heating and improve reliability without increasing the number of manufacturing steps.

[Embodiment 4] FIG. 1C is a longitudinal sectional view of a TFT having a self-aligned structure, and FIG.
FIG.

As shown in FIG. 1C, T according to this embodiment
The FT also has a channel region 5 facing the gate electrode 4 via the gate insulating film 2 and a source / drain region 8 connected to the channel region 5, and the source / drain region 8 On the other hand, it is a high concentration source / drain region formed in a self-aligned manner. However,
As shown in FIG. 6, in the TFT of the present embodiment, the gate electrode 4 has a bulging portion 44 which bulges in a central portion in the channel width direction while curving in a triangular shape rounded in the channel length direction. .

In the TFT thus configured, the first, second,
Is substantially the same as the TFT according to the above-described embodiment, and at the edge portion in the channel width direction, the channel length Lche is shorter,
Since the current tends to concentrate, the calorific value is large, but the temperature rise is small due to the good heat dissipation. On the other hand, in the central portion in the channel width direction, the current flowing therethrough is small and the amount of heat generation is small because the channel length Lchc is long, so that the temperature rise is small. Moreover, in the central portion in the channel width direction, the gate electrode 4 made of a material having a high thermal conductivity such as a metal and having excellent heat dissipation is expanded. It is possible to suppress a rise in temperature in a part. Further, since the gate electrode has a square shape and does not protrude, the current distribution in the channel width direction draws a gentle curve, so that the current does not concentrate on a specific portion. Moreover, in order to form such a structure, it is only necessary to change a mask pattern when the gate electrode 4 is formed by patterning. Therefore, according to the present invention, it is possible to suppress the local temperature rise due to self-heating and increase the reliability of the TFT without increasing the number of manufacturing steps.

[Modification of Fourth Embodiment] In forming the bulging portion 44 which bulges in the central portion of the gate electrode 4 while curving in the channel length direction, as shown in FIG. A rounded triangular bulge 44 may be formed on only one of the four. In addition, as shown in FIG. 8A, the gate electrode 4 is formed in an elliptical shape, or as shown in FIG. 8B, the gate electrode 4 is formed in a circular shape, and the bulge is used as it is. 4 may be used as the bulging portion 44.

[Application Example to Active Matrix Substrate]
The case where the present invention is applied to an active matrix substrate for a liquid crystal display device will be described with reference to the drawings.

(Overall Configuration of Active Matrix Substrate)
FIG. 9A is a block diagram schematically illustrating a configuration of an active matrix substrate of a liquid crystal display device.

As shown in FIG. 9A, in an active matrix substrate for a liquid crystal display device, a data line 90 made of a metal film of aluminum, tantalum, molybdenum, titanium, tungsten or the like is formed on a transparent substrate made of glass or the like. And a pixel area defined by the scanning lines 91,
There is a liquid crystal capacitor 94 (liquid crystal cell) to which an image signal is input via the pixel TFT 30. For the data line 90, the shift register 84, the level shifter 8
5, a data side drive circuit 82 (data driver unit) including a video line 87 and an analog switch 86 is configured. For the scanning line 91, a scanning driver circuit 83 (scan driver unit) including a shift register 88 and a level shifter 89 is configured. In the pixel region, a storage capacitor 93 is formed between the pixel region and the preceding scanning line 91, and the storage capacitor 93 has a function of improving the charge holding characteristics of the liquid crystal capacitor 94.

(Basic Configuration of CMOS Circuit) In the driving circuits on the data side and the scanning side, as shown in FIG.
CMOS by the TFT 10 of P type and the TFT 20 of P type
The circuit is configured. Such a CMOS circuit has 1
An inverter circuit is composed of two or more stages.

As described above, the CMOS circuit is replaced with an N-type TF
In the case of being constituted by T10 and P-type TFT 20,
When the TFTs according to the first to fourth embodiments are used, high reliability can be obtained because there is no local heat generation even when a large current flows.

When the TFTs of the first to third embodiments are used, since each TFT has an offset gate structure, the channel length can be shortened by the higher withstand voltage. Etc. can be suppressed. In this case, the offset length of the N-type TFT 10 is
It is preferable that the length be longer than the offset length of the FT 20.
With such a configuration, even if the N-type TFT has a larger on-state current than the P-type TFT in the case of the TFTs having the same structure, by adjusting the offset length, these TFTs can be formed.
Can be balanced.

(TFT on Active Matrix Substrate)
Further, as shown in FIG. 9A, a pixel switching TFT 30 is formed in a pixel area defined by the data line 90 and the scanning line 91.
As for the TFT 30, the TFTs according to the first to fourth embodiments may be used.

Of the TFTs according to the first to third embodiments,
When the TFT is used, since each TFT has an offset gate structure, the off-leak current is small, so that a decrease in contrast, display unevenness, flicker, and the like can be prevented, and display quality can be improved. However, if the N-type and P-type drive circuit TFTs 10 and 20 have the same offset gate structure as the N-type pixel TFT 30 and reduce the off-leakage current, the on-state current becomes too small and the drive circuit TFTs are reduced. The operating speed decreases or the required power supply voltage increases. Such a reduction in the operation speed of the drive circuit has a problem that high-quality display is hindered in a liquid crystal display device. Further, an increase in required power supply voltage hinders a reduction in power consumption. Therefore, by optimizing the structure of the TFTs used for different applications on the same substrate, it is possible to reduce the off-leak current and secure a large on-current for the drive circuit TFT, and to obtain the off-leak current for the pixel TFT. From the viewpoint of reducing the number of pixels, the offset length of the TFT 30 used as the pixel switching element is configured to be longer than the offset length of the TFTs 10 and 20 forming the drive circuit. Conversely, TFTs that constitute the drive circuit
The offset lengths of 10 and 20 are configured to be shorter than the offset length of the TFT 30 used as a pixel switching element.

As described above, in the active matrix substrate with a built-in drive circuit of a liquid crystal display device, as shown in FIG. 10, approximately three types of TFTs 10, 20, and 30 are formed. In FIG. 10, an N-type driving circuit TFT 10, a P-type driving circuit TFT 20, and an N-type pixel TFT 30 are formed on the same insulating substrate 50 from the left region to the right region. The state is shown.

A description will be given of the fact that the number of steps does not increase even if the three types of TFTs 10, 20, and 30 are manufactured using the TFTs according to the first to third embodiments in the active matrix substrate having such a configuration. Here, in the TFTs according to the first to third embodiments, the offset gate structure has been described as an example, but the LDD having the low-concentration source / drain regions in the portion corresponding to the offset region 7 is described.
Since the same can be said for the structure, here, the case where all the TFTs are formed by the LDD structure will be basically described, and the offset gate structure will be described in the description. In the case where the three types of TFTs 10, 20, and 30 are formed by the TFTs according to the fourth embodiment, a normal self-aligned TFT is manufactured except for changing a mask pattern when patterning a gate electrode. Since this is the same as the case, the description is omitted.

First, as shown in FIG. 11A, a thickness of about 2000 to 5000 Å is formed on a glass substrate 50 by plasma CVD using TEOS (tetraethoxysilane), oxygen gas or the like as a source gas. A base protective film 51 made of a silicon oxide film is formed. Next, the temperature of the substrate 50 is set to 350 ° C.
A thickness of about 300 to 7 on the surface of
A semiconductor film made of a 00 Å amorphous silicon film is formed. Next, a crystallization step such as laser annealing or a solid-phase growth method is performed on the semiconductor film made of the amorphous silicon film to crystallize the semiconductor film to a polysilicon film. In the laser annealing method,
For example, a line beam having an excimer laser beam length of 400 mm is used, and its output intensity is, for example, 200 mJ.
/ Cm ² . The line beam is scanned such that a portion corresponding to 90% of the peak value of the laser intensity in the width direction overlaps in each region.

Next, the polysilicon film is patterned into island-like semiconductor films 11, 21, and 31. The surface thereof is formed by plasma CVD using TEOS (tetraethoxysilane) or oxygen gas as a source gas. Saga about 60
Gate insulating films 12, 22, and 32 made of a silicon oxide film of 0 to 1500 angstroms are formed (gate insulating film forming step).

Next, a conductive film containing aluminum, tantalum, molybdenum, titanium, tungsten, or the like is formed by a sputtering method.
The T gate electrodes 14, 24, 34 are formed (gate electrode forming step).

Next, as shown in FIG. 11B, the formation regions of the N-type driver circuit TFT 10 and the N-type pixel TFT 30 are covered with a resist mask 61. In this state, when boron ions are implanted at a dose of about 10 ¹³ cm ^-2 ,
A low-concentration P-type region 23 having an impurity concentration of about 10 ¹⁸ cm ^-3 is self-aligned with the gate electrode 24 in the silicon thin film 21.
Is formed. Note that a portion where the impurity is not introduced becomes the channel region 25.

If the low concentration impurity implantation step is not performed, the P-type drive circuit TFT 20 has an offset gate structure instead of an LDD structure.

Next, as shown in FIG. 11C, the region where the P-type drive circuit TFT 20 is to be formed is
Cover with. In this state, when phosphorus ions are implanted at a dose of about 10 ¹³ cm ⁻² , the silicon thin films 11 and 31 have a low impurity concentration of about 10 ¹⁸ cm ^{−3 in} a self-aligned manner with respect to the gate electrodes 14 and 34. N-type regions 13 and 33 are formed. Note that portions where the impurities are not introduced become the channel regions 15 and 35.

If the low concentration impurity implantation step is not performed, the N-type driving circuit TFT 10 and the N-type pixel TFT 30 have an offset gate structure instead of an LDD structure.

Next, as shown in FIG. 11D, in addition to the formation regions of the N-type drive circuit TFT 10 and the N-type pixel TFT 30, a resist mask 63 that covers the gate electrode 24 is also formed. I do. Here, the resist mask 6
3 is the high-concentration source shown in the first to third embodiments.
It is formed in such a pattern that the drain region 8 is formed. In this state, approximately 10 ¹⁵ cm ⁻²
Boron ions are implanted at a dose amount of ³ to form a high concentration source / drain region 26 having an impurity concentration of about 10 ²⁰ cm ⁻³ . The portion of the low-concentration P-type region 23 covered with the resist mask 63 remains as the LDD region 27 (low-concentration source / drain region). Thus P
The drive circuit TFT 20 is formed.

Next, as shown in FIG. 11E, a resist mask 64 is formed to cover the gate electrodes 14 and 34 in addition to the region where the P-type drive circuit TFT 20 is to be formed. Here, the resist mask 64 is also formed in a pattern such that the high-concentration source / drain regions 8 described in the first to third embodiments are formed. In this state, the low concentration N
Phosphorus ions are implanted into the mold regions 13 and 23 at a dose of about 10 ¹⁵ cm ⁻² to form high-concentration source / drain regions 16 and 36 having an impurity concentration of about 10 ²⁰ cm ⁻³ . The portion of the low-concentration N-type regions 13 and 23 covered with the resist mask 64 has an impurity concentration of about 10 ¹⁸ cm ^{−3 as it is.}
Remain as LDD regions 17 and 37 (low-concentration source / drain regions). Thus, the N-type driving circuit T
The FT 10 and the N-type pixel TFT 30 are formed.

Thereafter, as shown in FIG.
2 is formed, annealing for activation is performed, and after that, a contact hole is formed, and then source / drain electrodes 41, 42, 43, 44, and 45 are formed, whereby an active matrix substrate can be manufactured. Further, four mask forming steps for forming the resist masks 61, 62, 63, and 64 and four impurity introducing steps are performed.
Source / drain regions having an LDD structure are formed. That is, only by matching the pattern of the resist masks 63 and 64 to the shape of the high-concentration source / drain region 8 shown in the first to third embodiments, the TFTs according to these embodiments can be formed.
Can be manufactured without increasing the number of steps.

[Other Structures] The technique of improving the periphery of the channel region and improving the reliability of the TFT according to the present invention can be applied to the following cases. For example, since the edges of the channel region and the source / drain regions in the channel width direction are contaminated at the time of patterning, there is a case where it is desired to reduce the current flowing through the edges and concentrate the current in the central portion in the channel width direction. . In this case, as shown in FIG. 12A, contrary to the first and second embodiments, a portion between the source / drain region 8 and the channel region 5 (a portion facing the end of the gate electrode 4). Alternatively, the offset region 7 having a structure in which the offset length of the central portion in the channel width direction is considerably shorter than the offset length of the edge portion may be formed. In this case, the cross section taken along the line BB 'passing through the central portion in the channel width direction in FIG.
(B) and (C), the cross section taken along the line AA ′ passing through the edge portion in the channel width direction in FIG.
It appears as shown in (A). In the case of such a configuration, in the channel region 5 and the offset region 7 of the source / drain region 8, the current flowing therethrough can be suppressed to be small due to the long offset length at the edge portion in the channel width direction.

As shown in FIG. 12B, the gate electrode 4 may have a constricted portion 49 at the center in the channel width direction, contrary to the fourth embodiment. Also in the case of such a configuration, the channel region 5 has a longer channel length at the edge portion in the channel width direction,
The current flowing there can be reduced.

[0074]

As described above, according to the present invention, in any of the above-described TFTs, the structure of the peripheral portion of the channel region, such as the planar shape of the offset region and the planar shape of the gate electrode, is improved to improve the manufacturing process. The local temperature rise due to self-heating is suppressed without increasing the number.
Therefore, the reliability of the TFT can be improved.

[Brief description of the drawings]

FIGS. 1A and 1B are longitudinal sectional views of a TFT having an offset gate structure, and FIG. 1C is a longitudinal sectional view of a TFT having a self-aligned structure.

FIG. 2 is a plan view of the TFT according to the first embodiment of the present invention.

FIG. 3 is a plan view of a TFT according to a second embodiment of the present invention.

FIG. 4 is a plan view of a TFT according to a third embodiment of the present invention.

FIG. 5 is a plan view of a TFT according to a modification of the third embodiment of the present invention.

FIG. 6 is a plan view of a TFT according to a fourth preferred embodiment of the present invention.

FIG. 7 is a plan view of a TFT according to a modification of the fourth embodiment of the present invention.

FIGS. 8A and 8B are plan views of a TFT according to another modification of the fourth embodiment of the present invention.

9A is a block diagram schematically showing a configuration of an active matrix substrate of a liquid crystal display device, and FIG.
It is a circuit diagram of an S circuit.

FIG. 10 is a cross-sectional view of three types of TFTs formed on the active matrix substrate shown in FIGS. 9A and 9B.

11 is a process sectional view illustrating an example of the method for manufacturing the active matrix substrate illustrated in FIG.

FIG. 12 is a plan view of a TFT to which the present invention is applied.

FIG. 13 is a plan view of a conventional self-aligned TFT.

FIG. 14 is a plan view of a conventional TFT having an offset gate structure.

[Explanation of symbols]

 2, 12, 22, 32 Gate insulating film 4, 14, 24, 34 Gate electrode 5, 15, 25, 35 Channel region 16, 26, 36 High concentration source / drain region 7 Offset region 8, Source / drain region 9 Contact Hole 10, 20, 30 TFT 17, 27, 37 LDD region or offset region 40 Wiring layer 50 Glass substrate 51 Base protective film 52 Interlayer insulating film

Claims (19)

[Claims] A channel region opposed to a gate electrode via a gate insulating film; a source / drain region connected to the channel region; and a channel region between at least one of the source / drain region and the channel region. A thin film transistor having a formed offset region, wherein the offset region has a longer offset length at a central portion in a channel width direction than an offset length at an edge portion. 2. A channel region facing a gate electrode via a gate insulating film, a source / drain region connected to the channel region, and a channel between at least one of the source / drain region and the channel region. The thin film transistor having the formed offset region, wherein the offset region is formed only in a central portion in a channel width direction. 3. A boundary portion between the offset region and a source / drain region adjacent to the offset region, wherein a central portion in a channel width direction is directed toward the source / drain region. A thin film transistor having a planar shape protruding so as to be curved. 4. The thin film transistor according to claim 3, wherein the width of the channel region is 50 μm or more. 5. The thin film transistor according to claim 3, wherein the offset region has an offset length of 2 μm or less at a central portion in a channel width direction. 6. The thin film transistor according to claim 3, wherein the offset region has an offset length at a central portion in a channel width direction in a range from 0.25 μm to 1.0 μm. 7. A channel region facing a gate electrode via a gate insulating film, a source / drain region connected to the channel region, and a region between at least one of the source / drain region and the channel region. A thin film transistor having a formed offset region, comprising a plurality of said offset regions and said plurality of source / drain regions alternately in a channel width direction. 8. The thin film transistor according to claim 7, wherein the channel region has a width of 200 μm or less. 9. The thin film transistor according to claim 7, wherein the offset region is unevenly distributed in a central portion in a channel width direction. 10. The thin film transistor according to claim 7, wherein, of the plurality of offset regions, a central offset region in a channel width direction has a wider width than an edge-side offset region. 11. The thin film transistor according to claim 9, wherein the channel region has a width of 200 μm or more. 12. The offset region according to claim 7, wherein the offset region has an offset length of 0.2 μm.
Characterized in that the thickness of the thin film transistor is in the range from 1 to 2 μm. 13. The offset region according to claim 7, wherein the offset length of the offset region is 0.5 μm.
Characterized in that the thickness is in the range from 0.5 to 0.75 μm. 14. The thin film transistor according to claim 1, further comprising a low-concentration source / drain region in a region corresponding to the offset region. 15. A thin film transistor having a channel region facing a gate electrode via a gate insulating film, and a source / drain region connected to the channel region, wherein the gate electrode is located at a central portion in a channel width direction. A thin film transistor comprising a bulging portion that bulges while being curved in a channel length direction. 16. A CMOS comprising a thin film transistor having the structure defined in any one of claims 1 to 15, wherein each of the thin film transistors has a reverse conductivity type, and the thin film transistors of the opposite conductivity type are interconnected. circuit. 17. A CMOS circuit comprising a thin film transistor having the structure defined in any one of claims 1 to 14, wherein each of the thin film transistors has a reverse conductivity type, and the thin film transistors of the opposite conductivity type are interconnected. A CMOS circuit, wherein the offset length of the N-type thin film transistor is longer than the offset length of the P-type thin film transistor among the reverse conductivity type thin film transistors. 18. A liquid crystal display device using an active matrix substrate having a driving circuit constituted by a thin film transistor having a structure defined in any one of claims 1 to 15. 19. A pixel switching element and a driving circuit in a pixel region using the thin film transistor having the structure defined in any one of claims 1 to 14, and an offset length of the thin film transistor used as the pixel switching element. Wherein an active matrix substrate configured to be longer than an offset length of a thin film transistor forming the driving circuit is used.