JPH10269789A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can let a differential amplifier more quickly output a difference of a data signal from a main memory cell and a dummy data signal from a dummy cell. SOLUTION: A circuit pattern of a first and a second dummy memory cell arrays DMY1, DMY2 is made approximate as much as possible to that of a memory cell array MEM. In selecting a memory cell of the memory cell arrays, a matrix position of a main memory cell M, a matrix position of a dummy memory cell DM1 and a matrix position of a dummy memory cell DM2 are agreed with one another. Accordingly, time constants of signal transmission routes of the memory cells are agreed, so that a potential difference of either between a data signal line DL and a first reference voltage line RL1 or between the data signal line DL and a second reference voltage line RL2 can be output quickly from a differential amplifier SA.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device for reading a data signal from a memory cell, amplifying the data signal with a differential amplifier, and outputting the amplified signal.

[0002]

2. Description of the Related Art A semiconductor memory device of this type includes a memory cell array in which a plurality of memory cells are arranged in a matrix. One memory cell is selected from the matrix array, and a data signal is transmitted from the memory cell. read out. Since the level of the data signal from the memory cell is extremely low, the data signal is determined and output by comparing the data signal with a predetermined reference voltage.

FIG. 3 shows an example of a conventional semiconductor memory device. Here, each memory cell (transistor) M
Are arranged in a matrix to form a memory cell array MEM. The source of each memory cell M is grounded through a bit signal line B1 and the drain of each memory cell M is Signal line B2
And the bit signal line B2 is connected to the differential amplifier S through the column selection transistor CT1 and the data signal line DL.
Connected to A. The gate of each memory cell M is connected to a row decoder X-DEC through a row selection signal line WL for each row of the matrix arrangement.

The row decoder X-DEC sequentially selects each row of the matrix arrangement and applies a high potential to the gate of each memory cell M in the selected row. Each memory cell M stores "1" or "0" data depending on whether an impurity is implanted into its gate. When a high potential is applied to its gate, it turns off or on. , “1” or “0”
Output the data signal.

[0005] The column decoder Y-DEC is connected to each column select transistor CT1, CT2, CT through each column select signal line CS.
3. Select and turn on sequentially. When these column selection transistors CT1, CT2, CT3,... Are sequentially turned on, the data signal of each memory cell M in one row is sequentially applied to the differential amplifier SA through the data signal line DL.

The differential amplifier SA sequentially receives the data signals of the memory cells M in one row and simultaneously receives a reference voltage line R
A constant voltage REF of a constant voltage source is input through L, these data signals and the constant voltage REF are sequentially differentially amplified, and these data signals are sequentially output.

However, in such a semiconductor memory device, the resistance and the stray capacitance of the data signal transmission path of each memory cell M cannot be neglected, and are dependent on the time constant based on the resistance and the stray capacitance. Thus, the level of the data signal of the memory cell M fluctuates at the beginning of its output, which delays the output of the differential amplifier SA.

Therefore, a semiconductor memory device having a dummy memory cell array DMY and a dummy coder DMY-DEC as shown in FIG. 4 instead of the reference voltage source VREF has been proposed (see Japanese Patent Application Laid-Open No. 6-60676). .

The dummy memory cell array DMY has one column of each dummy memory cell DM. These dummy memory cells DM are always off regardless of the potential of their gates, and output a dummy data signal of "1".

Here, when a high potential is applied to the gate of each memory cell M in one row by the row decoder X-DEC, a high potential is also applied to the gate of the dummy memory cell DM in the same row. When the column decoder Y-DEC turns on the column selection transistor CT1, the dummy coder DMY-DEC turns on the column selection transistor CDT in response to this. Therefore, a data signal from any one of the memory cells M in one row (hereinafter, a data signal output from the memory cell M is referred to as a main data signal)
Is output, dummy data signals are output from the dummy memory cells DM in the same row, and the main data signal and the dummy data signal are applied to the data signal line DL and the reference voltage line RL.
Through the differential amplifier SA. Differential amplifier SA
Differentially amplifies the main data signal and the dummy data signal,
This main data signal is output.

The differential amplifier SA in the device shown in FIG. 4 is configured, for example, as shown in FIG. This differential amplifier S
A is interposed between the data signal line DL and the reference voltage line RL, and is connected to each of the P-channel transistors T on the power supply voltage Vcc side.
11, T12, N-channel transistors T21, T on the ground side
22 and an N-channel transistor T31 inserted between each of the N-channel transistors T21 and T22 and the ground, and constitutes a current mirror circuit. Each of the load transistors T is connected to the data signal line DL and the reference voltage line RL.
Current is supplied via LM and TLD.

Each time the column select transistor CT is turned on, the data signal line DL is connected to one of the memory cells M and is grounded through one memory cell M, or
It is not grounded, and accordingly, the potential of the data signal line DL becomes either a low potential or a high potential.

The reference voltage line RL is connected to a column selection transistor C
Each time DT is turned on, it is connected to one of the dummy memory cells DM. By appropriately setting the load of the load transistor TLD, the potential of the reference voltage line RL is set to an intermediate value between the low potential and the high potential of the data signal line DL.

When one of the memory cells M in one row is selected to output a main data signal, the dummy memory cell DM in the same row is selected.
The time constant of the signal transmission path from the data signal line DL to the data signal line DL is approximated to the time constant of the signal transmission path from the dummy memory cell DM to the reference voltage line RL. Fluctuations follow.

At this time, when the N-channel transistor T31 is turned on, the difference between the potential of the data signal line DL and the potential of the reference voltage line RL is promptly output from the differential amplifier SA.

As shown in FIG. 6, the first and second dummy memory cell arrays DMY1, DMY2 and the dummy coder D
A semiconductor memory device provided with MY-DEC has been proposed (see Japanese Patent Application Laid-Open No. Hei 3-24289).

The first dummy memory cell array DMY1 includes:
It has one column of dummy memory cells DM1, and keeps off regardless of the gate potential. The second dummy memory cell array DMY2 has one column of each dummy memory cell DM2, and when a high potential is applied to the gate thereof,
Turns on.

Here, when each row of memory cells M is selected by the row decoder X-DEC, each dummy memory cell DM1, DM2 of the same row is selected. When the column selection transistor CT1 is turned on by the column decoder Y-DEC, the dummy coder DMY-
The DEC turns on each column selection transistor CDT1, CDT2. Therefore, when a main data signal is output from any of the memory cells M in one row, each dummy data signal is output from each of the dummy memory cells DM1 and DM2 in the same row, and these main data signals and each dummy data are output. The signal is a data signal line DL and first and second reference voltage lines RL1, R2.
L2 is applied to the differential amplifier SA. The differential amplifier SA differentially amplifies any of the main data signal and each of the dummy data signals, and outputs the main data signal.

The differential amplifier SA in the device shown in FIG. 6 is configured as shown in FIG. In the differential amplifier SA, four N-channel transistors T41, T42, T43, T44 are provided instead of the N-channel transistors T21, T22 in the amplifier of FIG. 5, and the gates of the N-channel transistors T41, T42 are provided. The gate of each of the N-channel transistors T43, T44 is connected to the first and second reference voltage lines RL1, RL2.

Each time the column select transistor CT is turned on, the potential of the data signal line DL becomes either a low potential or a high potential.

Further, the first and second reference voltage lines RL1, R
L2 is the first and second column selection transistors CDT1, CDT
Each time T2 is turned on, their potential becomes high potential and low potential.

The differential amplifier SA has a data signal line DL
Is low, the difference between the low potential of the data signal line DL and the high potential of the first reference voltage line RL1 is amplified and output. When the data signal line DL is high, the difference between the high potential of the data signal line DL and The difference between the low potentials of the second reference voltage line RL2 is amplified and output.

As described above, the low potential of the data signal line DL and the first potential
Amplification of the difference between the high potential of the reference voltage line RL1 and amplification of the difference between the high potential of the data signal line DL and the low potential of the second reference voltage line RL2 may cause variations in the potential of the data signal line DL. Error of the output of the differential amplifier SA can be prevented. Further, each load transistor TLM,
TLA and TLB can be configured with the same size, and adjustment of these sizes is unnecessary.

[0024]

FIG. 8 shows a specific example of a conventional memory cell array MEM. Here, each memory cell M is placed between an odd column and an even column of the matrix arrangement of the memory cell array MEM.
Of the memory cell M is connected to each bit signal line B1 (hereinafter, referred to as a sub-bit signal line), and these sub-bit signal lines B1 are connected to each bank selection transistor. The main bit signal line M1 is connected to the main bit signal line MB1 via BT1 and BT2.
B1 is connected to a differential amplifier SA via a column selection transistor CT1.
Connected to Further, the source of each memory cell M is connected to each bit signal line B2 (hereinafter, referred to as a sub-bit signal line), and these sub-bit signal lines B2 are connected to the main bit signal lines via the bank selection transistors BT3 and BT4. MB2, and the main bit signal line MB2 is grounded via the column selection transistor CT2.

The memory cell array MEM has, for example, a structure as shown in FIG. 9 and is formed by laminating a conductive layer, a semiconductor layer, an insulating layer and the like on a substrate, and forms each sub-bit signal line and each main bit. It has a hierarchical structure in which bit signal lines are arranged in different layers.

In FIG. 1, each sub-bit signal line B1, B2
Are diffusion regions formed on the semiconductor substrate, and are arranged in the column direction and in parallel with each other. The row selection signal line WL and the bank selection signal line BS are formed of polysilicon or the like and are arranged in the row direction. Each main bit signal line MB
1, MB2 is a metal film, and each contact hole C1, C2
Are connected to the respective sub-bit signal lines B1 and B2.

Each of the sub-bit signal lines B1 and B2 serves as a source and a drain of each memory cell M, and each row selection signal line WL serves as a gate of each memory cell M.

Data is written into the memory cells M by implanting ions into the gates of the memory cells M. For example, in the case of a P-type semiconductor substrate, the source and drain of each memory cell M are set to high concentration N-type (N ⁺ ), and P-type impurity ions (boron or the like) are implanted into the gate of each memory cell M. Data is written to these memory cells M depending on whether or not the data is written. When ions are implanted into the gate of the memory cell M, even if a high potential is applied to the gate, the memory cell M is non-conductive (high threshold), and ions are implanted into the gate of the memory cell M. Otherwise, when a high potential is applied to the gate, the memory cell M conducts (low threshold).

As is clear from FIGS. 8 and 9, four columns each including the memory cells M are arranged to form one memory cell array MEM, and a plurality of memory cell arrays MEM are sequentially arranged. In one memory cell array MEM, a circuit pattern of a column differs for each column including the memory cells M, and the main cause is a main bit signal line and a bank selection transistor. Therefore, the time constant differs for each column of the memory cell array MEM.

Therefore, as shown in FIGS. 4 and 6, one column of each dummy memory cell D is arranged in the dummy memory cell array.
When only M is provided, it is not possible to cope with the time constant of the signal transmission path of each memory cell M for all the columns of the memory cell array MEM, resulting in a delay in the output of the differential amplifier SA.

Therefore, for example, as shown in FIG. 10, the first and second dummy memory cell arrays DMY1 and DMY2 are provided with the main bit signal line MB and the bank selection transistor BT, and the time constant of the column composed of each dummy memory cell DM is provided. May be corrected.

However, if there is only one column including each dummy memory cell DM, it is also difficult to deal with the time constant of the signal transmission path of each memory cell for all columns of the memory cell array MEM. Since only one main bit signal line MB and one bank selection transistor BT are provided, a circuit for driving the bank selection transistor BT cannot be shared with the main memory cell array MEM, and a dedicated circuit for the dummy memory cell array is required. This complicates the circuit configuration. Alternatively, since the main bit signal line MB cannot be shared with that of the main memory cell array MEM, if the first and second dummy memory cell arrays DMY1 and DMY2 are arranged between the main memory cell arrays MEM, the two memory cell arrays Each main bit signal line MB
After all, in order to avoid the complication, the first and second dummy memory cell arrays DMY1 and DMY2 must be arranged at both ends of each main memory cell array MEM as shown in FIG. Was. For this reason, the first and second dummy memory cell arrays DMY1 and DMY2 are arranged between the main memory cell arrays MEM to reduce the positional dependency of these dummy memory cell arrays, that is, the bias of the time constant due to the position. Could not.

The memory cell array M shown in FIGS.
In the EM, when data is written into the gate of the memory cell M by ion implantation (data writing process of the mask ROM), ions are also implanted into the source and drain of the memory cell M due to misalignment of mask alignment. Then, the resistance of each of the sub-bit signal lines B1, B2 fluctuates. This also causes a mismatch between the time constant of the column including the memory cells M and the time constant of the column including the dummy memory cells DM.

Therefore, an object of the present invention is to solve such a problem of the prior art, and a difference between a data signal from a main memory cell and a dummy data signal from a dummy memory cell is calculated by a differential amplifier. An object of the present invention is to provide a semiconductor memory device that can output data more quickly.

[0035]

According to a first aspect of the present invention, there is provided a main memory cell storing main data and a dummy memory cell storing dummy data. In a semiconductor memory device that reads main data and dummy data from dummy memory cells and determines and outputs main data by comparing these data, a main memory cell array in which a plurality of main memory cells are arranged in a matrix, A dummy memory cell array in which memory cells are arranged in a matrix is provided, and the circuit pattern of the main memory cell array and the circuit pattern of the dummy memory cell array are made substantially the same.

According to such a configuration, since the circuit pattern of the main memory cell array and the circuit pattern of the dummy memory cell array are substantially the same, main data can be transferred from the main memory cell at an arbitrary position in the matrix array of the main memory cell array. The time constant of the path for reading out and the time constant of the path for reading out dummy data from the dummy memory cell at the same position (the same position as the main memory cell) in the matrix array of the dummy memory cell array substantially match each other.

Therefore, in reading out the main data and reading out the dummy data to be compared with the main data, a matrix of the main memory cells from which the main data is read out in a matrix array of the main memory cell array is provided. If the position and the matrix position of the dummy memory cell for reading the dummy data in the matrix array of the dummy memory cell array are made to coincide with each other, the initial level fluctuations of the main data and the dummy data substantially match, and the comparison of these data shows Data can be quickly determined and output.

As described in claim 3, for each column in the matrix arrangement of the main memory cell array, each main memory cell is commonly connected to a sub-bit signal line, and the sub-bit signal line of each column is selected by a respective bank. The transistors may be connected to a main bit signal line via a transistor, and the gate of each bank select transistor may be commonly connected to a bank select signal line along the row direction in the matrix arrangement of the main memory cell array.

As described in claim 4, each dummy memory cell of the dummy memory cell array preferably stores mutually common dummy data. For example, each dummy memory cell of the dummy memory cell array stores "1" or "0" as common data.

According to a fifth aspect of the present invention, the same number of dummy memory cell arrays are provided in accordance with the type of data of the memory cell, and for each dummy memory cell array, each dummy memory cell is connected to each of the memory cells. Any of the types of data may be stored as mutually common dummy data.
For example, first and second dummy memory cell arrays are provided,
“1” is stored as common data in each dummy memory cell of the first dummy memory cell array, and “0” is stored as common data in each dummy memory cell of the second dummy memory cell array.

According to a sixth aspect of the present invention, the matrix direction in the matrix arrangement of the main memory cell array and the matrix direction in the matrix arrangement of the dummy memory cell array coincide with each other, and each signal line along the row direction is connected to each main memory cell. And the dummy memory cells.

As described in claim 7, a plurality of main memory cell arrays and at least one dummy memory cell array may be provided, and the dummy memory cell arrays may be arranged between the main memory cell arrays. For example, as set forth in claim 8, a row decoder for accessing each row in the matrix array of the main memory cell array and each row in the matrix array of the dummy memory cell array is further provided, and the row decoder and the main memory cell array are arranged in the same order. Subsequently, a dummy memory cell array is arranged between the main memory cell arrays including the main memory cell array. In this case, it is possible to reduce the positional dependence of these dummy memory cell arrays, that is, the deviation of the time constant due to the position.

[0043]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows an embodiment of the semiconductor memory device of the present invention. The semiconductor memory device of this embodiment includes each main memory cell array MEM and first and second dummy memory cell arrays DMY1 and DMY2.

Each main memory cell array MEM is provided with four columns of each main memory cell M, and the circuit patterns of these main memory cell arrays MEM coincide with each other.

In the main memory cell array MEM, each of the main memory cells M is arranged between an odd column and an even column of the matrix arrangement.
The directions of the source and the drain are inverted, and the drain of each main memory cell M is connected to each sub-bit signal line B1,
These sub-bit signal lines B1 are connected to a main bit signal line MB1 via bank select transistors BT1 and BT2, and the main bit signal line MB1 is connected to a column select transistor C1.
It is connected to a data signal line DL via T1, and this data signal line DL is connected to a differential amplifier SA. Further, the source of each main memory cell M is connected to each sub-bit signal line B2, and these sub-bit signal lines B2 are connected to the main bit signal line MB2 via the bank selection transistors BT3 and BT4. The signal line MB2 is grounded via the column selection transistor CT2.

Each row of the matrix array of such a main memory cell array MEM is selected, and a high potential is applied to the gate of each main memory cell M in the selected row. At this time, each bank selection transistor BT1, BT2, BT3, By turning on the BT4 and the column selection transistors CT1 and CT2 at respective timings, each column of the matrix arrangement can be sequentially selected, and the main memory cell M of each column in the selected row can be selected.
, The main data signal can be sequentially output.

However, the drains of the main memory cells M in the fourth column of the main memory cell array MEM are connected to the sub-bit signal line B1 together with the drains of the first column of the second main memory cell array MEM. . This sub-bit signal line B1 is connected to the main bit signal line MB1 of the second main memory cell array MEM. Therefore, in order to output a main data signal from the main memory cell M in the fourth column, it is necessary to turn on each bank selection transistor and each column selection transistor of both main memory cell arrays MEM at respective timings.

First and second dummy memory cell arrays DM
Y1 and DMY2 make their circuit patterns as close as possible to those of the main memory cell array MEM.

The first dummy memory cell array DMY1 (or the second dummy memory cell array DMY2) is provided with four columns each including the dummy memory cells DM, and is provided between the odd columns and the even columns of the matrix arrangement. The directions of the source and the drain of the dummy memory cell DM are inverted, the drain of each dummy memory cell DM is connected to each sub-bit signal line B1, and these sub-bit signal lines B1 are connected via the bank selection transistors BT1 and BT2. It is connected to the main bit signal line MB1, and this main bit signal line MB1 is connected to the first reference voltage line RL1 (or
(Second reference voltage line RL2) and the first reference voltage line RL1
(Or the second reference voltage line RL2) is connected to the differential amplifier SA. Also, the source of each dummy memory cell DM is connected to each bit signal line B2, and these sub-bit signal lines B2 are connected to the main bit signal line MB2 via the bank selection transistors BT3 and BT4. Line M
B2 is grounded via the column selection transistor CT2.
Further, the drain of each dummy memory cell DM in the fourth column is connected to the sub-bit signal line B3, and this sub-bit signal line B3 is connected to the main bit signal line M via the bank selection transistor BT5.
B3, and connects the main bit signal line MB3 to the first reference voltage line RL1 (or the second reference voltage line RL1 via the column selection transistor CT3).
Reference voltage line RL2).

Each dummy memory cell DM1 of the first dummy memory cell array DMY1 remains off regardless of the potential of its gate. Therefore, when one of the dummy memory cells DM1 is selected and the dummy data of the selected dummy memory cell DM1 is output through the sub-bit signal line B1 and the main bit signal line MB1, the first reference voltage line RL1 goes high. Potential.

The second dummy memory cell array DMY
Each of the dummy memory cells DM2 is turned on when a high potential is applied to its gate. Therefore, when one of the dummy memory cells DM2 is selected and the dummy data of the selected dummy memory cell DM2 is output through the sub-bit signal line B1 and the main bit signal line MB1, the second reference voltage line RL2 becomes low. Potential.

On the other hand, each signal line in the row direction, that is, each row selection signal line WL, each column selection signal line CS, and each bank selection signal line BS are connected to each main memory cell array MEM, the first and second dummy memory cell arrays DMY1,. Shared between DMY2.

The differential amplifier SA is the same as that shown in FIG. 7, and when the data signal line DL has a low potential, the difference between the low potential of the data signal line DL and the high potential of the first reference voltage line RL1. Is amplified, and when the data signal line DL is at a high potential, the high potential of the data signal line DL and the second reference voltage line RL2
Is amplified and output.

In such a configuration, when each row of the matrix array of the main memory cell array MEM is selected and a high potential is applied to the gate of each main memory cell M in the selected row, the same is applied. A high potential is also applied to the first and second dummy memory cells DM1, DMY2.

At this time, one main memory cell array ME
In M, each bank selection transistor and each column selection transistor are turned on at each timing to sequentially select each column of the matrix arrangement, and to sequentially output a main data signal from each main memory cell M in the selected row. . Each time a main data signal is sequentially output from each main memory cell M, the data signal line DL goes to either a low potential or a high potential.

At the same time, the first dummy memory cell array DM
Also in Y1, each bank selection transistor and each column selection transistor are turned on at each timing,
Each column of the matrix arrangement is sequentially selected, and a dummy data signal is sequentially output from each dummy memory cell DM1 in the selected row. Each time a dummy data signal is sequentially output from each dummy memory cell DM1, the first reference voltage line RL
1 becomes high potential. Similarly, also in the second dummy memory cell array DMY2, each column of the matrix arrangement is sequentially selected, and each dummy memory cell DM2 in the selected row is selected.
To output dummy data signals sequentially. Each time a dummy data signal is sequentially output from each dummy memory cell DM2, the second reference voltage line RL2 becomes low potential.

Each time each column of the matrix arrangement is selected, the differential amplifier SA selects one of the potential of the data signal line DL, the high potential of the first reference voltage line RL1, and the low potential of the second reference voltage line RL2. Are differentially amplified, and the difference between them is output as a main data signal.

For example, when the main memory cell M in the first row and first column is selected in the main memory cell array MEM, the first and second dummy memory cell arrays DMY1 and DMY1
In MY2 as well, each dummy memory cell DM1, DM2 in the first row and first column is selected. The data signal line DL has a low potential according to the main data signal of the main memory cell M, the first reference voltage line RL1 has a high potential according to the dummy data of the dummy memory cell DM1, and the dummy data of the dummy memory cell DM2 , The second reference voltage line RL2 becomes low potential. The differential amplifier SA has a first potential different from the low potential of the data signal line DL and the low potential of the data signal line DL.
The high potential of the reference voltage line RL1 is differentially amplified, and the difference is output as a main data signal.

Thereafter, the same operation is sequentially performed for the first row, second column to fourth column of the matrix arrangement. Further, when sequentially selecting each column of each of the other memory cell arrays MEM, the first and second dummy memory cell arrays DM
Each column of Y1 and DMY2 is sequentially selected, and each time each column is selected, the differential amplifier SA differentially amplifies the potential of the data signal line DL and the potential of one of the first and reference voltage lines RL1 and RL2. Then, the difference is output as a main data signal. Of course, the same operation is repeated for the other rows.

As described above, the circuit patterns of the first and second dummy memory cell arrays DMY1 and DMY2 are made as close as possible to those of the main memory cell array MEM, and when selecting the memory cells of these memory cell arrays, the main memory cell M , The matrix position of the dummy memory cell DM1, and the matrix position of the dummy memory cell DM2 match each other, so that the data signal lines DL,
The time constants of the respective signal transmission paths leading to the first and second reference voltage lines RL1 and RL2 can be made to coincide with each other. From the differential amplifier SA, the potential of the data signal line DL and the first and second
The difference between the potentials of the reference voltage lines RL1 and RL2 is promptly output.

Since the circuit patterns of the main memory cell array MEM and the first and second dummy memory cell arrays DMY1 and DMY2 are similar to each other, when data is written to the gate of the main memory cell M by ion implantation (the mask ROM Due to misalignment of the mask alignment, ions are also implanted into the source and drain of the memory cell, and each sub-bit signal line B
Even if the resistances of the first and second memory cells change, the fluctuations also occur in each of the main memory cell arrays MEM and the first and second dummy memory cell arrays DMY1 and DMY2, and the main memory cells M, the first and second memory cells DMY1 and DMY2 also change. Second dummy memory cell D
Variations in the time constants of the signal transmission paths of M1 and DM2 also occur. For this reason, the influence of this variation is caused by the difference amplifier SA
Offset by

In this embodiment, the first and second dummy memory cell arrays DMY1 and DMY2 are provided. However, even when one dummy memory cell array or three or more dummy memory cell arrays are provided, the present invention is not limited thereto. The invention can be applied.

When a plurality of dummy memory cell arrays are provided, as shown in FIG.
In the middle of the array of EMs, each dummy memory cell array DM
Y, it is preferable to insert a row decoder X-DEC. Thereby, the position dependency of each dummy memory cell array can be reduced.

[0064]

As described above, according to the present invention,
Since the circuit pattern of the main memory cell array and the circuit pattern of the dummy memory cell array are substantially the same, the time constant of the path for reading main data from the main memory cell at an arbitrary position in the matrix array of the main memory cell array and the dummy memory cell array The time constants of the paths for reading the dummy data from the dummy memory cells at the same position (the same position as the main memory cell) in the matrix arrangement substantially match each other.

Therefore, when the main data is read and the dummy data to be compared with the main data is read, the matrix position of the main memory cell from which the main data is read in the matrix array of the main memory cell array and the matrix array of the dummy memory cell array If the matrix positions of the dummy memory cells from which the dummy data is read are matched with each other, the initial level fluctuations of the main data and the dummy data substantially match, and the comparison of these data promptly determines and outputs the main data. be able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a schematic diagram showing a modification of the semiconductor memory device of FIG. 1;

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory device;

FIG. 4 is a circuit diagram showing another example of a conventional semiconductor memory device.

FIG. 5 is a circuit diagram showing a differential amplifier in the device of FIG.

FIG. 6 is a circuit diagram showing another example of a conventional semiconductor memory device.

FIG. 7 is a circuit diagram showing a differential amplifier in the device of FIG. 6;

FIG. 8 is a circuit diagram specifically showing a conventional memory cell array.

FIG. 9 is a plan view showing the structure of a conventional memory cell array.

FIG. 10 is a circuit diagram showing a modification of the semiconductor memory device of FIG. 6;

FIG. 11 is a circuit diagram showing a modification of the semiconductor memory device of FIG. 10;

[Explanation of symbols]

B1, B2 Sub-bit signal line BT1, BT2, BT3, BT4, BT5 Bank select transistor CT1, CT2, CT3,... Column select transistor DL Data signal line DMY1 First dummy memory cell array DMY2 Second dummy memory cell array DM1, DM2 Dummy Memory cell M Memory cell MB1, MB2, MB3 Main bit signal line MEM Memory cell array RL1 First reference voltage line RL2 Second reference voltage line SA Differential amplifier X-DEC Row decoder

Claims (8)

[Claims] 1. A main memory cell storing main data and a dummy memory cell storing dummy data. The main data and the dummy data are read from the main memory cell and the dummy memory cell, and the main data is compared by comparing these data. A semiconductor memory device for determining and outputting data, comprising: a main memory cell array in which a plurality of main memory cells are arranged in a matrix; and a dummy memory cell array in which a plurality of dummy memory cells are arranged in a matrix. A semiconductor memory device in which a circuit pattern and a circuit pattern of a dummy memory cell array are substantially the same. 2. When reading main data and reading dummy data to be compared with the main data, a matrix position of a main memory cell from which main data is read in a matrix array of a main memory cell array and a matrix position of a dummy memory cell array in a matrix array of the dummy memory cell array. 2. The semiconductor memory device according to claim 1, wherein the matrix positions of the dummy memory cells from which the dummy data is read coincide with each other. 3. The main memory cells are commonly connected to sub-bit signal lines for each column in the matrix arrangement of the main memory cell array, and the sub-bit signal lines in each column are connected to the main bit signal via respective bank selection transistors. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to a line, and a gate of each bank selection transistor is commonly connected to a bank selection signal line along a row direction in a matrix arrangement of the main memory cell array. 4. The semiconductor memory device according to claim 1, wherein each dummy memory cell of said dummy memory cell array stores mutually common dummy data. 5. A method according to claim 1, further comprising: providing a plurality of dummy memory cell arrays in accordance with the type of data of the memory cell, wherein each dummy memory cell stores one of data of each type of memory cell for each dummy memory cell array. 5. The semiconductor memory device according to claim 4, wherein said semiconductor memory device is stored as mutually common dummy data. 6. The matrix direction in the matrix arrangement of the main memory cell array and the matrix direction in the matrix arrangement of the dummy memory cell array are made to coincide with each other, and each signal line along the row direction is connected between each main memory cell and each dummy memory cell. 6. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is shared. 7. The semiconductor memory device according to claim 1, comprising a plurality of main memory cell arrays and at least one dummy memory cell array, wherein the dummy memory cell arrays are arranged between the main memory cell arrays. And a row decoder for accessing each row in the matrix array of the main memory cell array and each row in the matrix array of the dummy memory cell array, wherein the row decoder and the main memory cell array are arranged in the same order;
8. A dummy memory cell array is interposed between each main memory cell array including the main memory cell array.
3. The semiconductor memory device according to claim 1.