JPH10268838A - Liquid crystal display - Google Patents

Abstract

(57) Abstract: Provided is a liquid crystal display device in which the frequency of a clock signal sent to a driving unit is reduced without increasing the bus width of a display data bus line. SOLUTION: A liquid crystal display panel (10), driving means (130) for applying a video voltage to a plurality of pixels in a column direction,
While sending the input display data to the driving means,
A liquid crystal display device comprising: a display control unit (110) that generates a control signal including at least a clock signal based on an input display control signal that is input, sends the control signal to a driving unit, and controls and drives the driving unit. , The display control means sends a plurality of clock signals having the same frequency but different phases to the driving means, and the driving means generates a multiplied clock signal whose frequency is multiplied based on the plurality of clock signals. And a storage means for storing display data sent from the display control means based on the multiplied clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and, more particularly, to a technology effective when applied to increase the resolution of a liquid crystal display panel.

[0002]

2. Description of the Related Art A liquid crystal display device includes a simple matrix-type liquid crystal display device for driving pixels at intersections of stripe-shaped XY electrodes, and an active element (for example, a thin film transistor) for each pixel.
And an active matrix type liquid crystal display device that switches and drives the active elements.

As this active matrix type liquid crystal display device, a liquid crystal display panel (TFT-LCD), a drain driver disposed on the upper side of the liquid crystal display panel, a gate driver and an interface section disposed on the side of the liquid crystal display panel are provided. There is known a TFT type liquid crystal display module including

In the TFT type liquid crystal display module, the liquid crystal display panel has a plurality of pixels formed in a matrix, and each pixel has a thin film transistor.

The drain electrode of the thin film transistor in each pixel in the column direction is connected to a drain signal line, and each drain signal line is connected to a drain driver for applying a video voltage (display data voltage) to the liquid crystal of the pixel in the column direction. Is done.

The gate electrode of the thin film transistor in each pixel in the row direction is connected to a gate signal line. Each gate signal line is connected to the gate of the thin film transistor for one horizontal scanning time by a positive bias voltage or a negative bias voltage. Connected to the gate driver that supplies the voltage.

In this TFT type liquid crystal display module, the interface section comprises a display control device and a power supply circuit. The power supply circuit is a drain driver,
A driving voltage to be applied to a gate driver and a common electrode of the liquid crystal display panel is generated.

The display control device is composed of a single semiconductor integrated circuit (LSI), and includes a clock control signal, a display timing signal, a horizontal synchronizing signal, a vertical synchronizing signal, a display control signal, and a display signal transmitted from the main computer. It controls and drives the drain driver and the gate driver based on the application data.

[0009] The drain driver, based on a display data latch clock signal (D2) (hereinafter referred to as a clock signal (D2)) sent from the display control device, outputs display data by the number of input registers in the number of output registers. Latch. Also, based on the output timing control clock signal (D1) sent from the display control device, the display data latched in the input register unit is latched in the storage latch unit, and further latched in the storage latch unit. The video voltages corresponding to the respective display data are output to the respective drain signal lines (D) of the liquid crystal display panel.

The gate driver transmits a frame start instruction signal and a clock signal (G) sent from the display control device.
Based on 1), a plurality of thin film transistors (TFTs) connected to each gate signal line (G) of the liquid crystal display panel are sequentially turned on every horizontal time in synchronization with the clock signal (G1).

By the above operation, an image is displayed on the liquid crystal display panel. Such a technique is described in, for example, Japanese Patent Application No. 8-24759.

[0012]

Conventionally, in a liquid crystal display device, it is required to increase the resolution of the liquid crystal display panel. For example, the resolution of the liquid crystal display panel is changed from 640 × 480 pixels in VGA display mode to SVGA display. The mode has been enlarged to 800 × 600 pixels.

However, in recent years, in a liquid crystal display device, with a demand for a larger screen of the liquid crystal display panel, the resolution of the liquid crystal display panel has been set to 102 in the XGA display mode.
4 × 768 pixels, 1280 × 10 in SXGA display mode
There are demands for 24 pixels, 1600 × 1200 pixels in the UXGA display mode, and higher resolution.

As the resolution of the liquid crystal display panel is increased, the display control device, the drain driver and the gate driver are also required to operate at high speed. In particular, a clock signal (a clock signal) output from the display control device to the drain driver is required. D2) and the operating frequency of the display data are greatly affected by the increase in speed.

For example, 640 × 48 in the VGA display mode
In a liquid crystal display panel of 0 pixels, a clock signal (D2) having a frequency of 25 MHz and a clock signal (D2) of 12.5 MHz (25 MHz) are used.
Display data at a frequency of (half of), and a liquid crystal display panel of 800 × 600 pixels in the SVGA display mode has 4 pixels.
0 MHz clock signal (D2) and 20M
The display data at a frequency of 50 Hz (half of 40 MHz) is a clock signal (D2) of a frequency of 65 MHz and 32.5 MHz (half of 65 MHz) in a liquid crystal display panel of 1024 × 768 pixels in the XGA display mode.
Display data of the frequency is required.

However, display data having a frequency of 32.5 MHz can be recognized by the drain driver.
The clock signal (D2) having a frequency of 65 MHz can be recognized by the drain driver because the clock signal (D2) is transmitted from the display control device to the drain driver via a signal line provided on the printed wiring board. Did not.

That is, the signal line provided on the printed wiring board is equivalent to an open-ended distributed constant line. However, when transmitting a clock signal (D2) having a frequency of 65 MHz through this open-ended distributed constant line. The waveform distortion becomes remarkable, and the drain driver cannot recognize the clock signal (D2).

As described above, in the conventional liquid crystal display device, when a high-resolution liquid crystal display panel is used in accordance with the enlargement of the screen of the liquid crystal display panel, the high frequency clock signal (D2) is transmitted from the display control device. There was a problem that the data could not be transferred to the drain driver.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a liquid crystal display device without increasing the bus width of a display data bus line. Another object of the present invention is to provide a technique capable of reducing the frequency of a clock signal sent to a computer.

Another object of the present invention is to provide a liquid crystal display device without using a special circuit or a delay circuit which is not suitable for high-speed operation in a driving means and minimizing a circuit change in the driving means. It is another object of the present invention to provide a technique capable of generating a clock signal whose frequency is multiplied from a clock signal sent to a driving unit.

The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0022]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A liquid crystal display panel having a plurality of pixels formed in a matrix, driving means for applying a video voltage based on display data to a plurality of pixels in a column direction, and transmitting input display data to the driving means. And a display control unit that generates a control signal including at least a clock signal based on the input display control signal that is input, sends the control signal to the driving unit, and controls and drives the driving unit. In the display device, the display control means sends a plurality of clock signals having the same frequency and different phases to the driving means, and the driving means outputs a plurality of clock signals having the same frequency and different phases from each other. Clock signal multiplying means for generating a multiplied clock signal whose frequency is multiplied based on Wherein comprising a storage means for storing display data sent from the display control means based on the multiplied clock signal.

The storage means includes a pre-latch section for storing display data sent from the display control means in synchronization with a fall (or a rise) of the multiplied clock signal generated by the clock signal multiplication means; A shift register unit for generating a data fetch signal in synchronization with a rising (or falling) time of the multiplied clock signal generated by the clock signal multiplying means; and a prelatch by the data fetch signal generated by the shift register unit An input latch unit for storing display data output from the unit.

The display control device sends display data to the driving means via two bus lines, and the storage means synchronizes with the falling edge of the multiplied clock signal generated by the clock signal multiplying means. And a first pre-latch unit for storing one of the two sets of display data sent from the display control means, and a first clock signal generated by the clock signal multiplying means synchronized with a rising edge of the multiplied clock signal. A second pre-latch unit for storing the other display data of the two systems of display data sent from the display control means; and a first data latch synchronized with a rising edge of a multiplied clock signal generated by the clock signal multiplying means. A first shift register unit for generating a capture signal, and a first shift register unit for generating a capture signal when a multiplied clock signal generated by the clock signal multiplying unit falls. A second shift register unit for generating a second data capture signal in anticipation, and display data output from the first pre-latch unit by the first data capture signal generated by the first shift register unit. And an input latch unit for storing display data output from the second pre-latch unit in response to a second data capture signal generated by the second shift register unit.

The plurality of clock signals include a first clock signal and a second clock signal having a phase different from that of the first clock signal.
Clock signal.

The clock signal multiplying means receives an AND circuit to which the first clock signal and the second clock signal are input, and inputs the first clock signal and the second clock signal. It is composed of a NOR circuit, and an OR circuit to which the AND circuit and the NOR circuit are input.

A liquid crystal display panel having a plurality of pixels formed in a matrix, a driving means for applying a video voltage based on display data to a plurality of pixels in a column direction, and transmitting input display data to the driving means. And a display control unit that generates a control signal including at least a clock signal based on the input display control signal that is input, sends the control signal to the driving unit, and controls and drives the driving unit. In the display device, the display control means sends a first clock signal and a second clock signal having the same frequency and a different phase as the first clock signal to the driving means, wherein the driving means A first pre-latch section for storing display data sent from the display control means in synchronization with a rise of the first clock signal; A second pre-latch unit for storing display data sent from the display control unit in synchronization with a falling edge of a clock signal, and generating a first data capture signal in synchronization with a rising edge of the second clock signal A first shift register unit, a second shift register unit that generates a second data capture signal in synchronization with a falling edge of the second clock signal, and a second shift register unit that generates the second data capture signal. Display data output from the first pre-latch section is stored by a first data capture signal, and output from the second pre-latch section by a second data capture signal generated by the second shift register section. And an input latch unit for storing display data.

The phase difference (θ) between a plurality of clock signals having the same frequency and different phases is 0 <θ <π or π <θ <2π.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[First Embodiment of the Invention] FIG. 1 is a block diagram showing a schematic configuration of a TFT type liquid crystal display module according to an embodiment of the present invention.

In the liquid crystal display module of the present embodiment, a drain driver 130 is disposed above a liquid crystal display panel (TFT-LCD) 10.
The gate driver 140 and the interface unit 1
00 is arranged.

The interface section 100 is mounted on an interface board, and the drain driver 130 and the gate driver 140 are also mounted on dedicated printed boards.

FIG. 2 is a diagram showing an equivalent circuit of one example of the liquid crystal display panel 10 shown in FIG.

As shown in FIG.
Has a plurality of pixels formed in a matrix. Each pixel has two adjacent signal lines (drain signal lines (D)
Alternatively, the gate signal line (G)) and two adjacent signal lines (the gate signal line (G) or the drain signal line (D)) are arranged in an intersecting region.

Each pixel has a thin film transistor (TFT). A source electrode of the thin film transistor (TFT) of each pixel is connected to a pixel electrode (not shown), and a liquid crystal is provided between the pixel electrode and a common electrode (Vcom). Since layers are provided,
A liquid crystal capacitor (CLC) is equivalently connected between the source electrode and the common electrode of the thin film transistor (TFT).

Further, an additional capacitance (CADD) is connected between the source electrode of the thin film transistor (TFT) and the gate signal line (G) in the preceding stage.

FIG. 3 is a diagram showing an equivalent circuit of another example of the liquid crystal display panel 10 shown in FIG.

In the example shown in FIG. 2, additional capacitance (CADD) is formed between the gate signal lines (G) and the source electrodes in all stages, but in the equivalent circuit of the example shown in FIG. Between the line (COM) and the source electrode (CST)
G) is different.

The present invention is applicable to both,
In the former method, the pulse of the gate signal line (G) in all stages jumps into the pixel electrode via the additional capacitance (CADD), whereas in the latter method, there is no jump, so that a better display is possible. .

The liquid crystal display panel 1 shown in FIG. 2 or FIG.
At 0, the drain electrodes of the thin film transistors (TFTs) of the pixels arranged in the column direction are respectively connected to the drain signal lines (D), and the drain signal lines (D) are connected to the liquid crystal of the pixels arranged in the column direction. Is connected to a drain driver 130 for applying a video voltage (display data voltage) to the drain driver 130.

The gate electrode of the thin film transistor (TFT) in each pixel arranged in the row direction is connected to a gate signal line (G).
Is connected to a gate driver 140 that supplies a positive bias voltage or a negative bias voltage to the gate of the thin film transistor (TFT) for one horizontal scanning time.

Here, the liquid crystal display panel 10 shown in FIG.
Is composed of 1024 × 3 × 768 pixels.

In the liquid crystal display module shown in FIG. 1, the interface unit 100 includes a display control device 110 and a power supply circuit 120.

The display control device 110 is composed of one semiconductor integrated circuit (LSI), and receives a clock signal (CK), a display timing signal (DTMG), and a horizontal synchronization signal (Hsyn) transmitted from the main computer.
c) The drain driver 130 and the gate driver 140 are controlled and driven based on each display control signal of the vertical synchronization signal (vsync) and the display data (R, G, B).

The power supply circuit 120 includes the positive voltage generation circuit 12
1, a negative voltage generation circuit 122, a common electrode (counter electrode) voltage generation circuit 123, a gate electrode voltage generation circuit 124, and a multiplexer 125.

Positive voltage generation circuit 121, negative voltage generation circuit 1
Each of the reference numerals 22 includes a series resistance voltage dividing circuit, and generates a gradation reference voltage of a positive voltage or a gradation reference voltage of a negative voltage.

The multiplexer 125 is provided for the display control device 1
The output voltage from the positive voltage generation circuit 121 or the output voltage from the negative voltage generation circuit 122 is switched and output to the drain driver 130 in accordance with the AC signal (AC timing signal; M) from 10.

The common electrode voltage generation circuit 123 applies a drive voltage applied to the common electrode to the gate electrode voltage generation circuit 12.
Reference numeral 4 generates a driving voltage (positive bias voltage and negative bias voltage) applied to the gate of the thin film transistor (TFT).

FIG. 4 is a block diagram showing a schematic configuration of the drain driver 130 of the present embodiment.

As shown in FIG.
0 has a logic circuit section 151, a shift register section 152, a pre-latch section 153, an input latch section 154, a liquid crystal drive voltage generation section 155 having a storage latch section 156, a gradation voltage generation circuit 157, and a voltage bus 158.

The gradation voltage generation circuit 157 generates gradation voltages for 64 gradations based on the gradation reference voltage input from the positive voltage generation circuit 121 or the negative voltage generation circuit 122, and connects the voltage bus line 158. The voltage is output to the liquid crystal drive voltage generation unit 155 via the LCD.

FIG. 5 is a timing chart of a display control signal from the main computer shown in FIG. 1 and a control signal generated by the display control device 110.
FIG. 6 shows a timing chart of the clock signals (D3, D4) shown in FIG. 5 and a timing chart of the clock signal (D2) shown in FIG.

The horizontal operation of the liquid crystal display panel 10 shown in FIG. 1 will be described below with reference to FIGS. 4, 5 and 6.

When a display timing signal is input, the display control device 110 determines that the display timing signal is a display start position, and converts the simple one-row display data received from the main computer via the display data bus line 134. Output to the drain driver 130. In this case, the display data is transferred in units of one pixel, that is, each set of data of red (R), green (G), and blue (B) as one set.

At this time, the display controller 110 controls the first clock signal (D3) (hereinafter, referred to as the clock signal (D3)) and the first clock signal (D3) having the same frequency and different phase as the clock signal (D3). 2 clock signal (D4) (hereinafter referred to as
This is referred to as a clock signal (D4). ) To the signal line (131,
132) to the drain driver 130.
In this case, as shown in FIG. 6, the phase of the second clock signal (D4) is delayed by (π / 2) from the first clock signal (D3).

The clock signal (D3) and the clock signal (D4) can be easily generated by providing a circuit as shown in FIG. 7 in the display control device 110, for example.

In the circuit shown in FIG. 7, the clock signal (D3) (or the clock signal (D4)) is output from the D-type flip-flop circuit 111 in synchronization with the rise of the clock signal (CK) from the main computer. The clock signal (D4) (or the clock signal) is output from the D-type flip-flop circuit 112 in synchronization with the rise of the clock signal (CK) inverted clock signal (the fall of the clock signal (D3)). (D
3)) is output.

The logic circuit section 151 receives the clock signal (D
3) AND circuit 51 to which clock signal (D4) is input, clock signal (D3) and clock signal (D4)
, And an OR circuit 53 to which the AND circuit 51 and the NOR circuit 52 are input.

As shown in FIG. 6, the logic circuit 151
From the clock signal (D3) and the clock signal (D4),
A display data latch clock signal (D2) (hereinafter, referred to as a clock signal (D2)) having a frequency that is twice the frequency of the clock signals (D3, D4) is generated.

The shift register section 152 includes the logic circuit section 1
In synchronization with the rising edge of the clock signal (D2) from the input unit 51, a data capture signal for the input latch unit 154 is generated and output to the input latch unit 154.

The display data from the display control device 110 is
First, the signal is input to the pre-latch unit 153,
Reference numeral 53 latches display data in synchronization with the rise of the inverted clock signal of the clock signal (D2) (the fall of the clock signal (D2)).

The input latch section 154 receives a data fetch signal output from the shift register section 152,
In synchronization with the clock signal (D2), the pre-latch unit 110
6 bits of display data for each color are latched by the number of output lines.

In this case, the carry output of the previous stage of the drain driver 130 is directly input to the carry input of the next stage drain driver 130, and the data latch operation of the drain driver 130 is controlled by the carry signal, thereby causing an incorrect display data. Is prevented from being written to the data latch unit.

The display control device 110 counts a predetermined number of clock signals after the display timing signal is input, thereby completing the input of the display timing signal or after the display timing signal is input. It is determined whether or not a predetermined time has passed. As a result, it is determined that one horizontal display data has been completed, and the output timing control clock signal (D1) is sent to the drain driver 130 via the signal line 133.
(Hereinafter, referred to as a clock signal (D1)).

The storage latch section 156 of the liquid crystal drive voltage generation section 155 operates according to the clock signal (D 1) from the display control device 110 to all input register circuits 156.
Latch the display data inside.

The liquid crystal driving voltage generation section 155 generates a gradation voltage of 64 gradations inputted through the voltage bus line 158 based on the display data and the AC signal (M) taken into the storage latch section 155. Select one of them and
Output to the drain signal line (D).

Next, the vertical operation of the liquid crystal display panel 10 shown in FIG. 1 will be described with reference to FIG.

When the first display timing signal is input after the vertical synchronizing signal is input, the display control device 110 determines that this is the first display line and sends it to the gate driver 140 via the signal line 142. It outputs a frame start instruction signal.

Further, the display control device 110 shifts the shift clock signal (G1) (G1) (G1) for sequentially selecting each gate signal line (G) of the liquid crystal display panel 10 every horizontal scanning time based on the horizontal synchronization signal. Hereinafter, the clock signal (G1)
Called. ) To the gate driver 1 via the signal line 141.
Output to 40.

The gate driver 140 is a conventionally known simple shift scan driver. Gate driver 140
When a frame start instruction signal (or a carry signal at the previous stage) is input, a clock signal (G1) is generated based on the clock signal (G1) input from the display control device 110.
A plurality of thin film transistors (TFT) connected to each gate signal line (G) of the liquid crystal display panel 10 in synchronization with 1)
Are sequentially turned on every horizontal time.

In general, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed, and as a result, an afterimage phenomenon is caused and the life of the liquid crystal layer is shortened.

In order to prevent this, in a conventional TFT type liquid crystal display module, the drive voltage applied to the liquid crystal layer is changed to an alternating current at a certain time interval (one line or one frame). Therefore, the display control device 110 outputs to the power supply circuit 120 an alternating signal (M) for converting the drive voltage applied to the liquid crystal layer into an alternating voltage at certain fixed time intervals.

Here, the term “alternating” means that the drain driver 130 is controlled based on the driving voltage of the common electrode (counter electrode).
, That is, the drive voltage applied to the pixel electrodes of the liquid crystal layer is changed to the positive voltage side / negative voltage side at regular time intervals.

As described above, according to the present embodiment, the 32.5 MHz clock signal (D3, D4), which is the same frequency as the display data, is transferred to the drain driver 130, and the frequency is changed inside the drain driver 130. Is 65
Since the display data latch clock signal (D2) of MHz is generated, the display data bus line 134 is generated.
It is possible to transfer clock signals (D3, D4) for latching display data from the display control device 110 to the drain driver 130 without increasing the bus width.

FIGS. 8 and 9 show the case where the resolution of the liquid crystal display panel was examined by the present inventor before the present embodiment.
FIG. 9 is a block diagram showing an example of a technique for transferring a high-frequency display data latch clock signal (D2) from the display control device 110 to the drain driver 130 in the case of 24 × 768 pixels.

In the method shown in FIG. 8, two bus lines 134a and 134b are provided as bus lines for display data, and the two bus lines (134a and 134b) are provided.
b) is connected to each drain driver 130, and display data for two pixels is input to the drain driver 130.

In the method shown in FIG. 9, two bus lines 134a and 134b are provided as display data bus lines, and the two bus lines (134a and 1b) are provided.
34b), the drain driver 130 is connected alternately,
The drain drivers 130 are simultaneously controlled.

The methods shown in FIG. 8 and FIG.
Two bus lines (1) are used as display data bus lines.
34a and 134b) (that is, the bus width of the display data bus line is doubled) and the frequency of the display data latch clock signal (D2) is 32.5 MHz (65 MHz).
z), the display control device 110 sends a display data latch clock signal (D
2) is transferred.

However, in the method shown in FIGS. 8 and 9, the bus width of the display data bus line is doubled (for example,
Since there are 36 (6 × 3 × 2) bits for 64 gradations and 48 (8 × 3 × 2) bits for 256 gradations,
There is a problem that the number of pins of the display control device 110 is increased and the printed wiring board on which the drain driver 130 is mounted is multi-layered and the area is increased, which causes a cost increase of the drain driver 130 and the printed wiring board.

Further, the resolution of the liquid crystal display panel is SX
In the case of 1280 × 1024 pixels in the GA display mode,
The frequency of the clock signal (D2) is 108 MHz, the frequency of the display data is 54 MHz, and the clock signal (D2) is
Even if the frequency of 2) is halved, it is as high as 54 MHz.

If the frequency of the clock signal (D2) is 2
If the frequency is 7 MHz (half of 54 MHz), it is possible to sufficiently transfer the data from the display control device 110 to the drain driver 130. In that case, however, it is necessary to provide four display data bus lines, and the bus line width is quadrupled. (For example, 72 (6 × 3 × 4) bits for 64 gradations and 96 (8 × 3 × 4) bits for 256 gradations), so that the display control device 110 has more pins and There is a problem that the printed wiring board on which the drain driver 130 is mounted is multi-layered and the area is enlarged, which causes an increase in the cost of the drain driver 130 and the printed wiring board.

Further, a circuit configuration for distributing display data to two or four bus lines is required for the display control device 110, which not only complicates the circuit configuration of the display control device 110 but also increases the cost. There was a problem that it became a factor.

However, according to the present embodiment, it is not necessary to increase the bus width of the display data bus line, the logic circuit 151 is provided in the drain driver 130, and the clock signal (D3) or the clock signal ( D
For 4), only one signal line needs to be added.
There is no increase in the number of pins of the display control device 110 and no increase in the number of layers and the area of the printed wiring board on which the drain driver 130 is mounted. Also, the drain driver 13
0 and the cost of the printed wiring board can be reduced.

The resolution of the liquid crystal display panel is 1024.
As another example of the method of transferring the high-frequency display data latch clock signal (D2) from the display control device 110 to the drain driver 130 in the case of × 768 pixels, the frequency of the clock signal (D2) is set to 32.5 MHz. (65M
Hz), and the drain driver 130 latches the display data at the rise and fall of the clock signal (D2).

According to this method, the frequency of the clock signal (D2) can be reduced without increasing the bus width of the display data bus line as in the methods shown in FIGS. .

However, the display data latch clock signal (inverted clock signal of the clock signal (D2) in FIG. 1) input to the pre-latch section 153 and the control clock signal (in FIG. 1
It is necessary to secure a predetermined timing between the clock signal (D2) and the clock signal (D2) in order to prevent timing racing. In the method of latching the display data at the rising and falling of the clock signal (D2), In the drain driver 130, a clock signal having a frequency twice the frequency of the clock signal (D2) is generated, or the clock signal (D2) is delayed by a delay circuit 159 for a predetermined time as shown in FIG. Shift register unit 1
52 must be entered.

In this case, the clock signal (D2) starts from the rising and falling of the clock signal (D2).
A special circuit is required to generate a clock signal having a frequency twice as high as the frequency of 2). FIG.
The design of the delay time of the delay circuit 159 shown in FIG.

Therefore, in the method of latching the display data at the rising and falling of the clock signal (D2), a special circuit is required inside the drain driver 130, or the delay time of the delay circuit 159 is designed. There was a problem that the burden was large for high-speed operation.

However, in this embodiment, no special circuit is required inside the drain driver 130, and there is no need to set a delay time of a delay circuit that is not suitable for high-speed operation.

In this embodiment, the case where the first and second clock signals (D3, D4) are used has been described. However, the first to n-th clock signals (D3, D4) are used. .. Dn), the clock signals (D3, D4,.
It is also possible to further reduce the frequency of Dn). In that case, the logic circuit unit 151 outputs the n clock signals (D
, D4... Dn) by a clock signal (D
2) needs to be generated.

[Second Embodiment of the Invention] FIG. 11 is a block diagram showing a schematic configuration of a drain driver 130 according to another embodiment of the present invention.

The drain driver 130 of the present embodiment
Has a configuration in which the logic circuit section 151 shown in FIG. 4 is omitted, and two pre-latch sections (153a, 153b) and two shift register sections (152a, 152b) are provided.

Here, the pre-latch section 153a latches the display data in synchronization with the rising of the clock signal (D3), and the pre-latch section 153b latches the rising of the inverted clock signal of the clock signal (D3) (clock signal). Display data is latched in synchronization with (at the fall of (D3)).

The shift register section 152a outputs a data fetch signal in synchronization with the rising edge of the clock signal (D4), and the shift register section 152b outputs the inverted clock signal of the clock signal (D4) at the rising edge of the clock signal (D4). A signal for capturing data is output in synchronization with the falling edge of the signal (D4).

The display data latched by the pre-latch section 153a is captured by the input latch section 154 in response to a data capture signal from the shift register section 152a.
The display data latched by the pre-latch unit 153b is captured by the input latch unit 154 according to a data capturing signal from the shift register unit 152b.

As described above, in this embodiment, the clock signal (D3) is used exclusively for the pre-latch units (153a, 153b), and the clock signal (D4) is used exclusively for the shift register units (152a, 152b). It is.

Also in the present embodiment, clock signals (D3, D4) for latching high-frequency display data without increasing the bus width of the display data bus line.
Can be transferred from the display control device 110 to the drain driver 130.

[Embodiment 3] FIG. 12 is a block diagram showing a schematic configuration of a drain driver 130 according to another embodiment of the present invention.

FIG. 13 shows display data and a clock signal (D
(3, D4).

In the present embodiment, two bus lines of display data A and display data B are provided as display data bus lines.
It is provided with two pre-latch sections (153a, 153b) and two shift register sections (152a, 152b). Here, the display data A and the display data B have the same frequency, and the phase of the display data B is delayed by (π / 2) from the display data A.

The pre-latch unit 153a is connected to the logic circuit unit 15
The display data A is latched when the inverted clock signal of the clock signal (D2) rises from 1 (when the clock signal (D2) falls), and the pre-latch unit 153b
Latches the display data B in synchronization with the rise of the clock signal (D2).

The shift register section 152a outputs a data capture signal in synchronization with the rising edge of the clock signal (D2), and the shift register section 152b outputs the inverted clock signal of the clock signal (D2) at the rising edge of the clock signal (D2). At the time of the fall of the signal (D2)), a data capture signal is output.

The display data A latched by the pre-latch section 153a is latched by the input latch section 154 in response to a data latch signal from the shift register section 152a, and the display data B latched by the pre-latch section 153b is shifted by The data is input to the input latch unit 154 by a data input signal from the register unit 152b.

In the present embodiment, since two bus lines for display data are provided, the frequency of clock signals (D3, D4) for latching display data can be further reduced. .

[Embodiment 4] FIG. 14 is a view showing an external appearance of an example of a liquid crystal monitor device according to another embodiment of the present invention, and FIG. 15 is a liquid crystal display monitor of the present embodiment. FIG. 2 is a block diagram illustrating a schematic configuration of the device.

In FIG. 14, reference numeral 200 denotes a liquid crystal monitor device, 210 denotes a monitor cable, and 220 denotes a monitor connector. This embodiment is an embodiment in which the present invention is applied to a liquid crystal monitor device. The liquid crystal monitor device 200 of the present embodiment employs a digital interface as an interface with a personal computer.

[0109] In the present embodiment, LVDS (L ow V
oltage D ifferential S ignal
clock signal (CK), display timing signal (DTMG),
Horizontal synchronization signal (Hsync), vertical synchronization signal (vsync)
c) each display control signal and display data (R, G,
B) is sent out.

Therefore, as shown in FIG. 15, a transmitter (170a) composed of a semiconductor integrated circuit (LSI) is provided between the output stage of the graphic controller 180 on the computer main body side and the input stage of the display control device 110, respectively. , 170b) and receivers (160a, 160).
b) are provided.

The rest of the circuit configuration is the same as the circuit configuration shown in FIG. However, in FIG. 15, since the drawing is complicated, the signal line of the clock signal (D3) and the signal line of the clock signal (D4) are represented by the same signal line 135.

The transmitter 170a (or 1)
70b) is a 21-bit signal including a display timing signal (DTMG), a horizontal synchronization signal (Hsync), a vertical synchronization signal (vsync), and display data (R, G, B) from the graphic controller 180 in parallel. Serial conversion and three twisted pair receiver 160
a (or 160b).

The receiver 160a (or 160)
b) a serial-to-parallel conversion of the serial signal and a display control device for converting a display timing signal (DTMG), a horizontal synchronizing signal (Hsync), a vertical synchronizing signal (vsync) and display data (R, G, B) into a display control device Send to 110.

The clock signal (CK) is supplied to the transmitter 170a (or 170c) by a single twisted pair.
b) to the receiver 160a (or 160b).

The frequency of the serial signal on the three twisted pairs is seven times the frequency of the clock signal (CK).

In the present embodiment, the interface with the personal computer may be an analog interface. In this case, the LCD monitor device converts analog RGB video signals into digital signals. Needless to say, it needs to be converted into a signal.

Further, in each of the above embodiments, the present invention is applied to T
The case where the present invention is applied to the FT type liquid crystal display device has been described, but the present invention is not limited to this.
It goes without saying that the present invention can be applied to an N-type simple matrix liquid crystal display device.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the gist of the present invention. .

[0119]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, in a liquid crystal display device having a high-resolution liquid crystal display panel, the frequency of a clock signal sent to a driving unit can be reduced without increasing the bus width of a display data bus line. It is possible to do.

(2) According to the present invention, in a liquid crystal display device having a high-resolution liquid crystal display panel, a special circuit or a delay circuit is not used in the driving means, and the circuit in the driving means is changed. Is minimized, and a clock signal whose frequency is multiplied can be generated from the clock signal sent to the driving means.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a TFT type liquid crystal display module according to an embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of an example of the liquid crystal display panel shown in FIG.

FIG. 3 is a diagram showing an equivalent circuit of another example of the liquid crystal display panel shown in FIG.

FIG. 4 is a block diagram illustrating a schematic configuration of a drain driver according to the first embodiment;

5 is a diagram showing a timing chart of a display control signal from the main body computer side shown in FIG. 1 and a control signal generated by the display control device 110. FIG.

6 is a diagram showing a timing chart of the clock signals (D3, D4) shown in FIG. 5 and the clock signal (D2) shown in FIG.

FIG. 7 is a diagram illustrating an example of a circuit configuration for generating a clock signal (D3) and a clock signal (D4) in the display control device according to the first embodiment.

FIG. 8 is a diagram showing a clock signal (D2) for high-frequency display data latching from the display control device to the drain driver when the resolution of the liquid crystal display panel is large, which was examined by the present inventors before the present embodiment. FIG. 3 is a block diagram illustrating an example of a technique for transferring the data.

FIG. 9 is a diagram illustrating a clock signal (D2) for latching high-frequency display data from the display control device to the drain driver when the resolution of the liquid crystal display panel is large, which was examined by the inventor before this embodiment. FIG. 3 is a block diagram illustrating an example of a technique for transferring the data.

FIG. 10 illustrates a case where the display data is latched at the rising and falling edges of the clock signal (D2) when the resolution of the liquid crystal display panel has been studied by the present inventor before the present embodiment is large. FIG. 2 is a block diagram showing a schematic configuration of a drain driver shown in FIG.

FIG. 11 is a block diagram illustrating a schematic configuration of a drain driver according to a second embodiment.

FIG. 12 is a block diagram illustrating a schematic configuration of a drain driver according to a third embodiment;

FIG. 13 shows clock signals (D3, D3) according to the third embodiment.
FIG. 4 is a diagram showing a timing chart of 4) and a clock signal (2).

FIG. 14 is a diagram illustrating an appearance of an example of a liquid crystal monitor device according to another embodiment of the present invention.

FIG. 15 is a block diagram illustrating a schematic configuration of a liquid crystal display monitor device according to a fourth embodiment.

[Explanation of symbols]

Reference Signs List 10: liquid crystal display panel (TFT-LCD), 51: AND circuit, 52: NOR circuit, 53: OR circuit, 100: interface unit, 110: display control device, 111, 11
2: D-type flip-flop circuit, 120: power supply circuit, 1
21: positive voltage generation circuit, 122: negative voltage generation circuit, 12
3: Common electrode (counter electrode) voltage generation circuit, 124: Gate electrode voltage generation circuit, 125: Multiplexer, 13
0: drain driver, 151: logic circuit section, 152
152a, 152b, 162 ... shift register section, 15
3, 153a, 153b: pre-latch unit, 154: input latch unit, 155: liquid crystal drive voltage generation unit, 156: storage latch unit, 157: gradation voltage generation circuit, 158
... voltage bus, 159 ... delay circuit, 140 ... gate driver, 160a, 160b ... receiver, 170a, 170
b: transmitter, 180: graphic controller, 200: liquid crystal monitor device, 210: monitor cable, 220: monitor connector.

Claims (8)

[Claims] 1. A liquid crystal display panel having a plurality of pixels formed in a matrix, driving means for applying a video voltage based on display data to a plurality of pixels in a column direction, and driving the input display data to the driving means. And a display control unit for generating a control signal including at least a clock signal based on the input display control signal to be input, transmitting the control signal to the driving unit, and controlling and driving the driving unit. In the liquid crystal display device, the display control unit sends a plurality of clock signals having the same frequency and different phases to the driving unit, and the driving unit sets the plurality of clock signals having the same frequency and different phases from each other. A clock signal multiplying means for generating a multiplied clock signal whose frequency is multiplied based on the clock signal; The liquid crystal display device and storage means for storing display data sent from the display control means based on the multiplied clock signal, characterized by at least including that. 2. A pre-latch unit for storing display data sent from the display control unit in synchronization with a fall (or a rise) of a multiplied clock signal generated by the clock signal multiply unit. A shift register unit for generating a data capture signal in synchronization with the rising (or falling) of the multiplied clock signal generated by the clock signal multiplying means; and a data capture signal generated by the shift register unit. 2. The liquid crystal display device according to claim 1, further comprising at least an input latch unit that stores display data output from the pre-latch unit. 3. The display control device sends display data to the driving unit via two bus lines, and the storage unit stores a falling edge of a multiplied clock signal generated by the clock signal multiplying unit. A first pre-latch unit for storing one of the two sets of display data sent from the display control means in synchronism with the first clock signal, and a first pre-latch unit for synchronizing with the rising of the multiplied clock signal generated by the clock signal multiplying means. A second pre-latch unit for storing display data of the other of the two systems of display data transmitted from the display control means, and a first pre-latch unit for synchronizing with the rising of the multiplied clock signal generated by the clock signal multiplying means. A first shift register unit that generates a data capture signal of
A second shift register unit that generates a second data capture signal in synchronization with a fall of the multiplied clock signal generated by the clock signal multiplying unit; and a first shift register unit that is generated by the first shift register unit. Display data output from the first pre-latch section is stored by a data capture signal, and is output from the second pre-latch section by a second data capture signal generated by the second shift register section. An input latch unit for storing display data is provided at least.
2. A liquid crystal display device according to claim 1. 4. The apparatus according to claim 1, wherein the plurality of clock signals are a first clock signal and a second clock signal having a phase different from that of the first clock signal. 2. The liquid crystal display device according to claim 1. 5. The clock signal multiplying means according to claim 1, wherein:
And an AND circuit to which the clock signal and the second clock signal are input, a NOR circuit to which the first clock signal and the second clock signal are input, and the AND circuit and the NOR circuit 5. The liquid crystal display device according to claim 4, wherein the liquid crystal display device is configured by an OR circuit to be input. 6. A liquid crystal display panel having a plurality of pixels formed in a matrix, driving means for applying a video voltage based on display data to a plurality of pixels in a column direction, and driving the input display data to the driving means. And a display control unit for generating a control signal including at least a clock signal based on the input display control signal to be input, transmitting the control signal to the driving unit, and controlling and driving the driving unit. In the liquid crystal display device, the display control means includes: a first clock signal;
A second clock signal having the same frequency as that of the second clock signal and having a different phase from the first clock signal, and the second clock signal is transmitted from the display control unit in synchronization with the rising of the first clock signal. A first pre-latch unit for storing display data to be displayed, a second pre-latch unit for storing display data sent from the display control means in synchronization with a fall of the first clock signal, A first shift register unit that generates a first data capture signal in synchronization with the rising edge of the second clock signal; and a second shift register unit that generates a second data capture signal in synchronization with the falling edge of the second clock signal. 2 shift register unit and display data output from the first pre-latch unit in response to a first data capture signal generated by the first shift register unit. And an input latch unit for storing display data output from a second pre-latch unit in response to a second data capture signal generated by the second shift register unit. Liquid crystal display device. 7. A phase difference (θ) between a plurality of clock signals having the same frequency and different phases from each other is 0 <θ <π,
7. The liquid crystal display device according to claim 1, wherein π <θ <2π. 8. A liquid crystal monitor comprising the liquid crystal display device according to claim 1, wherein the display data and the input display control signal are low-amplitude and differential signals from the computer main body side. A liquid crystal monitor, which is input to the display control device.