JPH10257108A - Receiving machine - Google Patents

Abstract

(57) [Summary] A receiver for receiving a modulated wave having a digital signal as a modulation signal is adapted to be compatible with a plurality of transmission speeds, thereby improving convenience. A cutoff frequency variable low-pass filter (20) is provided at a stage subsequent to a subtraction circuit (14) constituting a detector (9), and the number of sampling signal cycles per cycle of a demodulated signal included in an output signal (S14) of the subtraction circuit (14) is counted. Thus, a cutoff frequency control circuit 21 for detecting the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 and controlling the cutoff frequency of the cutoff frequency variable low-pass filter 20 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a receiver for receiving a modulated wave using a digital signal as a modulation signal.

[0002]

2. Description of the Related Art FIG. 18 shows a conventional zero-IF receiver (receiver having no intermediate frequency amplifier circuit) for receiving a frequency shift key modulation wave (hereinafter, referred to as FSK wave) using a digital signal as a modulation signal. FIG. 3 is a circuit diagram illustrating a main part of an example.

In FIG. 18, 1 is an antenna, 2 is a high frequency amplifier circuit, 3 is a local oscillation circuit for outputting a local oscillation signal S3,
Reference numeral 4 denotes a π / 2 phase shift circuit that advances the phase of the local oscillation signal S3 output from the local oscillation circuit 3 by π / 2 [rad].

Further, reference numeral 5 denotes an output signal S of the high-frequency amplifier circuit 2.
2 is a multiplication circuit for multiplying the output signal S4 of the π / 2 phase shift circuit 4, and 6 is a multiplication circuit for multiplying the output signal S2 of the high frequency amplification circuit 2 and the local oscillation signal S3.

Reference numeral 7 denotes a low-pass filter for extracting a fundamental frequency component, that is, a frequency shift component S7, from the output signal S5 of the multiplication circuit 5, and reference numeral 8 denotes a low-pass filter for extracting a frequency shift component S8 from the output signal S6 of the multiplication circuit 6. It is.

Reference numeral 9 denotes a detector; 10, a differentiating circuit for differentiating the output signal S 7 of the low-pass filter 7;
Reference numeral 1 denotes a differentiating circuit for differentiating the output signal S8 of the low-pass filter 8.

A multiplier 12 multiplies the output signal S7 of the low-pass filter 7 by the output signal S11 of the differentiator 11, and a multiplier 13 multiplies the output signal S8 of the low-pass filter 8 by the output signal S10 of the differentiator 10. Multiplication circuit, 1
Reference numeral 4 denotes a subtraction circuit for subtracting the output signal S12 of the multiplication circuit 12 from the output signal S13 of the multiplication circuit 13.

Reference numeral 15 denotes an output signal S1 of the subtraction circuit 14.
Reference numeral 16 denotes a low-pass filter that removes unnecessary components from 4 to extract a demodulated signal S15, and 16 denotes a waveform shaping circuit that shapes the waveform of the demodulated signal S15 output from the low-pass filter 15 and outputs a demodulated signal S16.

Here, the FSK wave S1 received by the antenna 1 is represented by a · sin (w _c + w _d ) t, the output signal S2 of the high-frequency amplifier circuit 2 is represented by A · sin (w _c + w _d ) t, When the output signal S3 of the oscillation circuit 3 and B · sin w _c t, the output signal S4 of the [pi / 2 phase shift circuit 4 is to become _{B · sin (w c t +} π / 2). However, a, A, B is the amplitude, is w _c is the carrier angular frequency, w _d is the angular frequency shift.

[0010] The output signal S5 of this result, multiplication circuit 5, AB / 2 · {sin ( 2w c + w d) t + sinw d t} , and the output signal S6 of the multiplication circuit _{6, AB / 2 · {cosw d} t −cos (2w _c + w _d ) t.

The frequency component [AB / 2 · sin (2w _c + w _d ) t] of the output signal S5 of the multiplying circuit 5 is removed by the low-pass filter 7, and the output signal S7 of the low-pass filter 7 is AB / 2 · sinw. _d t.

The frequency of the output signal S6 of the multiplication circuit 6
Component [-AB / 2 · cos (2w_c+ W _d) t] is Ropa
Filter 8 removes the low-pass filter 8
Output signal S8 is AB / 2 · cosw_dt.

As a result, the output signal S10 of the differentiating circuit 10
The output signal S11 of ABw _d / 2 · cosw _d t, and the differentiating circuit 11 becomes _{-ABw d / 2 · sinw d t} .

Therefore, the output signal S1 of the multiplication circuit 12
^{2, - (AB / 2) 2} w d · sin 2 w d t and the output signal S13 of the multiplying circuit 13 becomes _{^{(AB / 2) 2 w d}} · cos 2 w d t.

[0015] Thus, also, the output signal S14 of the subtractor circuit 14, the _{^{(AB / 2) 2 w d}} .

Here, when w _d > 0, the output signal S16 of the waveform shaping circuit 16 is S16 = + (AB / 2) ² | w _d |, and when w _d <0, the waveform signal is The output signal S16 of the shaping circuit 16 is as follows: S16 = − (AB / 2) ² | w _d |

In the zero IF receiver shown in FIG. 18, the FSK wave S1 received by the antenna 1
Asin (w _c + w _d ) t is demodulated to obtain a demodulated signal S16 whose waveform is shaped.

[0018]

Here, the signal system in the current paging system is 512 bps,
The transmission speed of 1200 bps is the mainstream, but in order to increase the amount of transmission information per unit time due to the increase in the amount of transmission information today, the transmission speed was increased to 2400 bps and 36 bps.
There is a move to adopt 00 bps.

However, in the conventional zero-IF receiver shown in FIG. 18, the cut-off frequency of the low-pass filter 15 for extracting the demodulated signal S15 from the output signal S14 of the subtraction circuit 14 is fixed. Unless the receiver is changed, there is a problem that modulated signals having different transmission rates cannot be demodulated.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a receiver capable of coping with a plurality of transmission speeds and improving the convenience.

[0021]

According to a first aspect of the present invention, there is provided a receiver for removing unnecessary components from an output signal of a detector for demodulating a modulated wave having a digital signal as a modulation signal. In a receiver comprising a low-pass filter for extracting a demodulated signal, a cut-off frequency variable low-pass filter having a variable cut-off frequency is provided as a low-pass filter, and the transmission speed of the demodulated signal is detected from the output signal of the detector. And a cutoff frequency control circuit for controlling the cutoff frequency of the variable cutoff frequency low-pass filter to a frequency corresponding to the transmission speed of the demodulated signal detected from the output signal of the detector.

According to the first aspect of the present invention, as the low-pass filter for extracting the demodulated signal from the output signal of the detector, a low-pass filter with a variable cut-off frequency is provided, and the cut-off frequency of the low-pass filter with a variable cut-off frequency is detected. Since a cutoff frequency control circuit that controls the frequency corresponding to the transmission rate of the demodulated signal detected from the output signal is provided, a plurality of transmission rates can be handled.

According to a second aspect of the present invention, there is provided a receiver according to the first aspect, wherein the variable cut-off frequency low-pass filter makes the plurality of transconductor circuits equivalently appear as resistors. A transconductor combination circuit formed by combining the transconductor circuits is provided, and the cutoff frequency is controlled by controlling a value of a transconductance value control current to be passed through the plurality of transconductor circuits.

According to a third aspect of the present invention, there is provided a receiver according to the first aspect, wherein the variable cut-off frequency low-pass filter causes the plurality of transconductor circuits to appear equivalently as inductance. A transconductor combination circuit formed by combining the transconductor circuits is provided, and the cutoff frequency is controlled by controlling a value of a transconductance value control current to be passed through the plurality of transconductor circuits.

According to a fourth aspect of the present invention, there is provided a receiver according to the second or third aspect, wherein the cutoff frequency control circuit comprises a sampling signal generating circuit for generating a sampling signal, and a detector. Transmission rate detection for detecting the transmission rate of the demodulated signal output from the detector by counting the number of cycles of the sampling signal per cycle of the preamble signal included in the demodulated signal output from the detector and outputting a transmission rate detection signal And a transconductor combination circuit control circuit that controls the transconductor combination circuit so that a transconductance value control current having a value corresponding to the transmission rate indicated by the transmission rate detection signal flows through the transconductor combination circuit. It is.

In a fifth aspect of the present invention, the receiver according to the fifth aspect is the first, second, third or fourth aspect.
A high-frequency amplifier circuit for amplifying a frequency shift keying wave that uses a digital signal as a modulation signal, as a circuit preceding the detector,
A phase shift circuit that shifts the phase of a local oscillation signal having the same frequency as the carrier frequency of the frequency shift keying wave by π / 2 [rad], and a first signal that multiplies an output signal of the high frequency amplifier circuit and an output signal of the phase shift circuit. A multiplying circuit, a second multiplying circuit for multiplying the output signal of the high-frequency amplifier circuit and the local oscillation signal, a first low-pass filter for extracting a frequency shift component from the output signal of the first multiplying circuit, A second low-pass filter for extracting a frequency shift component from the output signal of the multiplication circuit, wherein the detector includes a first differentiation circuit for differentiating the output signal of the first multiplication circuit, and an output signal of the second multiplication circuit. Second to differentiate
, A third multiplication circuit for multiplying the output signal of the first low-pass filter and the output signal of the second differentiation circuit, the output signal of the second low-pass filter and the output signal of the first differentiation circuit , And a subtraction circuit for subtracting the output signal of the third multiplication circuit from the output signal of the fourth multiplication circuit.

According to a sixth aspect of the present invention, there is provided a receiver according to the first, second, third or fourth aspect.
A high-frequency amplifier circuit for amplifying a frequency shift keying wave that uses a digital signal as a modulation signal, as a circuit preceding the detector,
A phase shift circuit that shifts the phase of the output signal of the high-frequency amplifier circuit by π / 2 [rad]; and a multiplication unit that multiplies the output signal of the phase shift circuit by a local oscillation signal having the same frequency as the carrier frequency of the frequency shift keying wave A first multiplication circuit, a second multiplication circuit for multiplying the output signal of the high-frequency amplification circuit and the local oscillation signal, a first low-pass filter for extracting a frequency shift component from the output signal of the first multiplication circuit, A second low-pass filter for extracting a frequency shift component from an output signal of the second multiplication circuit, wherein the detector includes a first differentiation circuit for differentiating the output signal of the first multiplication circuit, and a second multiplication circuit. A second differentiating circuit for differentiating the output signal, a third multiplying circuit for multiplying the output signal of the first low-pass filter and the output signal of the second differentiating circuit, an output signal of the second low-pass filter, Output signal of differentiation circuit of 1 A fourth multiplying circuit for multiplying a, is that the output signal of the fourth multiplying circuit is constituted by a subtraction circuit for subtracting an output signal of the third multiplication circuit.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
An embodiment of the present invention will be described with an example in which the present invention is applied to a zero-IF receiver for receiving an FSK wave. In FIGS. 1 and 13, portions corresponding to those in FIG. 18 are denoted by the same reference numerals, and redundant description will be omitted.

1 to 12 FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention. The first embodiment of the present invention employs a conventional zero-power amplifier shown in FIG. I
Instead of the low-pass filter 15 having a fixed cut-off frequency provided in the F receiver, a cut-off frequency variable low-pass filter 20 for varying the cut-off frequency is provided, and the cut-off frequency variable low-pass filter 20 is provided.
Is provided with a cutoff frequency control circuit 21 for controlling the cutoff frequency, and the other components are configured similarly to the conventional zero IF receiver shown in FIG.

FIG. 2 is a circuit diagram showing the configuration of the cut-off frequency variable low-pass filter 20. In FIG. 2, reference numeral 23 denotes a transconductor circuit which is a voltage-controlled current source whose output current is controlled in proportion to the input voltage. The combined transconductor combination circuit, 24 is a capacitor.

FIG. 3 is a circuit diagram showing a configuration of the transconductor combination circuit 23. In FIG.
Is a transconductor circuit.

[0032] FIG. 4 is a diagram for explaining the function of the transconductor circuit, the input voltage v _in the transconductor circuit 27, and the output current is i _0, the transconductor G transconductor circuit 27, G = Δi ₀ / Δv _in next, transresistance R transconductor circuit 27 becomes _{R = 1 / G = Δv in} / Δi 0.

FIG. 5 is a circuit diagram showing a configuration example of the transconductor circuit 25 shown in FIG. 3. In FIG. 5, reference numeral 29 denotes a VCC power supply line for supplying a power supply voltage VCC, reference numerals 30 and 31 denote PNP transistors forming a load, VA is the bias voltage, 32
35 to 35 are NPN transistors for performing a voltage / current conversion operation, and 36 is a variable current source which is a supply source of transconductance value control currents ix1 and ix2 for controlling the transconductance value to be passed to the transconductor circuit 25.

In the first embodiment of the present invention,
The transconductor circuit 26 shown in FIG. 3 is configured similarly to the transconductor circuit 25 by sharing the variable current source 36 with the transconductor circuit 25.

It should be noted that pMOS transistors can be used instead of the PNP transistors 30 and 31, and nMOS transistors can be used instead of the NPN transistors 32-35.

FIG. 6 is a circuit diagram showing the configuration of the variable current source 36. In FIG. 6, reference numeral 39 denotes a constant voltage V1 of 1.0 [V].
, A constant voltage source 40, a comparator 41, 42
Is nM whose gate voltage is controlled by the comparator 40
The OS transistors 43 and 44 are resistors.

Here, the nMOS transistor 41 and the resistor 43 constitute a current source for supplying a current i1 to a current path through which the transconductance value control current ix1 is to flow, and the nMOS transistor 42 and the resistor 44 constitute the current source. And a current source for supplying a current i1 to a current path through which the transconductance value control current ix1 is to flow.

Reference numeral 45 denotes a constant voltage V2 of 1.1.
Constant voltage source for outputting [V];
Reference numerals 7 and 48 denote nMOS transistors whose gate voltages are controlled by the comparator 46, and reference numerals 49 and 50 denote resistors.

Here, the nMOS transistor 47 and the resistor 49 constitute a current source for supplying a current i2 to a current path through which the transconductance value control current ix1 flows, and the nMOS transistor 48 and the resistor 50 constitute the current source. And a current source for supplying a current i2 to a current path through which the transconductance value control current ix2 is to flow.

Reference numeral 51 denotes a constant voltage V3 of 1.2.
A constant voltage source for outputting [V], 52 is a comparator, 5
Reference numerals 3 and 54 denote nMOS transistors whose gate voltages are controlled by the comparator 52, and 55 and 56 denote resistors.

Here, the nMOS transistor 53 and the resistor 55 constitute a current source for supplying a current i3 to a current path through which the transconductance value control current ix1 should flow, and the nMOS transistor 54 and the resistor 56 constitute the current source. And a current source for supplying a current i3 to a current path through which the transconductance value control current ix2 flows.

The nMOS transistors 41, 42,
Instead of 47, 48, 53 and 54, NPN transistors can be used.

V59 is a transconductance value control current control voltage supplied from a D / A converter (described later) constituting the cutoff frequency control circuit 21. The transconductance value control current control voltage V59
1.05 [V], 1.15 [V], 1.25
[V] is selectively supplied.

When 1.05 [V] is supplied as the transconductance value control current control voltage V59, the output of the comparator 40 = H level, the output of the comparator 46 = L level, and the output of the comparator 52 = L level.

As a result, the nMOS transistor 41 = O
N, nMOS transistor 42 = ON, nMOS transistor 47 = OFF, nMOS transistor 48 = O
N, the nMOS transistor 53 = OFF and the nMOS transistor 54 = OFF, and the transconductance value control currents ix1 and ix2 flowing through the transconductor combination circuit 23 become i1.

When 1.15 [V] is supplied as the transconductance value control current control voltage V59, the output of the comparator 40 = H level, the output of the comparator 46 = H level, and the output of the comparator 52 =
It becomes L level.

As a result, the nMOS transistor 41 = O
N, nMOS transistor 42 = ON, nMOS transistor 47 = ON, nMOS transistor 48 = ON,
The nMOS transistor 53 = OFF and the nMOS transistor 54 = OFF, and the transconductance value control current ix flowing to the transconductor combination circuit 23
1, ix2 is i1 + i2.

When 1.25 [V] is supplied as the transconductance value control current control voltage V59, the output of the comparator 40 = H level, the output of the comparator 46 = H level, and the output of the comparator 52 =
It becomes H level.

As a result, the nMOS transistor 41 = O
N, nMOS transistor 42 = ON, nMOS transistor 47 = ON, nMOS transistor 48 = ON,
The nMOS transistor 53 = ON, the nMOS transistor 54 = ON, and the transconductor combination circuit 2
3, the transconductance value control current ix1,
ix2 is i1 + i2 + i3.

Here, in FIG. 3, the input voltage of the transconductor combination circuit 23 is V1, the input current is I1,
Assuming that the output voltage is V2 and the output current is I2, the transconductance G of the transconductor combination circuit 23
Is G = V ₁ −V ₂ / I ₁ −I ₂ , and the transresistance R of the transconductor combination circuit 23 is R = I ₁ −I ₂ / V ₁ −V ₂ .

Therefore, the equivalent circuit of the transconductor combination circuit 23 is as shown in FIG. 7 and the equivalent circuit of the cut-off frequency variable low-pass filter 20 is as shown in FIG. The circuit constants are set so as to function as follows.

That is, when the transconductance value control currents ix1 and ix2 are i1, as shown in FIG. 9, the transconductor combination circuit 23 can be equivalently regarded as a resistor R1, and as a result, the cutoff frequency fc is fc
1 = １ ／ π × R1 × C, and an unnecessary component is removed from the output signal S14 of the subtraction circuit 14 to reduce the transmission speed to 512 bp.
It functions as a low-pass filter that extracts the demodulated signal s. Here, C is the capacitance value of the capacitor 24, and the same applies hereinafter.

When the transconductance value control currents ix1 and ix2 are i1 + i2, as shown in FIG. 10, the transconductor combination circuit 23 can be equivalently regarded as a resistor R2 (<R1), and the cutoff The frequency fc becomes fc2 = 1 / 2π × R2 × C, and the subtraction circuit 14
Function as a low-pass filter for removing a demodulated signal having a transmission rate of 1200 bps by removing unnecessary components from the output signal S14.

When the transconductance value control currents ix1 and ix2 are i1 + i2 + i3, as shown in FIG. 11, the transconductor combination circuit 23 can be equivalently regarded as a resistor R3 (<R2), and the cutoff is achieved. The frequency fc becomes fc3 = 1 / 2π × R3 × C, and functions as a low-pass filter for extracting a demodulated signal having a transmission speed of 2400 bps by removing unnecessary components from the output signal S14 of the subtraction circuit 14.

FIG. 12 is a circuit diagram showing the configuration of the cutoff frequency control circuit 21. In FIG. 12, 57 is a subtraction circuit 1
4 is a sampling signal generation circuit that outputs a sampling signal S57 used for detecting the transmission speed of the demodulated signal from the output signal S14 of the sampling signal S57.
Frequency is 512 bps, 1200 bps, 24
19200 Hz, which is the least common multiple of 00 bps.

Reference numeral 58 denotes an output signal S1 of the subtraction circuit 14.
4 is a counter forming a transmission rate detection circuit that counts the number of cycles of the sampling signal S57 per cycle of the demodulated signal included in 4 and detects the transmission rate of the demodulated signal included in the output signal S14 of the subtraction circuit 14.

Here, when the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 is 512 bps,
1 of the demodulated signal included in the output signal S14 of the subtraction circuit 14
The number of cycles of the sampling signal S57 existing in the cycle is 19200 × (1/512) × 2 = 75 (pieces).

On the other hand, the output signal S of the subtraction circuit 14
In the case where the transmission speed of the demodulated signal included in 14 is 1200 bps, the number of cycles of the sampling signal S57 existing in one cycle of the demodulated signal included in the output signal S14 of the subtraction circuit 14 is 19200 × (1/1200). × 2 = 32 (pieces).

When the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 is 2400 bps,
1 of the demodulated signal included in the output signal S14 of the subtraction circuit 14
The number of cycles of the sampling signal S57 existing in the cycle is 19200 × (１／400) × 2 = 16 (pieces).

Here, when the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 is 512 bps, one cycle is 3.91 msec.
When the operation is performed for 00 msec, the output signal S14 of the subtraction circuit 14 is output.
The subtraction circuit 1 that can sample the sampling signal S57 when the transmission speed of the demodulated signal included in the signal is 512 bps
The number of cycles of the output signal S14 of 4 is 100 × (1 / 3.91) × 2 = 51.2 (pieces).

On the other hand, the output signal S of the subtraction circuit 14
When the transmission speed of the demodulated signal included in the signal 14 is 1200 bps, one cycle is 1.67 msec. Therefore, if the sampling operation is performed for 100 msec, the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 becomes 1200 bps.
In this case, the number of cycles of the output signal S14 of the subtraction circuit 14 that can sample the sampling signal S57 is 100 × (1 / 1.67) × 2 = 120 (pieces).

When the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 is 2400 bps, one cycle is 0.83 msec.
When the operation is performed for 00 msec, the output signal S14 of the subtraction circuit 14 is output.
The number of cycles of the output signal S14 of the subtraction circuit 14 that can sample the sampling signal S57 when the transmission speed of the demodulated signal included in the above is 2400 bps is 100 × (1 / 0.83) × 2 = 240 (pieces).

Then, the counter 58 uses the preamble signal in the demodulated signal included in the output signal S14 of the subtraction circuit 14 for 100 msec to generate the sampling signal S5.
7 is counted, and the output signal S of the subtraction circuit 14 is counted.
14, the average value of the number of cycles of the sampling signal S57 per one cycle of the demodulated signal is calculated, and the transmission speed is set to 51
When the transmission speed is 2 bps, the transmission speed detection signal S58-512 is output. When the transmission speed is 1200 bps, the transmission speed detection signal S58-1200 is output.
In the case of s, the transmission rate detection signal S58-2400 is output.

Reference numeral 59 denotes a transmission speed detection signal S58-512, S58-1200,
This is a D / A converter that constitutes a transconductor combination circuit control circuit that converts S58-2400 from digital to analog and outputs a transconductance value control current control voltage V59.

The D / A converter 59 includes a counter 5
8, when the transmission speed detection signal S58-512 is output, the transconductance value control current control voltage V
When the transmission speed detection signal S58-1200 is output from the counter 58, 1.15 [V] is output as the transconductance value control voltage V59, and the counter 58 outputs When the transmission speed detection signal S58-2400 is output, the transconductance value control current control voltage V59 is set to 1.
It is configured to output 25 [V].

In the first embodiment of the present invention configured as described above, each circuit from the antenna 1 to the subtraction circuit 14 operates in the same manner as in the case of the conventional zero IF receiver shown in FIG.

Here, when the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 is 512 bps,
The counter 58 outputs the transmission rate detection signal S58-512, and the D / A converter 59 correspondingly outputs 1.05 [V] as the transconductance value control current control voltage V59. The variable cut-off frequency low-pass filter 20 removes unnecessary components from the output signal S14 of the subtraction circuit 14 to reduce the transmission speed by 51%.
A demodulated signal S20 of 2 bps is extracted.

On the other hand, the output signal S of the subtraction circuit 14
When the transmission speed of the demodulated signal included in the signal No. 14 is 1200 bps, the counter 58 outputs the transmission speed detection signal S58-1.
200, and the D / A converter 5
9 is a transconductance value control current control voltage V5
Therefore, the cutoff frequency variable low-pass filter 20 removes unnecessary components from the output signal S14 of the subtraction circuit 14 to extract the demodulated signal S20 having a transmission speed of 1200 bps. become.

When the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 is 2400 bps,
The counter 58 outputs the transmission speed detection signal S58-2400, and in response to this, the D / A converter 59 outputs 1.25 [V] as the transconductance value control current control voltage V59. Therefore, the cut-off frequency variable low-pass filter 20
Thus, a demodulated signal S20 having a transmission speed of 2400 bps is extracted by removing unnecessary components from the output signal S14 of FIG.

As described above, according to the first embodiment of the present invention, since the cutoff frequency variable low-pass filter 20 and the cutoff frequency control circuit 21 are provided, the transmission speed is set to 512 bps, 1200 bps, and 2400 bps. An FSK wave having a digital signal as a modulation signal can be demodulated, and convenience can be improved.

FIG. 13 is a circuit diagram showing a main part of a second embodiment of the present invention. FIG. 13 is a circuit diagram showing a second embodiment of the present invention. First
A cut-off frequency variable low-pass filter 61 having a circuit configuration different from that of the cut-off frequency variable low-pass filter 20 provided in the embodiment is provided, and the other configuration is the same as that of the first embodiment of the present invention shown in FIG.

FIG. 14 is a circuit diagram showing the configuration of the cut-off frequency variable low-pass filter 61. In FIG.
Is a transconductor combination circuit formed by combining transconductor circuits, and 65 is a capacitor.

FIG. 15 shows a transconductor combination circuit 6
4 is a circuit showing the configuration of FIG. 4. In FIG. 15, 67 and 68 are transconductor circuits.

FIG. 16 is a circuit diagram showing the structure of the transconductor circuit 67.
7, a variable current source 77 having a circuit configuration different from that of the variable current source 36 included in the transconductor circuit 25 shown in FIG. 5 is provided, and the other configuration is the same as that of the transconductor circuit 25 shown in FIG.

In the variable current source 77, 78, 7
Reference numeral 9 denotes an NPN transistor to which a transconductance value current control voltage V59 output from the D / A converter 59 is applied to the gate, and reference numerals 80 and 81 denote resistors.

Here, the NPN transistor 78 and the resistor 8
0 constitutes a current source for flowing the transconductance value control current ix1, and the nMOS transistor 79
And the resistor 81, the transconductance value control current i
A current source for flowing x2 is configured.

Note that in the second embodiment of the present invention,
The transconductor circuit 68 shown in FIG. 15 is also configured similarly to the transconductor circuit 67 by sharing the variable current source 77 with the transconductor circuit 67.

Here, the variable current source 77 supplies the transconductor value control current control voltage V
When 1.05 [V] is supplied as 59, i1 is output as the transconductor value control currents ix1 and ix2, and 1.15 [V] as the transconductor value control current control voltage V59 from the D / A converter 59. Is supplied, the transconductor value control current ix1,
i1 + i2 is output as ix2, and the D / A converter 5
9, when 1.25 [V] is supplied as the transconductor value control current control voltage V59, the transconductor value control currents ix1 and ix2 are i1 + i2 +
The circuit constant is set so as to output i3.

Therefore, the transconductor combination circuit 64 has the transconductor value control current control voltage V59 supplied from the D / A converter 59 in the first embodiment of the present invention except for the variable current source. The operation is the same as that of the transconductor combination circuit 23.

In the second embodiment of the present invention thus configured, each circuit from the antenna 1 to the subtraction circuit 14 operates in the same manner as in the case of the conventional zero IF receiver shown in FIG.

Here, when the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 is 512 bps,
The counter 58 outputs the transmission rate detection signal S58-512, and the D / A converter 59 correspondingly outputs 1.05 [V] as the transconductance value control current control voltage V59. The variable cut-off frequency low-pass filter 61 removes unnecessary components from the output signal S14 of the subtraction circuit 14 to reduce the transmission speed by 51%.
A 2 bps demodulated signal S61 is extracted.

On the other hand, the output signal S of the subtraction circuit 14
When the transmission speed of the demodulated signal included in the signal No. 14 is 1200 bps, the counter 58 outputs the transmission speed detection signal S58-1.
200, and the D / A converter 5
9 is a transconductance value control current control voltage V5
Therefore, the cut-off frequency variable low-pass filter 61 removes unnecessary components from the output signal S14 of the subtraction circuit 14 to extract the demodulated signal S61 having a transmission speed of 1200 bps. become.

When the transmission speed of the demodulated signal included in the output signal S14 of the subtraction circuit 14 is 2400 bps,
The counter 58 outputs the transmission speed detection signal S58-2400, and the D / A converter 59 correspondingly outputs 1.25 [V] as the transconductance value control current control voltage V59. The variable cut-off frequency low-pass filter 61 removes unnecessary components from the output signal S14 of the subtraction circuit 14 to reduce the transmission speed to 24.
A demodulated signal S61 of 00 bps is extracted.

As described above, according to the second embodiment of the present invention, since the cutoff frequency variable low-pass filter 61 and the cutoff frequency control circuit 21 are provided, the transmission speed is set to 512 bps, 1200 bps, and 2400 bps. An FSK wave having a digital signal as a modulation signal can be demodulated, and convenience can be improved.

In the first and second embodiments of the present invention, as the transconductor combination circuit constituting the cut-off frequency variable low-pass filter, the transconductor circuit is equivalently combined so as to look like a resistor. Has been described, but instead, as shown in FIG. 17, a transconductor combination circuit formed by combining transconductor circuits 84 and 85 so as to look equivalent to an inductance may be used. .

In the first and second embodiments of the present invention, the π / 2 phase shift circuit 4 for advancing the phase of the local oscillation signal S3 output from the local oscillation circuit 3 by π / 2 [rad]. Has been described, but instead of this, a π / 2 phase shift circuit for advancing the phase of the output signal S2 of the high frequency amplifier circuit 2 by π / 2 [rad] is provided. The output signal of the π / 2 phase shift circuit that advances the phase of the output signal S2 of the amplifier circuit 2 by π / 2 [rad] may be multiplied by the local oscillation signal S3.

In the first and second embodiments of the present invention, a case has been described where the present invention is applied to a receiver for receiving a frequency-shifted modulated wave using a digital signal as a modulation signal. INDUSTRIAL APPLICABILITY The present invention can be generally applied to a receiver that receives a modulated wave having a digital signal as a modulation signal.

[0088]

According to the first, second, third or fourth aspect of the present invention (receiver according to the first, second, third or fourth aspect), a modulated signal having a digital signal as a modulation signal is provided. Since the receiver for receiving waves can support a plurality of transmission speeds, the convenience can be improved.

Further, according to the fifth or sixth aspect of the present invention (receiver according to claim 5 or 6), a receiver for receiving a frequency-shifted modulated wave having a digital signal as a modulation signal. With respect to the above, since it is possible to cope with a plurality of transmission speeds, it is possible to improve convenience.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a variable cutoff frequency low-pass filter included in the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a transconductor combination circuit constituting a cutoff frequency variable low-pass filter provided in the first embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining functions of a transconductor circuit included in a transconductor combination circuit provided in the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a transconductor circuit included in a transconductor combination circuit provided in the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a variable current source included in a transconductor combination circuit provided in the first embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of a transconductor combination circuit included in the first embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a cutoff frequency variable low-pass filter included in the first embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of a cutoff frequency variable low-pass filter included in the first embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram of a cutoff frequency variable low-pass filter included in the first embodiment of the present invention.

FIG. 11 is an equivalent circuit diagram of a cutoff frequency variable low-pass filter included in the first embodiment of the present invention.

FIG. 12 is a circuit diagram illustrating a configuration of a cutoff frequency control circuit included in the first embodiment of the present invention.

FIG. 13 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 14 is a circuit diagram illustrating a configuration of a cutoff frequency variable low-pass filter included in a second embodiment of the present invention.

FIG. 15 is a circuit diagram showing a configuration of a transconductor combination circuit constituting a variable cutoff frequency low-pass filter provided in a second embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of a transconductor circuit included in a transconductor combination circuit provided in a second embodiment of the present invention.

FIG. 17 is a circuit diagram showing another configuration example of a transconductor combination circuit that can configure a cutoff frequency variable low-pass filter included in the present invention.

FIG. 18 is a circuit diagram showing a main part of an example of a conventional zero-IF receiver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Antenna 2 High frequency amplification circuit 3 Local oscillation circuit 4 π / 2 phase shift circuit 5, 6, 12, 13 Multiplication circuit 7, 8, 15 Low pass filter 10, 11 Differentiation circuit 14 Subtraction circuit 16 Waveform shaping circuit

Claims (6)

[Claims] 1. A receiver comprising a low-pass filter for removing an unnecessary component from an output signal of a detector for demodulating a modulated wave having a digital signal as a modulation signal and extracting a demodulated signal, wherein a cut-off frequency is used as the low-pass filter. With a variable cut-off frequency variable low-pass filter, the transmission speed of the demodulated signal was detected from the output signal of the detector, and the cut-off frequency of the cut-off frequency variable low-pass filter was detected from the output signal of the detector. A receiver comprising a cutoff frequency control circuit for controlling a frequency corresponding to a transmission speed of a demodulated signal. 2. A low-pass filter having a variable cutoff frequency, comprising: a transconductor combination circuit formed by combining a plurality of transconductor circuits so as to appear equivalently as resistors; 2. The receiver according to claim 1, wherein the cutoff frequency is controlled by controlling the value of the control current. 3. The low-pass filter having a variable cutoff frequency includes a transconductor combination circuit formed by combining a plurality of transconductor circuits so as to look equivalently as inductance, and a transconductance value to be passed through the plurality of transconductor circuits. 2. The receiver according to claim 1, wherein the cutoff frequency is controlled by controlling the value of the control current. 4. A cut-off frequency control circuit, comprising: a sampling signal generating circuit for generating a sampling signal; and counting a number of periods of the sampling signal per one period of a preamble signal included in a demodulated signal output from the detector. A transmission rate detection circuit that detects the transmission rate of the demodulated signal output from the detector and outputs a transmission rate detection signal; and a transconductance value control current having a value corresponding to the transmission rate indicated by the transmission rate detection signal. 4. A receiver according to claim 2, further comprising: a transconductor combination circuit control circuit for controlling the transconductor combination circuit so that the transconductor combination circuit flows through the transconductor combination circuit. 5. A high frequency amplifying circuit for amplifying a frequency shift keying wave having a digital signal as a modulating signal, and a local oscillation signal having the same frequency as a carrier frequency of the frequency shift keying wave as π as a preceding circuit of the detector. / 2 [rad] phase shift circuit, a first multiplying circuit for multiplying the output signal of the high frequency amplifier circuit and the output signal of the phase shift circuit, the output signal of the high frequency amplifier circuit and the local oscillation A second multiplication circuit for multiplying the output signal of the first multiplication circuit, a first low-pass filter for extracting a frequency shift component from the output signal of the first multiplication circuit, and a frequency shift component from the output signal of the second multiplication circuit. A second low-pass filter for extracting the output signal of the first multiplication circuit; and a second differentiation circuit for differentiating the output signal of the second multiplication circuit. When A third multiplication circuit for multiplying the output signal of the first low-pass filter and the output signal of the second differentiation circuit; And a subtraction circuit for subtracting an output signal of the third multiplication circuit from an output signal of the fourth multiplication circuit. ,
The receiver according to 2, 3, or 4. 6. A high frequency amplifying circuit for amplifying a frequency shift keying wave using a digital signal as a modulating signal, and an output signal of the high frequency amplifying circuit as π /
A phase shift circuit that shifts the phase by 2 [rad]; a first multiplier circuit that multiplies an output signal of the phase shift circuit by a local oscillation signal having the same frequency as a carrier frequency of the frequency shift keying wave; A second multiplication circuit for multiplying the output signal of the circuit and the local oscillation signal, a first low-pass filter for extracting a frequency shift component from an output signal of the first multiplication circuit, and a second multiplication circuit. A second low-pass filter that extracts a frequency shift component from an output signal, wherein the detector is configured to differentiate an output signal of the first multiplication circuit, and an output signal of the second multiplication circuit. A second differentiating circuit, a third multiplying circuit for multiplying the output signal of the first low-pass filter and the output signal of the second differentiating circuit, and an output signal of the second low-pass filter. The first derivative A fourth multiplying circuit for multiplying the output signal of the circuit by a circuit, and a subtraction circuit for subtracting the output signal of the third multiplying circuit from the output signal of the fourth multiplying circuit. Claim 1,
The receiver according to 2, 3, or 4.