JPH10256342A - Transfer control method - Google Patents

Abstract

(57) [Summary] When transferring a plurality of substrates to a plurality of destinations in parallel according to a transfer processing schedule without simultaneously transferring a plurality of substrates to a substrate transfer apparatus, the schedule is deviated from an actual transfer processing step. Ensuring product quality even when time occurs. First, a process by the apparatus is monitored to detect a time lag between the schedule and an actual process (step S4). If the time lag is detected, a transport process is started at the present time. And a substrate for which the transfer process has not yet started. Next, the schedule of the substrate whose processing has been started is corrected based on the time lag except for the portion related to the substrate whose processing has not yet started from the schedule (step S5), and then the processing starts in the corrected schedule. The schedule relating to the unprocessed substrates is added to avoid the simultaneous transport to create a new transport processing schedule (step S6).
To S11), thereby executing the subsequent transport process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of transferring a plurality of substrates to a plurality of destinations in parallel without sequentially transferring the plurality of substrates to a plurality of destinations in accordance with a transfer processing schedule. Regarding the transfer control method for executing the transfer process, in particular, even if a shift time occurs between the transfer process schedule and the actual transfer process, avoid simultaneous transfer and create a new transfer process schedule. The present invention relates to a transport control method for ensuring the quality of a manufactured semiconductor product by creating and executing a subsequent transport process according to the new transport process schedule.

[0002]

2. Description of the Related Art As a semiconductor manufacturing apparatus for sequentially processing a plurality of semiconductor wafers in parallel, for example, a cluster type single wafer semiconductor manufacturing apparatus is known. FIG. 7 shows a configuration example of the cluster-type single-wafer semiconductor manufacturing apparatus 1. The apparatus 1 includes, for example, a process module (PM) that performs a wafer process such as forming a thin film on a wafer, a transport module (TM) that is a substrate transfer device that performs a wafer transfer process, and a plurality of wafers. There are provided a cassette module (CM) for storing, and a docking module (DM) for connecting between the transport module and the transport module and exchanging wafers between these modules.

[0003] The above-mentioned cassette module includes:
A door separating the inside and the outside of the device 1 is provided;
Through this door, wafer exchange processing inside and outside the apparatus 1 is performed. In addition, a gate valve (GV) composed of, for example, an interface flange, which is a boundary surface for separating the atmosphere between the two modules, is provided between the transport module and the other modules.
The modules having the various functions described above can be used in any combination, and as shown in FIG.
By integrating necessary modules into a semiconductor manufacturing apparatus, a production system that is environmentally isolated from the outside of the apparatus can be established.

In the semiconductor manufacturing apparatus 1 having the configuration shown in FIG. 7, generally, a plurality of wafers are processed in time parallel by a plurality of process modules provided in the apparatus 1. . That is, in the transport module, for example, one wafer is transported to a certain destination, and while another wafer is being processed at this destination, another wafer is transported to another destination. In this manner, a plurality of wafers are processed in parallel. In general, processing in each module is performed under the control of a control device such as a computer. For example, in the semiconductor manufacturing apparatus 1 shown in FIG. 7, as shown in FIG. 7, a process module controller (PMC) for controlling each process module
Are connected, and a transport / cassette module controller (TM / CMC) for controlling each transport module and cassette module is connected.

Each of the above-mentioned module controllers is connected to a cluster controller (CC) 2 which controls these controllers via a line such as an Ethernet LAN 3.
Are all performed by this cluster controller 2.
Is controlled by For this reason, the cluster controller 2 stores a processing schedule such as what processing is performed for each wafer, and the cluster controller 2 sequentially processes a plurality of wafers according to the stored schedule. To go.

A so-called automatic operation is one in which a schedule is set for each wafer by using such a scheduling function so that a plurality of wafers are processed smoothly. Further, when the schedule in the automatic operation is created so as to minimize the waiting time of the processing in each module described above, the throughput of the semiconductor manufacturing apparatus (the number of wafers processed per unit time)
Can be improved. That is, in general, a semiconductor manufacturing apparatus is constantly operated for 24 hours, and a product is efficiently manufactured using the above-described automatic operation function. In order for the semiconductor manufacturing apparatus to correctly execute the automatic operation as described above, it is necessary to create a schedule so that the processing of each wafer at the same time does not overlap. When it is necessary to carry out a certain wafer transfer process at the time of completion or the like, at this time, the transport module (robot)
Is a necessary condition that is not operating.

Further, for example, when a wafer is subjected to a high-temperature process in a process module, if the wafer is left in the process module after the process is completed, the film on the wafer is adversely affected. Must immediately take out the wafer from the process module and perform the subsequent processing. A schedule of the wafer processing is created so as to satisfy such conditions and the above-described conditions in the transfer processing, and the schedule is preset in the apparatus by a user or the like. Here, FIG. 9 shows an example of a schedule for causing the cluster-type single-wafer semiconductor manufacturing apparatus 4 shown in FIG. 8 to execute automatic operation. The semiconductor manufacturing apparatus 4 shown in FIG. 8 includes two cassette modules CM1 and CM2, six process modules PM1 to PM6, and one transport module T
M, and a module controller similar to that shown in FIG. 7 and a cluster controller 2 for controlling these modules are connected to the respective modules via a LAN 3 (not shown). ).

FIG. 8 shows a processing procedure (processing route) input by the user for each wafer to be processed. For example, first, for the first wafer (wafer 1), Then, the wafer 1 is taken out from the slot 1 (wafer position) of the cassette module CM1, the processing is performed in the process module PM1, the processing is performed in the process module PM2, and finally, the processing is performed in the slot 1 of the cassette module CM2. A processing route is set so as to store the processed wafer 1. Also, the processing routes for the second and third wafers (wafer 2 and wafer 3) are defined as shown, and the fourth and subsequent wafers (wafer 4, wafer 5,
For the wafers 6...), The same route as the processing route for the wafers 1 to 3 is repeatedly used for the process.

In the processing route described above, information indicating which wafer is to be taken out from which slot (wafer position) of which cassette module and information indicating which wafer is to be stored in which slot of which cassette module (load / load).
(Unload cassette module name and slot number)
And information on which process module processes the wafer (name of the process module). Although not shown in FIG. 8, the cluster controller 2 stores, for the wafer processing in the process module, control parameters such as a process time expected to be required for the process and a temperature and a pressure at the time of performing the process. The determined process recipe is stored in correspondence with the number of processes performed in the apparatus 4, and for each process module of each wafer described above, which of the stored process recipes is used to perform the process. (Process recipe name) is defined.

FIG. 9 shows an example of a semiconductor manufacturing schedule created according to the processing route for each wafer shown in FIG. In the schedule shown in the drawing, the processing flow of when processing such as transfer processing is performed on each wafer is summarized for all the wafers in order of time. In the schedule shown in the figure, the time required for each process is
The transfer process is expected to take 30 seconds regardless of the type of the transfer source module and the transfer destination module, and the process modules PM1, PM2, PM
4. It is assumed that one minute is required for wafer processing in PM5, one minute and 30 seconds is required for wafer processing in process module PM3, and two minutes is required for wafer processing in process module PM6. Scheduled and scheduled have been created. Further, as described above, the schedules are set so that the times at which the same processing is performed on two or more wafers do not overlap in the processing such as the transfer processing.

[0011]

However, when a process such as a transfer process is performed on a wafer according to the above-described schedule, the actual transfer process may be performed due to, for example, a temporary failure occurring in each of the above-described modules. In some cases, the process deviates in time from the originally planned process. Here, FIG. 10 shows an example in which a delay time of 30 seconds occurs in the processing of the wafer 1 in the process module PM1 in the schedule of the transfer processing shown in FIG. As a method of coping with such a processing delay, for example, as shown in the figure, the start time of the third or later wafer processing that has not been started yet when the delay has occurred for the wafer 1 is simply set. In order to extend the wafer input waiting time by delaying the wafer by the delay time, that is, 30 seconds, such a simple change of the schedule requires the removal of the wafer after the completion of the processing in the process module. (The wafer transfer processing time) may overlap between two or more wafers.

[0012] For example, in the case shown in FIG.
Since the transfer processing times (2 minutes 30 seconds to 3 minutes) overlap with each other, 30 seconds are further provided as a waiting time so that the wafer 3
Is started from time 3 minutes. In this case, the processing start time of the wafer 4 is changed to the original scheduled time (5
Assuming that the time is 5 minutes and 30 seconds delayed from the minutes by 30 seconds, the transfer processing time of the wafer 3 and the wafer 4 (7 minutes to 7 minutes and 30 seconds)
Are duplicated, and it becomes impossible to perform any of the processing of these wafers in a normal procedure. For this reason, for example, as shown in FIG. 10, when the transfer processing time of the wafer 4 is further delayed and started at 7 minutes 30 seconds, the film quality of the wafer 4 which cannot be processed normally is determined. There was a problem that the quality deteriorated.

In the above description, a case has been described in which a temporary time lag occurs that does not affect the subsequent processing between the scheduled wafer processing time and the actual processing step. Then, since the scheduled time is actually different from the set time, a similar time lag may occur for the same subsequent processing. Even in such a case, as in the above case, for example, simply changing the processing start time of the subsequent wafer by the shifted time may cause duplication of the transfer processing for the subsequent wafer. There was a problem that the products could be made to produce poor quality products.

As described above, in a semiconductor manufacturing apparatus that executes processing according to a schedule created in advance, if the actual wafer processing step deviates from the planned schedule, the transfer processing is performed for the subsequent wafer. There is a problem that the semiconductor device may be duplicated, so that even if the subsequent semiconductor manufacturing process is continued, a product of poor quality is manufactured. In addition, when the time lag as described above occurs, the manufacturing process can be stopped and the user can be called. In this case, the user can use the apparatus every time the time lag occurs. It is necessary to perform a recovery operation or the like, and there is a problem that such an operation is very troublesome for the user.

The present invention has been made to solve such a conventional problem. According to the present invention, a transfer processing schedule for transferring a plurality of substrates to a plurality of transfer destinations in parallel without sequentially transferring the plurality of substrates is provided. When causing the substrate transfer apparatus provided in the semiconductor manufacturing apparatus to execute the transfer processing of the substrate, simultaneous transfer is performed even if a time lag occurs between the transfer processing schedule and the actual transfer processing process. An object of the present invention is to provide a transfer control method capable of ensuring the quality of a manufactured semiconductor product by avoiding and creating a new transfer processing schedule and executing a subsequent transfer processing according to the new schedule. I do. Further, the present invention, even in the case where a deviation time has occurred between the transfer processing schedule and the actual transfer processing process, even if the manufacturing process is stopped and the user does not perform a recovery operation or the like, Ensure product quality,
An object of the present invention is to provide a transport control method capable of ensuring scheduled quality and executing subsequent manufacturing processing.

[0016]

In order to achieve the above object, in the transfer control method according to the present invention, a transfer processing schedule for transferring a plurality of substrates sequentially and in parallel to a plurality of transfer destinations without simultaneously transferring a plurality of substrates is provided. According to the above, when the substrate transfer device provided in the semiconductor manufacturing apparatus executes the transfer process of the substrate, the transfer control process is performed in the following procedure. First, the transfer process by the substrate transfer device is monitored by a sensor or the like to detect a shift time between the transfer process schedule and the actual transfer process, and when a shift time is detected therebetween, the plurality of shift processes are performed. Among the substrates, a substrate for which the transfer processing has been started at the present time and a substrate for which the transfer processing has not been started are specified based on, for example, the execution status of the transfer processing schedule. Next, after correcting the transfer processing schedule of the substrate whose transfer processing has been started at present except for the part related to the substrate for which the transfer processing has not yet started from the transfer processing schedule, based on the shift time, the corrected transfer processing is performed. A new transfer processing schedule is created by adding the transfer processing schedule relating to the substrate for which transfer processing has not yet started to the schedule while avoiding simultaneous transfer. Then, the subsequent transfer processing is executed by the substrate transfer apparatus according to the created new transfer processing schedule.

Therefore, even if a time delay occurs between the transfer processing schedule and the actual transfer processing, a new transfer processing schedule is created by avoiding simultaneous transfer, and the new transfer processing schedule is created. Since the subsequent transfer processing for the substrate is performed according to the schedule, it is possible to prevent a decrease in product quality such as the film quality of the substrate and to execute the subsequent semiconductor manufacturing processing. Here, the semiconductor manufacturing apparatus according to the present invention includes not only an apparatus for processing a semiconductor wafer, but also an apparatus for processing a glass substrate for an LCD, etc. And a glass substrate for LCD and the like. Further, the process of sequentially transporting a plurality of substrates in parallel to a plurality of destinations without simultaneously transporting the substrates is, for example, a transport process performed by a substrate transport device performed based on the schedule shown in FIG. 9, This is a process of sequentially transporting a plurality of substrates to a plurality of destinations in parallel in time.

In the above-described transport control process,
A step of detecting a time lag between the transfer processing schedule and an actual transfer processing step; and a step of specifying a board for which transfer processing has been started and a board for which transfer processing has not yet started. The order in which the transfer processing is started is arbitrary, for example, the substrate on which the transfer processing has been started and the substrate on which the transfer processing has not yet started during the semiconductor manufacturing process are always monitored, and thus both these substrates may be always specified. In short, it suffices if it is possible to identify a substrate for which the transfer process has already been started and a substrate for which the transfer process has not yet started when the shift time is detected.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment according to the present invention will be described with reference to the drawings. In this example, an example in which a semiconductor manufacturing process such as a wafer transfer process is executed by the cluster type single wafer type semiconductor manufacturing apparatus 4 shown in FIG. It is assumed that a transfer processing schedule having the same contents as the transfer processing schedule for each wafer shown in FIG. 9 is stored in advance in the cluster controller 2 that integrally controls the manufacturing apparatus 4.

FIG. 1 shows an example of a transfer control process by the transfer control method according to the present invention. In this example, it is assumed that a transport processing schedule table 20a shown in FIG. In this table 20a, each wafer (W
AFER) for identifying a wafer I by, for example, a number.
D, the transfer start time, which is the time at which transfer of each of these wafers is started, and the transfer end time, which is the time at which this transfer is ended, and the names of the modules of the wafer transfer source and transfer destination in this wafer transfer processing. This is set in advance, and as described above, the same transport processing schedule as the schedule shown in FIG. 9 is set as the contents. It should be noted that, for example, “CM1” shown when the transfer source or the transfer destination is a cassette module in the drawing.
"-2" means slot 2 (wafer position) in cassette module CM1.

The planned wafer transfer processing and wafer processing in each process module as described above are monitored by the cluster controller 2, and the table 20a shown in FIG. For the transport process, the status of the process such as "completed" is indicated.
In addition, when waiting for the process to be completed in the process module for the next wafer to be transferred, a processing state such as “waiting for time-up” is displayed. As the transfer control processing according to the table 20a as described above, first, the cluster controller 2 causes the semiconductor manufacturing apparatus 4 to start automatic operation (step S1). On the other hand, in the semiconductor manufacturing apparatus 4, the semiconductor manufacturing processing is performed on each wafer in the processing order according to the schedule (step S2), and at the same time, the wafer transfer processing and the process by the substrate transfer apparatus (transport module TM) are performed. The wafer processing in the module is monitored by a sensor or the like, and each time the processing is completed, the completion of the processing is notified to the cluster controller 2.

When the cluster controller 2 receives from the semiconductor manufacturing apparatus 4 a notification notifying the end of each process described above (step S3), the scheduled time of the transfer process and the actual transfer in the transfer process schedule set in the table 20a are performed. Compare the execution time of the process in the process step,
It is determined whether or not a time lag occurs between them, and if a lag occurs, the lag time between them is detected (step S4). Here, in this example, when determining whether or not a time lag has occurred between the scheduled schedule and the actual processing process, a threshold value of, for example, 5 seconds is set for the lag time, and If a time lag that is equal to or longer than this threshold value occurs between the actual process and the actual process, it is determined that a lag time has occurred between the two, and this lag time is detected. The threshold value of the shift time may be set arbitrarily, and may be set based on the quality required for the manufactured product. Also, different threshold values may be set for each process.

If no time difference is detected between the planned schedule and the actual transport processing step by the above processing steps, the above processing steps (steps S2 to S4) are repeated. Then, the subsequent transport processing is continuously executed. On the other hand, when a time lag between the scheduled schedule and the actual transport processing is detected, the cluster controller 2 controls the transport processing as follows. First, a wafer that has already been taken out of the cassette module and the transfer process has started (started) when the shift time is detected,
The wafer whose transfer processing has not yet been started (started) is specified based on, for example, the execution status of the transfer processing schedule.

Here, in this example, the above-described table 20 is used.
In the transfer process according to a, time 30 seconds to 1 minute 3
The processing on the wafer 1 in the process module PM1 that was to be performed until 0 seconds actually requires an additional 30 seconds longer.
A case where a processing time of up to two minutes is required will be described. In this case, for example, the transfer processing of the wafer 1 that was to be started from the time 1 minute and 30 seconds is to be started from the time 2 minutes with a delay of 30 seconds and to be started from the time 2 minutes. At this point, the transfer process of the wafer 3 is not started. In this case, the cluster controller 2
However, the wafers 1 and 2 are specified as the wafers for which the transfer processing has already been started at the time when the delay time is detected, and the wafer IDs of which the transfer processing has not been started and the wafer IDs of “3” or later ( Wafer 3) is specified.

Next, the cluster controller 2 detects the transfer processing schedule for the wafer for which the transfer processing has already been started, except for the schedule for the wafer for which the transfer processing has not been started yet. Correction based on time (step S
5). That is, in the case of the present example, as shown in a table 20b shown in FIG. 3, the schedule relating to the wafers 3 and subsequent wafers for which the transfer process has not yet been started is removed from the table 20a, and the schedule from the time when the delay time occurs Also, the scheduled time of the transfer process for the wafer 1 performed later is delayed by 30 seconds, and similarly, the scheduled time of the transfer process for the wafer 2 performed later than the time when the delay time occurs is delayed by 30 seconds.

As a method of such a correction processing, for example, a schedule for the wafer 3 and thereafter is stored in a table 20a.
This is performed by delaying the schedule for each of the wafers 1 and 2 after the deletion. However, the method of this correction processing is arbitrary. For example, the schedule set in the table 20a is temporarily delayed for all the wafers. After that, the schedule for the wafer 3 and thereafter may be deleted. FIG. 4 shows a schedule of a transfer process and the like for the wafers 1 and 2 after the correction corresponding to the table 20b. The contents of the schedule shown in FIG.
The contents are the same as the contents of the table 20b. Further, the state of the processing step at this point is as follows.
It has just been transferred from the process module PM1 to the process module PM2 during 0 seconds.

Here, when the above-described schedule correction processing is performed, the wafer 2 for which the transfer processing has already been started at the time when the deviation time is detected is determined.
For example, as shown in FIG.
The module is left in the module for 30 seconds longer than the processing time (1 minute and 30 seconds) scheduled in the step 3, and the quality of the product cannot be guaranteed. For this reason, in this example, a new transfer processing schedule is created by further correcting the schedule for the wafer 2 while ensuring the originally planned processing procedure for the wafer 2 below. For a wafer, such as the above-described wafer 2, for which a part of the processing has already been started at the time when the shift time is detected, a procedure which is also planned by the correction processing of a further schedule described below. Since it is not always possible to make a schedule as described above, it is optional whether or not to perform the further correction processing described below.

That is, in this example, as shown in the table 20b, the time between the time of 2 minutes 30 seconds to 3 minutes and the time of 4 minutes to
Since there is no schedule for the transfer processing of the wafer 1 as described above in any of the time periods of 4 minutes and 30 seconds, by utilizing these idle times, the wafer 2 can be used.
Can be further corrected to the original schedule, and the original processing procedure for the wafer 2 can be secured. Here, this correction processing is the above-mentioned further correction processing. As described above, it is assumed that the transfer processing of the wafer 1 has been scheduled at the time when the transfer processing of the wafer 2 was originally scheduled. Cannot perform this further correction process on the wafer 2.

After the schedules for the wafers 1 and 2 have been corrected as described above, the cluster controller 2 determines that the transfer processing has not started yet for the wafers 3 and subsequent wafers at the time when the shift time has occurred. The schedule is incorporated into the corrected transport processing schedule as follows. In this example, the schedule reloading process is performed in the order of the wafer IDs (wafer 3, wafer 4,...), And first, the schedule of the wafer 3 is corrected as described above. The process of moving into the transfer process schedule for the wafer 2 will be described.

First, a search is made, for example, in ascending order of time, to determine whether there is a free time in the gap between the scheduled transfer times for the wafers 1 and 2 incorporated in the corrected schedule (step S6). The vacant time is, for example, from 3 minutes to 3 minutes and 30 seconds, and during this time, there is no schedule for the transfer process for the wafers 1 and 2. In this case, when the schedule is set to transfer the wafer 3 from the cassette module CM1 (slot 3) to the process module PM5 by utilizing the idle time, the time of another subsequent transfer processing of the wafer 3 is performed. In addition, a necessary condition is that the schedule of the transfer process by the substrate transfer device is vacant, that is, simultaneous transfer is avoided.

Therefore, next, in the case described above, the wafer 3
Is the time required to process the wafer 3 in the module PM5 at the time 3 minutes 30 seconds when the transfer process to the process module PM5 is completed.
By adding minutes, time A expected to take out the wafer 3 from the module PM5, that is, time 4
Minute and 30 seconds are calculated (step S7), and it is confirmed whether the transfer processing of the wafer 3 can be performed at the time A, that is, whether or not the transfer processing of another wafer is scheduled (step S8).

When a plurality of transfer processes are performed in a series of processes in the semiconductor manufacturing apparatus 4 such as the wafer 3, for example, the above confirmation process ( Steps S7 to S8) are performed simultaneously. For example, for the wafer 3, there is a vacancy in the transfer processing schedule at the scheduled transfer time of 4 minutes 30 seconds to 5 minutes, and the process module PM 6 to be further performed on the wafer 3 to the cassette module CM 2 (slot 3) Scheduled time 7 minutes to 7
It is confirmed that the schedule of the transfer processing schedule is vacant even for 30 minutes, and it is determined that the schedule for the wafer 3 is to be included in the empty time, and the schedule is included in the transfer processing schedule (step S9). .

The above processing (steps S7 to S8)
In the case where the transfer processing of another wafer has already been scheduled at the scheduled time of any transfer processing for the wafer 3, another gap is again set from the gap in the schedule for the already set other wafer. The vacant time is searched (step S6), and the above processing (steps S7 to S7) is performed.
Repeat step 8). Further, when there is no free time in the gap in the schedule for the wafer already set in the table, or even if there is a free time, as a result of the above-described confirmation processing, any of these free times can be used. If the schedule of the wafer 3 cannot be incorporated by avoiding simultaneous transfer, the schedule at the end of the table, that is, a time later than the time at which the schedule for all the other wafers already set in the table is expected to end is set. The schedule of the wafer 3 is recalculated (step S11).

Next, by the same renormalization processing as in the case of the wafer 3 described above, the schedule of the wafers after the wafer 4 is also changed to the transfer processing schedule by avoiding simultaneous transfer with the wafers for which the transfer processing is already set. The process is sequentially performed (step S10). By the above processing steps, a new transport processing schedule table 20c as shown in FIG.
Causes the substrate transfer apparatus to execute the subsequent transfer processing according to the newly created transfer processing schedule (step S2). FIG. 6 shows a schedule of the semiconductor manufacturing process corresponding to the table 20c shown in FIG. 5, and the content of the schedule is the same as the content of the table 20c.

Therefore, according to a transfer processing schedule for sequentially transferring a plurality of substrates to a plurality of transfer destinations in parallel without transferring the plurality of substrates at the same time, the substrate transfer processing provided in the semiconductor manufacturing apparatus is performed. At this time, even if a time lag occurs between the transfer processing schedule and the actual transfer processing step, a simultaneous transfer processing is avoided as described above, and a new transfer processing schedule is created. Subsequent transport processing is performed according to a suitable schedule, so that the quality of the manufactured semiconductor product can be ensured. In addition, when the above-described transport control method is used, even if the above-described shift time has occurred, it is not necessary to stop the manufacturing process and perform a recovery operation by the user. The original normal operation state can be restored by a controller or the like that controls the semiconductor control device.

Further, in the above embodiment, when the schedule relating to the wafers for which the transfer process has not yet started at the time when the shift time has occurred, the free time is searched for in the order of earlier time and the transfer process is performed. Since the processing is performed, a new transfer processing schedule can be created so as to reduce the total processing time required to process all of the wafers to be processed. Here, in the above-described embodiment, a case has been described in which the processing time (1 minute) scheduled in advance for processing the wafer 1 in the process module PM1 is different from the actual processing time (1 minute 30 seconds). The schedule of the subsequent wafers 4, wafers 7,... In which the same processing as that of the wafer 1 is performed is also shown in FIG. A new transport processing schedule table 20c was created.

In this case, for example, as shown in FIG.
The cluster controller 2 previously stores a table 10 in which processing times expected to be required for each processing step are summarized. Then, for example, the process module P
It was confirmed that the time required for the actual processing (process recipe A) performed on the wafer 1 in M1 was different from the processing time (1 minute) scheduled in advance, and that an additional processing time of 30 seconds was required. In this case, the “1 minute” set in the table 10 is changed to “1 minute 30” required for actual processing.
Secondly, the actually required processing time is stored as a new set time, and is reflected when a new transport processing schedule is created (learning of delay time).

In the above embodiment, the transport control process according to the transport control method according to the present invention is performed by the processor executing a control program in a hardware resource (cluster controller 2) having a processor and a memory, for example. Although an example of the case has been described, in the present invention, the function means for performing each processing step described in the above-described transport control processing may be configured as an independent hardware circuit.

Further, in the above embodiment, the case where the delay time occurs in the wafer processing in the process module has been described. However, the cause of the time lag between the transfer processing schedule and the actual transfer processing step is as follows. For example, a shift time may occur during the substrate transfer processing by the substrate transfer apparatus, and the present invention ensures execution of a normal operation of the semiconductor manufacturing apparatus in response to the shift time thus generated. . In addition, the shift time is not necessarily limited to the case in which the actual transfer process is delayed from the scheduled schedule as in the above-described embodiment, and the schedule in which the actual transfer process is scheduled is not limited. Even when the process proceeds faster, a new transport processing schedule can be created according to the present invention to prevent a decrease in product quality.

Further, according to the present invention, when the shift time is detected, after correcting the schedule for the substrate for which the transfer process has already been started, the schedule for the substrate for which the transfer process has not yet been started is set. Since the corrected transport processing schedule is incorporated into the corrected transport processing schedule while avoiding simultaneous transport, if there are a plurality of free times where the schedule can be included, the schedule is incorporated using any available time. Is also good. At this time, the schedule may be added at a time earlier than the scheduled start time of the transport process.

Further, in the above embodiment, after detecting a time lag between the scheduled transfer processing schedule and the actual transfer processing step, the substrate for which the transfer processing has been started at this time and the transfer processing are still started. Although the substrate that has not been identified is specified, the order in which these two processing steps are performed is arbitrary. For example, the substrate whose transfer processing has always been started by the above-described cluster controller 2 and the substrate whose transfer processing has not yet started And the time difference between the scheduled transfer processing schedule and the actual transfer processing step may be monitored. In short, the transfer processing is already started when the shift time is detected. It suffices if it is possible to identify the substrate that has been moved and the substrate that has not yet started the transfer processing.

[0042]

As described above, according to the transfer control method of the present invention, semiconductor manufacturing is performed according to a transfer processing schedule for transferring a plurality of substrates in parallel to a plurality of transfer destinations sequentially without transferring the plurality of substrates simultaneously. When causing a substrate transfer device provided in the device to execute a substrate transfer process,
Even if a time lag occurs between the transfer processing schedule and the actual transfer processing process, a simultaneous transfer is avoided to create a new transfer processing schedule, and the subsequent transfer is performed according to the new schedule. Since the process is executed, the quality of a product manufactured by the semiconductor manufacturing apparatus can be ensured.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a transport control process according to an embodiment of the present invention.

FIG. 2 is an example of a preset transfer processing schedule.

FIG. 3 is a diagram for explaining correction of a transport processing schedule.

FIG. 4 is an example of a semiconductor manufacturing process schedule according to a corrected transport process schedule.

FIG. 5 is an example of a newly created transport processing schedule.

FIG. 6 is an example of a semiconductor manufacturing process schedule according to a newly created transport process schedule.

FIG. 7 is a configuration example of a cluster-type single-wafer semiconductor manufacturing apparatus and a controller.

FIG. 8 is a diagram for explaining a wafer processing route.

FIG. 9 is an example of a schedule for automatic operation in a semiconductor manufacturing process.

FIG. 10 is a diagram for explaining a shift time generated during wafer processing.

[Explanation of symbols]

1. Cluster-type single-wafer semiconductor manufacturing apparatus, 2. Cluster controller, 3. LAN, 4. Cluster-type single-wafer semiconductor manufacturing apparatus,

Claims (1)

[Claims] 1. A substrate transfer device provided in a semiconductor manufacturing apparatus executes a substrate transfer process according to a transfer process schedule for sequentially transferring a plurality of substrates to a plurality of transfer destinations in parallel without transferring the plurality of substrates simultaneously. In the transfer control method, a step of monitoring a transfer process by a substrate transfer device and detecting a time lag between the transfer process schedule and an actual transfer process, and a transfer process is started at the present time in the plurality of substrates. Identifying a board that has been transferred and a board for which transfer processing has not yet started, and a transfer processing of a board for which transfer processing has been started at the present time excluding a portion related to a board for which transfer processing has not been started from the transfer processing schedule. Correcting the schedule on the basis of the time lag; Creating a new transfer processing schedule by avoiding simultaneous transfer of the transfer processing schedule relating to the substrates for which the transfer has not started, and executing the transfer processing subsequent to the substrate transfer apparatus according to the created new transfer processing schedule A transport control method, comprising: