JPH10256234A - Manufacturing method of multilayer wiring - Google Patents

Abstract

(57) Abstract: A lower wiring 2, an insulating film 3, and an etching resistant film having a hole pattern are sequentially formed on a base substrate 1, and a selection is made using the etching resistant film as a mask. In a method of manufacturing a multilayer wiring in which a hole or a slot 6 is opened in the insulating film 3 by etching and an upper layer wiring 11 is formed by connecting the inside of the hole or the slot 6 and the upper surface of the insulating film 3, a fine and etching residue is removed. It is possible to form a hole 6 without
As a result, the wiring width can be reduced, and the semiconductor integrated circuit can be miniaturized and multi-functionalized accordingly. The problem is solved by using a composite film of a mask metal film 4 and a resist mask 5 as the etching resistant film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaAs-based
The present invention relates to a method for manufacturing wiring of a semiconductor integrated circuit such as an i-system communication IC and a hybrid microwave circuit.

[0002]

2. Description of the Related Art In the wiring of semiconductor integrated circuits such as GaAs-based and Si-based communication ICs / hybrid microwave circuits, a large number of wiring layers are connected via a thick insulating film in a VIA connection (connection perpendicular to the wiring layers). A three-dimensional wiring structure using a multilayer wiring structure formed as described above or a vertical structure such as this VIA connection as the wiring itself is effective for miniaturization and multifunctionalization of a circuit. (Reference: M. Hirano, et. Al., "Thre
e-Dimensional PassiveCircuit Technology for Ultra-
Compact MMIC's ", IEEE Trans. On MTT, Vol. 43, pp 2
845-2850, Dec. 1995.) FIG. 2 shows a conventional wiring forming method of this kind.

(A) After a lower wiring 2 and an insulating film 3 such as polyimide are sequentially formed on a base substrate 1 on which wiring is to be formed,
A resist mask 5 having a hole pattern or a groove pattern is formed thereon using a resist material.

(B) Using a resist mask 5 having a hole pattern or a groove pattern, an insulating film 3 is formed by reactive ion etching (RIE) using O ₂ as a main etching gas.
Then, a hole or a slot 6 reaching the surface of the lower wiring 2 is formed.

[0005] (c) The mask 5 is removed with an organic solvent or the like to obtain the state shown in (d).

(E) A first conductive film 7 as a barrier metal / milling stopper layer of a high melting point metal such as WSi or WSiN, and a low-resistance metal film are formed on the entire surface of the insulating layer including the inside of the hole. A second conductive film 8 as a plating electrode of Au or the like is continuously formed by a sputtering method. A third conductive film 9 of the same type as the second conductive film is grown thereon by electrolytic plating.

(F) Next, the region of the hole or slot 6 and the desired wiring pattern region are covered with a resist mask 10 and the conductive film 9 in an unnecessary region is etched by an etching technique such as milling.
And the conductive film 8 are removed.

(G) Thereafter, after the resist mask 10 is removed by oxygen plasma treatment (ashing) or the like, the first conductive film 7 other than the second and third conductive film wiring pattern portions is subjected to SF.
_The upper layer wiring 11 is formed by removing it by RIE using ₆ gases (Japanese Patent Application No. 3-53355).

[0009]

In order to reduce the size or increase the degree of integration of an integrated circuit, it is necessary to reduce the width of the wiring. However, in manufacturing, the width of the wiring must be larger than the diameter of the hole in the insulating film. There is. Therefore, in order to reduce the size or increase the integration of the integrated circuit, it is necessary to first reduce the diameter of the hole in the insulating film.

When a hole is formed in an insulating film, the shape and the like of the hole are greatly affected by the mask material. In the prior art, a resist mask was used. However, since the etching rate was almost the same as that of the insulating film, the peripheral edge of the mask pattern receded during the etching, and the diameter of the hole became large. (See FIGS. 2B and 2C).

On the other hand, there is a metal film mask as a mask having an extremely low etching rate as compared with an insulating film. When this is used, the peripheral edge of the mask pattern hardly recedes during the etching, but the metal film is slightly etched by the sputtering effect during the etching, and it scatters into the hole. If the diameter of the hole is large, the sputtering effect in the hole is almost the same as that on the surface of the insulating film, so the metal scattered in the hole is also etched by the sputtering effect, and the hole can be processed without any problem. Was. However, when the diameter of the hole is small, ions are difficult to enter, so that the sputtering effect in the hole is reduced, and the metal scattered in the hole cannot be etched. The remaining metal becomes a micromask (very small mask)
This causes the generation of needle-like residues. The needle-like residue reduces the effective hole area, and as a result, the contact resistance between the lower wiring and the upper wiring increases, and the circuit operation characteristics deteriorate.

[0012]

In order to solve the above-mentioned problems, in the present invention, a mask having a two-layer structure formed by covering a metal film with a resist is used as a mask for forming holes in an insulating film.

By using a metal film mask as a lower layer of the two-layer mask, the retreat of the periphery of the mask pattern during etching is suppressed, and the spread of holes is suppressed. As the material of the metal film,
WSi, WSiN, Ti or the like is used. Since such a metal has extremely high resistance to anisotropic etching using oxygen gas, a relatively hard-to-etch material such as polyimide or a bisbenzocyclobutene polymer is used by using this as a mask. Even when is used as an insulating film, fine and accurate etching can be performed at a practically sufficient speed.

Further, by covering the metal film mask with a resist mask, scattering of the metal film during etching can be suppressed, and generation of needle-like residues can be eliminated. In this case, the initial film thickness of the resist is desirably such that the resist covers the metal film until the formation of the holes in the insulating film is completed. When a Si-containing resist is used as the resist, the resist has good resistance to the etching of the mask metal film and the etching of the insulating film. The condition of covering is easy to hold.

Further, when anisotropically etching the insulating film,
Even if the scattering of the metal film is suppressed by the above-described method, an etching residue may still be observed. In this case, 1 to 10% by volume of C
Addition of F ₄ , He, or Ar can prevent generation of a residue.

As described above, by implementing the present invention, it is possible to form a fine hole having no etching residue in the interlayer insulating film, thereby reducing the wiring width and the accompanying miniaturization of the semiconductor integrated circuit. And multi-functionalization becomes possible.

[0017]

DETAILED DESCRIPTION OF THE INVENTION In the present invention, in forming wiring of a semiconductor integrated circuit, a metal film for a mask is first deposited on an interlayer insulating film as an etching mask for forming a hole in an insulating film. After forming a mask having a hole pattern using a resist material thereon, holes are formed in a metal film using a resist mask, and holes are formed in an insulating film using a two-layer mask of the metal film and the resist. Thereby, a minute hole without residue is formed.

FIG. 1 shows an embodiment of the present invention. Hereinafter, this embodiment will be described.

(A) Lower wiring 2, thick insulating film 3 of polyimide or bisbenzocyclobutene polymer (BCB) or the like, WSi, WSi
After sequentially forming a mask metal film 4 of N, Ti or the like, a mask 5 having a hole pattern is formed thereon using a material such as a Si-containing resist. At this time, the thickness of the resist mask 5 is set to such a thickness as to remain even after the etching of the mask metal film 4 and the etching of the insulating film 3. Since the Si-containing resist has good resistance to these two types of etching, the requirements for the resist film thickness are:
It is easily satisfied by using a Si-containing resist.

(B) Resist mask 5 having hole pattern
The hole pattern is transferred to the mask metal film 4 by RIE using SF ₆ gas.

(C) Using O ₂ as the main etching gas,
RIE to which a small amount of gas such as F ₄ , He or Ar is added
Thereby, a hole or a slot 6 reaching the surface of the lower wiring 2 is formed in the insulating film 3. Similar effects were obtained when the concentration of the added gas was in the range of 1 to 10% by volume.

(D) After the resist mask 5 is removed by RIE using an organic solvent or O ₂ gas, the mask metal film 4 is removed by RIE using SF ₆ gas.

(E) First, a refractory metal such as WSi or WSiN is formed over the entire surface of the insulating film including the inside of the hole or the slot 6.
The first conductive film 7 as a barrier metal / milling stopper layer, etc., and the second conductive film 8 as a plating electrode such as Au which is a low resistance metal film are continuously formed by sputtering. A third conductive film 9 of the same type as the second conductive film is grown thereon by electrolytic plating.

(F) Next, the hole area and the desired wiring pattern area are covered with a resist mask 10, and unnecessary areas of the conductive film 9 and the conductive film 8 are etched by an etching technique such as milling.
Is removed.

(G) Thereafter, after the resist mask 10 is removed by oxygen plasma treatment (ashing) or the like, the first conductive film 7 located in a place other than the second and third conductive film wiring pattern portions is SF-coated. _The upper wiring 11 is formed by removing by RIE or the like using ₆ gases.

[0026]

As described above, according to the present invention, it is possible to form fine holes without residue in an insulating film. According to the present invention, the wiring width can be reduced, and
And miniaturization and multifunctionalization of semiconductor integrated circuits such as IC-based and Si-based communication ICs and hybrid microwave circuits.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a wiring forming step according to the present invention.

FIG. 2 is a cross-sectional view schematically showing a wiring forming step according to a conventional technique.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 base substrate 2 lower wiring 3 insulating film 4 metal film for mask 5 resist mask 6 hole or groove 7
... first conductive film, 8 ... second conductive film, 9 ... third conductive film, 10 ... resist mask, 11 ... upper layer wiring.

Claims (6)

[Claims] 1. A step of sequentially depositing at least one lower wiring, an insulating film and a mask metal film on a substrate, and forming a resist film having a hole pattern or a groove pattern on the surface of the mask metal film. Performing a selective etching of the mask metal film using the resist film as a mask to expose the insulating film; and performing anisotropic selection of the exposed insulating film using the mask metal film as a mask. Etch,
Forming a hole-shaped or slot-shaped opening reaching the lower wiring, removing the resist film and the mask metal film, connecting the bottom surface, the side surface, and the upper surface of the insulating film of the opening; Forming an upper layer wiring by performing the method. 2. The method according to claim 1, wherein the resist film has a thickness necessary to remain on the mask metal film even after the etching of the insulating film. 3. The method according to claim 1, wherein the mask metal film is made of WSi, WSiN,
2. The method according to claim 1, wherein the multilayer wiring is made of Ti. 4. The method according to claim 1, wherein the resist film is made of a Si-containing resist. 5. The method according to claim 1, wherein the insulating film is made of a polyimide or a bisbenzocyclobutene polymer. 6. The multilayer wiring according to claim 1, wherein the gas used for the anisotropic selective etching is a gas obtained by adding CF ₄ , He, or Ar to an oxygen gas at 1 to 10% by volume. Production method.