JPH10254788A - Multi-bank constitution storage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the delay time of data in an error detecting and correcting circuit(EC circuit) to <2T and to shorten the reception and passing time of read data by providing each bank with an ECC circuit excluding a flip-flop. SOLUTION: ECC circuits are provided for each bank. For example, data read out of a bank 0 is outputted and inputted to a flip-flop 2-2. Then the data are outputted from the flip-flop 2-2 and sent out to an ECC circuit 2-4 on the side of the bank 0. At this time, readout data outputted from a bank 1 inputted to a flip-flop 2-3. On the side of the bank 0, flip-flops which store and hold data are eliminated among circuits constituting the ECC circuit 2-4, so there is neither their circuit delay nor lock skew and the time of data transfer by a syndrome generating circuit 2-8, etc., is shortened correspondingly. The data transfer time of the ECC circuit 2-5 on the side of the bank 1 is shortened as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-bank configuration storage circuit, and more particularly to a multi-bank configuration storage circuit having an error detection / correction circuit, in which data is read and written from separate terminals.

[0002]

2. Description of the Related Art A conventional multi-bank configuration memory circuit having an error detection and correction function, in which data reading and writing are performed from separate terminals, as disclosed in Japanese Patent Application Laid-Open No. 2-22047, etc. As shown in FIG. 5, an error detection / correction code generation / addition circuit (hereinafter referred to as an ECG circuit) for adding a redundant bit for error detection / correction at the time of writing is provided on the writing side. An error detection and correction circuit (hereinafter, referred to as an ECC circuit) for detecting and correcting an error using a redundant bit is provided on the read side, and is shared by each bank.

As an example, a reading side of a storage circuit having a two-bank configuration shown in FIG. 6 will be described.

The storage circuit 6-1 has a flip-flop 6-2 for inputting read data from the bank 0, a flip-flop 6-3 for inputting read data from the bank 1, and read data of either the bank 0 or the bank 1. 6-6, an ECC circuit 6-5, and a flip-flop 6-11.

The ECC circuit 6-5 includes a syndrome generation circuit 6-6, a flip-flop 6-7, an error data detection circuit 6-8, a flip-flop 6-9, and an error data correction circuit 6-10. .

The read operation of storage circuit 6-1 will be described.

First, the read data from the bank 0 is input to the flip-flop 6-2, and the selector 6-4 which selects the bank 0 after one clock cycle (hereinafter, n clock cycle is called nT, in this case, 1T), the syndrome, The signal passes through the generation circuit 6-6 and is input to the flip-flop 6-7. At this time, the read data from the bank 1 has been input to the flip-flop 6-3.

Thereafter, the read data from bank 0 is output from error data detecting circuit 6 1T after flip-flop 6-7.
The signal is input to the flip-flop 6-9 through -8, and after 1T, is input to the final-stage flip-flop 6-11 via the error data correction circuit 6-10.

Similarly, the read data of bank 1 passes through ECC circuit 6-5 and is input to flip-flop 6-11 with a delay of 1T from the read data of bank 0.

Referring to the time chart of FIG. 4, both the read data from the flip-flop 6-2 of the bank 0 and the read data from the flip-flop 6-3 of the bank 1 are output, and the ECC circuit 6-5 is operated. 3T until they are input to the final stage flip-flop 6-11.
Of time.

[0011]

In the above-described conventional multi-bank configuration storage circuit, the bank 0 and the bank 1 are provided with E
Since the CC circuit is shared, a flip-flop circuit for holding and storing data is inserted between each of the syndrome circuit, the error data detection circuit, and the error data correction circuit constituting the ECC circuit, and the bank in the ECC circuit is inserted. This prevents data read from 0 and bank 1 from being mixed. Therefore, there is a disadvantage that the time required for the processing of the ECC circuit requires 3T.

Therefore, if the clock period is made longer than the transit time of the ECC circuit, data can be prevented from being mixed in the ECC circuit, but there is a drawback that the data read time becomes longer.

[0013] It is an object of the present invention to provide each bank with an EC.
By providing a C circuit, the flip-flop circuit in the ECC circuit is eliminated by avoiding the mixture of data between banks and the EC
It is an object of the present invention to provide a multi-bank configuration storage circuit capable of shortening the transfer time of read data by shortening the data passage time of the C circuit within 2T.

[0014]

According to a first aspect of the present invention, there is provided a multi-bank configuration storage circuit for detecting and correcting an error in read data in a multi-bank configuration storage circuit in which data reading and writing are performed from separate terminals. Each bank is provided with an error detection and correction means having no clock data holding function, and a selection means for selecting and outputting the output of each error detection and correction means.

[0015] A multi-bank configuration storage circuit according to a second aspect of the present invention comprises:
In the multiple bank configuration storage circuit according to the first aspect of the invention, the error detection and correction unit includes a syndrome generation unit, an error data detection unit, and an error data correction unit, and holds data by a clock between the components. It is characterized by having no function.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a storage circuit having a plurality of banks according to the present invention.

As shown in FIG. 1, the multiple-bank configuration storage circuit according to the present embodiment is provided with an ECC circuit for each bank. As will be described later, a syndrome circuit and an error data The flip-flop circuit that holds and stores data between each of the detection circuit and the error data correction circuit is omitted.

FIG. 2 shows a multi-bank configuration storage circuit according to one embodiment of the present invention.

The storage circuit having a plurality of banks shown in FIG. 2 is a storage circuit having a two-bank configuration. The storage circuit 2-1 has a flip-flop 2- which inputs read data from the bank 0.
2. Flip-flop 2-3 for inputting read data from bank 1, ECC circuit 2-4 on bank 0, ECC circuit 2-5 on bank 1, selector 2 for selecting read data from bank 0 or bank 1 -6 and a final stage flip-flop 2-7.

The ECC circuit 2-4 and the ECC circuit 2-5 include a syndrome generation circuit 2-8, a syndrome generation circuit 2-11, and an error data detection circuit 2-5, respectively.
9, an error data detection circuit 2-12, an error data correction circuit 2-10, and an error data correction circuit 2-13. There is no flip-flop for holding and storing data between the circuits, and the circuits are directly connected. I have. This is ECC circuit 2
-4 and the ECC circuit 2-5 are provided for each bank, so that the ECC circuit 2-4 and the ECC circuit 2-5 are provided.
Since the data of different banks are not mixed, the data holding function can be deleted.

Next, the operation of this embodiment will be described with reference to FIG.

First, read data is output from bank 0 and input to flip-flop 2-2. Next, data is output from the flip-flop 2-2 and sent to the ECC circuit 2-4 on the bank 0 side. At this time, the read data output from the bank 1 is input to the flip-flop 2-3.

On the bank 0 side, the circuit delay and clock skew are eliminated between the circuits constituting the ECC circuit 2-4 because the flip-flops for holding and storing data are deleted as described above. Therefore, the data transfer time by the syndrome generation circuit 2-8, the error data detection circuit 2-9, and the error data correction circuit 2-10 is shortened accordingly.

Similarly, the data transfer time of the ECC circuit 2-5 on the bank 1 side is reduced. The reduced time will be described.

Assuming that the delay times of the syndrome generation circuit 2-8, the error data detection circuit 2-9, and the error data correction circuit 2-10 are substantially equal to k, the delay time of the flip-flop is f, and the clock skew is s, Conventional EC of FIG.
The maximum delay time of the C circuit 6-5 (including the flip-flop 6-11) is 3 (k + f + s),
Since this requires 3T, 2 (k + f + s)>T> (k + f + s). The upper limit of T in the above equation is equal to that of the conventional ECC circuit 6−.
5, the delay time from the syndrome generation circuit 6-6 to the flip-flop 6-9 and the delay time from the error data detection circuit 6-8 to the flip-flop 6-11 are longer than the clock cycle. It is a restriction from the thing.

On the other hand, the ECC circuit 2-4 of FIG.
And the ECC circuit 2-5 (in each case, the flip-flop 2-
7), and the delay time is (3k + f + s)
Since this is shorter than the delay time required for the conventional ECC circuit by the amount of removing the flip-flop (of course, smaller than 3T), if this is further shorter than 2T, this time is substantially shortened. The effect can be used for data transfer.

Therefore, the condition of T for making the delay time shorter than 2T is as follows: T> (3k + f + s) / 2 from 2T> (3k + f + s).

Since ((3k + f + s) / 2)> (k + f + s), the clock cycle T must be 2 in order for the multi-bank configuration storage circuit of the present embodiment to exhibit the effect at the same clock cycle as the conventional example. (K + f + s)>T> (3k + f + s) / 2.

That is, if the clock cycle of the conventional circuit is in the range of the above equation, the processing time of the ECC circuit can be reduced by 1T by adopting the configuration as in the present embodiment.

To give a specific numerical example, k = 5 ns,
If f = 0.5 ns and s = 0.3 ns, 11.6 ns>T> 7.9 ns That is, if the clock cycle of the conventional circuit is 9 ns,
With the configuration as in this embodiment, the processing time of the ECC circuit can be reduced by 9 ns.

FIG. 3 is a time chart showing the operation of the storage circuit of FIG. Under the above conditions, both the data read from the bank 0 and held in the flip-flop 2-2 and the data read from the bank 1 and held in the flip-flop 2-2 are both flip-flops 2T after 2T. -7, and it is understood that the time is shortened by 1T even in comparison with FIG. 4 showing the operation of the conventional circuit.

As described above, the multi-bank configuration storage circuit of this embodiment reduces the processing time of the ECC circuit by one clock cycle for a clock cycle within a certain range by providing the ECC circuit for each bank. This has the effect that the transfer time of the read data to another can be advanced by one clock cycle.

[0034]

As described above, in the multi-bank configuration storage circuit of the present invention, the processing time of the ECC circuit is reduced by one clock cycle for a clock cycle within a certain range by providing an ECC circuit for each bank. This has the effect that the transfer time of the read data to another can be advanced by one clock cycle.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an n-bank configuration storage circuit according to the present invention.

FIG. 2 is a block diagram showing one embodiment of a two-bank configuration storage circuit of the present invention.

FIG. 3 is a time chart illustrating an example of an operation in the two-bank configuration storage circuit of the present embodiment.

FIG. 4 is a time chart showing an example of an operation in a conventional two-bank configuration storage circuit.

FIG. 5 is a block diagram showing a configuration of a conventional n-bank configuration storage circuit.

FIG. 6 is a block diagram showing a configuration of a conventional two-bank configuration storage circuit.

[Explanation of symbols]

2-1 5-1 6-1 Storage circuit 2-2, 2-3, 2-7, 6-2, 6-3, 6-7, 6
-9, 6-11 Flip-flop 2-4, 2-5, 6-5 ECC circuit 2-6, 6-4 Selector 2-8, 2-11, 6-6 Syndrome circuit 2-9, 2-12, 6-8 Error Data Detection Circuit 2-10, 2-13, 6-10 Error Data Correction Circuit

Claims (2)

[Claims] In a multi-bank configuration storage circuit in which data read and write are performed from separate terminals, error detection and correction means for detecting and correcting errors in read data and having no data holding function by a clock is provided for each bank. And a selecting means for selecting and outputting an output of each of the error detection and correction means. 2. The error detecting and correcting means comprises a syndrome generating means, an error data detecting means, and an error data correcting means, and does not have a function of holding data by a clock between the constituent means. 2. The multi-bank configuration storage circuit according to claim 1, wherein: