JPH10254512A - Programmable controller, power supply unit for programmable controller, reactuating device for programmable controller, and computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make short the word length of a part corresponding to a process I/O group and to improve memory use efficiency, etc., by outputting a select signal to a process I/O group corresponding to a register means when address information matches information written in the register means. SOLUTION: A comparator 404 outputs a coincidence detection signal 414 to a specific corresponding process I/O group 402 when the value of a register 403 matches the contents of a high-order address 412. In this case, the value from the register 403 does not match the contents of the high-order address 412 as to another pair of a comparator 404 and a register 403, so the corresponding process I/O group 402 is never selected. The process I/O group 402 having received the coincidence detection signal 414, on the other hand, specifies a process I/O that an application program is to use by using the low-order address 413 of an address 411 inputted through a bus 312.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a programmable controller, a programmable controller power supply device, a programmable controller restart device, and a computer.

[0002]

2. Description of the Related Art Programmable controllers are widely used in plants and the like as devices for controlling various control objects.

FIG. 19 is a functional conceptual diagram of a general programmable controller.

FIG. 20 is a diagram showing a specific hardware configuration example corresponding to the programmable controller shown in FIG.

[0005] The programmable controller 301 controls the control target 302, and controls the control target 30.
2 receives a control signal or receives an output of a measured value or the like from the control target 302 and performs various processes. Such input / output signals are transmitted between the external input / output means 303 and the control target 302. Further, the external input / output unit 3 is connected to a signal transmission unit 304, which is further connected to a data control unit 305, a data storage unit 306, and an abnormality detection unit 307. The data control unit 305 and the abnormality detection unit 307 can exchange information with each other.

Next, the programmable controller 301
Will be described more specifically with reference to FIG.

First, a microprocessor 311 is used as the data control means 305.

The microprocessor 311 controls transmission of data via a bus 312 such as an address bus for transmitting an address information signal, a data bus for transmitting a data information signal, and a control signal bus for transmitting a control signal. I do. In addition, each memory 313, 314 and each I / O 315, 316
Process the data input from
Output to O.

Next, as the data storage means 306, R
AM 313 and ROM 314 are used.

The RAM 313 is a rewritable memory means, and is used for working the microprocessor 311 and for storing control information handled by an application program unique to the control system. However, normally, when the power is turned off, the stored information is erased, or more precisely, replaced with another data.

The ROM 314 is normally a non-rewritable memory, but has a characteristic that information can be retained even when power supply is cut off. The purpose of using the ROM 314 is to store an initialization program for causing the microprocessor 301 to perform an operation at the time of initialization including power-on of the programmable controller 301.
Depending on the capacity of the ROM 314, not only an initialization program but also a program of an operating system of the microprocessor 311 may be stored.

Next, the abnormality occurrence detecting means comprises a parity detecting device 317, a watch dog timer device 318 and the like.

The parity detection device 317 is connected to the bus 312, performs a parity operation to determine the validity of data, and outputs the result to the microprocessor 31.
Notify 1. The parity error indicates an error due to destruction or loss of all or part of the data.

The watchdog timer 318 (hereinafter referred to as W
DT 318) is periodically triggered by the microprocessor 311. When this trigger is received, the value being timed is initialized, and if the trigger generation stops, a timeout occurs. Stopping the trigger is considered to mean stopping the microprocessor 311, and the timeout output is used as a stop detection output of the microprocessor 311.

Next, the external input / output means corresponds to a device connected to the microprocessor 311 except for a memory. These are generally referred to as I / O ports and often refer to devices having special functions used around the microprocessor. However, in the programmable controller 301 shown in FIGS. 19 and 20, such a general I / O port 315 is provided, and an input / output device called a process I / O 316 is added. The process I / O 316, unlike the I / O port 315, is not primarily intended for direct service to the microprocessor 311. In other words, the purpose is to serve as an interface between the programmable controller 301 and the control target 302 for a control target 302 called a specific process or plant controlled by the programmable controller 301.

Next, of the signal transmission means 304, a bus 312 for address signals, data signals, input / output control signals, etc.
The (signal transmission path) is configured using a conductor of a printed circuit board or a cable. Each of the above-mentioned signals is composed of a plurality of bits.
Depending on the specifications of the O port, data width conversion may be required. At this time, a device called a gate or a buffer is inserted as a signal connection control means (not shown). Gates and buffers may be inserted to limit the length of the signal transmission path when the signal transmission path becomes longer and the effect of the stray capacitance cannot be ignored.

Next, a power supply device for converting a commercial AC power supply to a DC power supply for an electronic circuit is used as power supply means (not shown in FIG. 19). Alternatively, a power supply device that converts a DC power supply input into another electronic circuit DC power supply may be used.

The power supply means is a main power supply used during normal operation of the above-mentioned device, and saves data of the programmable controller even when the main power supply is cut off at the time of power failure or maintenance work. An auxiliary power supply for operation may be provided separately.

This auxiliary power source is a non-rechargeable primary battery,
Alternatively, a means for storing energy using a chemical reaction such as a rechargeable secondary battery is often used, and an energy storage means which does not use a chemical reaction such as a large-capacity capacitor may be used as an auxiliary.

[0020]

The conventional programmable controller configured as described above has problems to be solved as described below.

First, the first problem will be described.

FIG. 21 is a diagram showing a conventional process I / O selection device.

When the process I / O 316 is connected to the microprocessor 311, it is usually necessary to prepare an appropriate selection means for connecting several tens of process I / Os 316. Normally, this selection means is
This is realized by a device called a combinational logic decoder 801 that associates a specific combination of the state of the address signal output by the first and a specific process I / O 316.

Further, in order to prevent the use of a small number of process I / Os or a large number of process I / Os from being wasted in terms of cost, a unit for applying the hierarchical structure and including the microprocessor 311 is provided. It is advantageous to divide the process I / O 316 into units each having a predetermined number and add a unit of the process I / O as needed. FIG. 21 shows a process I including a plurality of units.
The state where the decoder 801 outputs a selection signal to the / O group 802 is shown.

In this method, a device called a master interface is inserted in a unit in which a CPU (microprocessor 311) is inserted. The unit of the process I / O 316 includes a device called a bus interface. The master interface manages process I / O on a unit basis. The bus interface individually manages the process I / O in the unit.

In this case, when the upper part of the address is handled in the master interface and the lower part of the address is handled in the bus interface, the hardware is simplified and the management is simplified.

However, if it is attempted to handle a large number of process I / O units, the number of process I / O groups 802 increases, and the amount of information of upper addresses required by the master interface increases. That is, the result is as shown in FIG.

FIG. 22 is a diagram showing a conventional resource map.

As shown in FIG.
When the number of / O groups 802 increases, in a program describing the content of the programmable controller 311 controlling the control target 302, address information including an upper address and a lower address is described every time the process I / O 316 is accessed. Must. Since the increase in the address information has an effect on the increase in the information amount of the program, there is a problem that the efficiency of the memory for storing the program deteriorates.

Next, the second problem will be described.

The microprocessor 311 executes the process I /
As a means for selecting O316, the combinational logic decoder 801 is used as described above. Here, the address to which the process I / O is allocated is the process I / O.
Rules may be created to correspond to the type of O316 and the position of the unit to be mounted. This is because a simple hardware configuration can be realized in this way.

FIG. 23 is a diagram showing a conventional address conversion memory setting method.

However, when the address is set in this way, that is, as shown in FIG. 23 (811) and the application program is executed (812), the address of the process I / O 316 used in a specific control program is set. May be intermittent depending on the type and mounting position.
In such a situation, it becomes difficult to handle addresses on software.

In order to solve the above problem, conventionally, the system of the address information output from the processor 311 and the system of the address information received by the process I / O 316 are different, and an address conversion memory means for associating the two systems. There is a method of providing. This method is a method of realizing conversion between the two systems by hardware table lookup using an address conversion memory. In this method, if the address translation memory is appropriately set, the microprocessor can treat the process I / O groups as if they were intensively allocated to a limited narrow area.

However, if the address translation memory is rewritten to unexpected information due to disturbances such as noise or other causes, the microprocessor may fail even if a failure has not actually occurred in the process I / O. There is a problem that determination may be made or input / output may be made to a process I / O different from the intended one.

Next, the third problem will be described.

In a system in which the data in the RAM 313 is retained when the main power supply is turned off, the above-described auxiliary power supply such as a battery is indispensable.

When a secondary battery that can be charged to this battery is used, the battery is overcharged due to a failure in the charging circuit.
Dangers such as heat, smoke, and ignition cannot be eliminated.

In order to avoid this, when using a primary battery,
Replacement due to battery consumption is indispensable, and there is a problem that maintenance labor costs increase.

Next, the fourth problem will be described.

During maintenance of a power supply device that converts the voltage and frequency from a high-voltage primary power supply and supplies the primary power from the terminal block, it is confirmed that the high-voltage side voltage has completely disappeared during maintenance. Otherwise, there is a risk of electric shock and it is dangerous.

FIG. 24 is a diagram showing a configuration example of a conventional power supply device.

Usually, the main switch of the primary power supply is often separated from the power supply, and it is necessary to provide another device to know that the high voltage has disappeared on the power supply side. There are issues.

Next, the fifth problem will be described.

When performing maintenance work on a power supply device that converts a voltage or frequency from a high-voltage primary power supply and outputs it,
Normally, the high-voltage charging section protected by a cover or the like is exposed and is dangerous.

It is often not possible to clearly indicate which part of the high-voltage charging section in the power supply is due to space restrictions.

Therefore, it is a common practice to shut off the primary power supply and leave it for a while to wait for discharge.

However, the amount of time to be left varies depending on the device, and the danger cannot be completely removed. Leaving it for a long time to ensure safety even a little causes a reduction in work efficiency and an increase in labor costs.

Next, the sixth problem will be described.

When a voltage or frequency is converted from the primary power supply to the secondary power supply, if there is a loss accompanying the conversion, this loss is usually discarded as heat. In order to perform the heat radiation efficiently, it is better to increase the temperature difference between the heat generating part and the surroundings. For this reason, there is a high temperature part in the power supply unit that often causes burns when touched.

Normally, this high-temperature portion is protected by a cover or the like so that it is not accidentally touched. However, when disassembling the device such as during maintenance work, it is impossible to prevent the risk of touching the device without cooling. There is.

Next, the seventh problem will be described.

In the conventional method, even if a bus error has occurred, its location cannot be specified. In this case, even if a failure is detected and it is found that an abnormality has occurred in the bus, there is a problem that it is not possible to accurately and quickly identify and deal with an abnormal position.

Next, the eighth problem will be described.

FIG. 25 is a diagram showing an example of the configuration of a portion relating to the stoppage of the abnormality detection system in a conventional programmable controller.

Conventionally, when an abnormality is detected in the programmable controller, the content of the abnormality is determined by the abnormality detecting means 307, and restoration is performed if possible.

In the case of a simple abnormality, the abnormality is repaired and the abnormality is recovered, but in the case of an extremely serious abnormality, the abnormality cannot be repaired.

More specifically, as shown in FIG.
When an error is detected by the circuit 251 and transmitted to the NMI circuit 252 by the WDT error signal 2511,
The NMI circuit 252 sends an NMI signal 2512 to the CPU 253.
Issue Based on this notification, the CPU 253 performs the NMI processing, and after inactivating the CPU 253, terminates the operation. Note that the reset circuit 255 shown in FIG.
Is for restarting the system after stopping.

In the case of such a serious abnormality, there is a problem that the abnormality cannot be repaired and the system stops.

Next, the ninth problem will be described.

In the case of the eighth problem, even if a measure for avoiding a system stop is taken, if the failure mode is a permanent failure, the system itself cannot be recovered. In such a case, there is a possibility that the system cannot be normally stopped by repeatedly stopping and starting the system.

The present invention has been made in view of such circumstances, and a programmable controller, a power supply device for a programmable controller, and a programmable controller capable of solving any of the above-mentioned problems 1 to 9 are provided. It is an object of the present invention to provide a restart device and a computer.

[0063]

According to a first aspect of the present invention, there is provided a programmable controller for controlling an object to be controlled, comprising a plurality of process I / O means for inputting and outputting to and from the object to be controlled. In addition, when a selection signal is received, a plurality of sets of process I / O groups for selecting process I / O means corresponding to the input address information, and a plurality of process I / O groups are provided corresponding to the respective process I / O groups. At least a group-designated portion of the address information is written in the register means corresponding to the process I / O group having the rewritable register means and the process I / O means to be selected. Processor means for outputting the address information when the O means is selected, all or part of the address information, and register means Comparing the written information, to the process I / O group corresponding to the register means when they match, a programmable controller and a judgment selection means for outputting a selection signal.

According to a second aspect of the present invention, a process I / O address allocated to a plurality of process I / O means for controlling a control target and performing input / output with respect to the control target, In a programmable controller having a processor address different from the processor address used when the processor means for controlling the I / O means specifies the process I / O means, address conversion information for converting the processor address into a process I / O address is stored, and A first memory means used for performing address conversion when designating a process I / O means, and address conversion information for converting a processor address into a process I / O address, and a first memory means. A second memory device configured to reduce the probability of erasure of the held information as compared with the means. Provided and in which, the address conversion information stored in the second memory means is a programmable controller to update the contents of the first memory means at a predetermined cycle.

According to a third aspect of the present invention, in a power supply apparatus for a programmable controller comprising a main power supply means and an auxiliary power supply means, the auxiliary power supply means comprises a plurality of sub-auxiliary power supply means, A power supply device for a programmable controller, comprising: a selection output unit that controls a current value from each of the sub auxiliary power supply units so that a time change of each current value supplied from the sub auxiliary power supply unit follows a predetermined function. It is.

Further, the invention corresponding to claim 4 is as follows:
A power supply device for a programmable controller that obtains a high-voltage input from the outside and converts the high-voltage input to supply power; and a determination unit that determines whether a high-voltage input is supplied. A power supply device for a programmable controller, comprising: an output unit that outputs a determination result to the outside.

On the other hand, a fifth aspect of the present invention provides a charge accumulating unit which receives a high voltage input from the outside, converts the high voltage input to supply power, and accumulates electric charge during the conversion. A power supply device for a programmable controller, comprising: a determination unit for determining an amount of charge stored in a charge storage unit; and an output unit for outputting the determination result to the outside. .

Next, the invention according to claim 6 obtains a high-voltage input from the outside, converts the high-voltage input to supply electric power, and includes a high-temperature portion which becomes high in temperature for conversion. A power supply device for a programmable controller, comprising: a determination unit that determines a temperature of a high-temperature portion; and an output unit that outputs the determination result to the outside.

According to a seventh aspect of the present invention, in a programmable controller for controlling an object to be controlled, signal transmission is connected to processor means for executing various processes, and is divided into a plurality of sections in order from the processor means. A test signal provided for the road and the section, each of which is connected to the section closest to the processor means of the plurality of sections and the section corresponding to itself, and transmitted in the corresponding section. And at least one register means configured to be able to output the stored contents to the processor means through a connection with the nearest section, and when an abnormality occurs in the signal transmission path, the processor means Outputting an inspection signal to the transmission line and detecting an abnormal portion of the transmission line based on information stored in a register unit; A log Lama Bull controller.

Further, according to the present invention, there is provided a restarting device for a programmable controller for controlling a controlled object, comprising: an abnormality detecting means for detecting occurrence of an abnormality; and a programmable controller based on an abnormality detection signal from the abnormality detecting means. System stopping means for stopping the operation of
A restart device for a programmable controller, comprising: a delay unit for delaying an abnormality detection signal; and a system restart unit for initializing the whole or a part of the programmable controller when receiving the abnormality detection signal delayed by the delay unit.

Further, the invention according to claim 9 is as follows:
An invention according to claim 8, which is a restart device for a programmable controller, further comprising control means for prohibiting or permitting operation of the system restart means in response to a predetermined input signal.

According to a tenth aspect of the present invention, a signal transmission path which is connected to a processor for executing various processes and is divided into a plurality of sections in order from the processor is provided. And each of the plurality of sections is connected to the section closest to the processor means and the section corresponding to itself, and stores the test signal transmitted in the corresponding section and determines whether or not the section is the closest section. At least one register means configured to be able to output the stored contents to the processor means via a connection, and when an abnormality occurs in the signal transmission path, the processor means outputs an inspection signal to the transmission path. And a computer that detects an abnormal portion of the transmission path based on the information stored in the register means.

(Operation) Therefore, in the programmable controller according to the first aspect of the present invention, first,
Process I / O to be selected by processor means
At least a part of the address information designated by the group is written into the register means corresponding to the group. After such designation has been made in advance, the processor means operates according to an application program or the like.
The address information is output to select the / O means.

When the address information is output, first, all or a part of the address information is compared with the information written in the register means by the judgment and selection means. A selection signal is output to the process I / O group to be executed.

On the other hand, in the process I / O group receiving the selection signal, the processor I / O means corresponding to the address information is selected.

Therefore, even if there are many process I / O groups, the process I / O
Since the word length of the portion corresponding to the group can be shortened, memory use efficiency and the like can be improved.

Next, in the programmable controller according to the second aspect of the present invention, the first memory means
Address conversion information for converting a processor address into a process I / O address is stored, and when the processor specifies the process I / O, the address conversion is performed with reference to the first memory.

Further, address conversion information for converting a processor address into a process I / O address is also stored in the second memory means.
It is configured such that the probability of loss of the held information is lower than that of the first memory means. For example, it includes an error detection or repair element, or includes a storage element in a broad sense that is excellent in environmental performance.

Then, the contents of the first memory means are updated at a predetermined cycle according to the address conversion information stored in the second memory means.

Therefore, even if the contents of the first memory means are destroyed for some reason, it is quickly restored and the possibility of the controller being downed is increased.

In the power supply apparatus for a programmable controller according to the third aspect of the present invention, an auxiliary power supply means is provided in addition to the main power supply means.

The plurality of sub-auxiliary power supply means included in the auxiliary power supply means are controlled by the selection output means so that the time variation of the current value at the time of supplying the power follows a predetermined function.

Therefore, backup can be performed for a longer period of time, and when a battery is used as one of the sub auxiliary power supply means, the frequency of replacement can be reduced.

Further, in the power supply device for a programmable controller according to the present invention,
A high voltage input is obtained from the outside, and power is supplied by converting the high voltage input.

In such an apparatus, the determination means determines whether or not a high voltage input is supplied. Then, the determination result is output to the outside by the output means.

On the other hand, in the power supply device for a programmable controller according to the present invention, a high-voltage input is obtained from the outside, and the high-voltage input is converted to supply power. In this case, a charge accumulating portion for accumulating electric charges is provided.

In such an apparatus, the determining means
The amount of charge stored in the charge storage unit is determined, and the determination result is output to the outside by the output unit.

Next, in the power supply device for a programmable controller according to the present invention, a high-voltage input is obtained from the outside, the high-voltage input is converted, and power is supplied. For this purpose, a high-temperature portion that becomes high in temperature is provided.

In such an apparatus, the judging means judges the temperature of the high temperature portion, and the output means outputs this judgment result to the outside.

Further, in the programmable controller according to the present invention, the signal transmission path is divided into a plurality of sections in order from the closest to the processor.

The register means provided corresponding to each section is connected to the section closest to the processor means and the section corresponding to itself.

Therefore, when an abnormality occurs in the signal transmission line, the processor outputs the inspection signal to the transmission line, and the inspection signal is transmitted through the connection with the section corresponding to the signal transmission line. It is stored in register means. Then, if the information in the register is read out and inspected through the connection to the section closest to the processor means, it is possible to know whether or not the signal transmission path has failed before reaching the section.

Therefore, for example, if such inspection is performed in order from a section close to the processor means, an abnormal point on the signal transmission path can be specified.

Further, in the restart device for a programmable controller according to the present invention, the occurrence of an abnormality is detected by the abnormality detecting means.

The operation of the programmable controller is stopped by the system stopping means based on the detection signal from the abnormality detecting means.

On the other hand, an abnormality detection signal separate from that provided to the system stop means is delayed by the delay means.
The whole or a part of the programmable controller is initialized by the system restart unit to which the delayed abnormality detection signal is input.

As a result, the system can be restarted even when an abnormality occurs, which has conventionally been forced to stop.

Further, in the restart device for a programmable controller according to the ninth aspect of the present invention, in addition to the same operation as the invention according to the eighth aspect, the system is restarted by the control means in response to a predetermined input signal. The operation of the means is prohibited or permitted.

As a result, when necessary, the automatic restart can be prohibited, and the same effects as those of the invention according to claim 8 can be obtained, while the permanent failure can be coped with.

On the other hand, in the computer according to the tenth aspect, the same operation and effect as those of the seventh aspect can be obtained even in a general computer system.

[0101]

Embodiments of the present invention will be described below.

The basic configuration of the programmable controller to which each embodiment is applied is the same as the conventional programmable controller shown in FIGS. 19 and 20, and the basic operation is also the same. Therefore, in the following description of each embodiment, portions of the programmable controller shown in FIGS. 19 and 20 that are to be solved by the present invention will be described in detail, and description of portions similar to those of FIG. 19 or FIG. 20 will be omitted. I do. In each of FIGS. 1 to 18 illustrating the embodiment, FIG. 19 or FIG.
The same parts as those of 0 are denoted by the same reference numerals and description thereof will be omitted.

(First Embodiment of the Invention) FIG. 1 is a block diagram showing a configuration example of a process I / O selection device portion of a programmable controller according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a resource map of a memory space applied to the apparatus of FIG.

In this programmable controller, an external input / output means 303 is constituted by the master interface 401 and the process I / O group 402.

The process I / O groups 402, as shown in FIG.
2,. . . , A plurality of process I / O groups 402, and each of the groups # 1, # 2,. . Is a unit capable of storing a predetermined number of process I / Os.

The programmable controller can execute a plurality of application programs, and each application program corresponds to each process I / O group 402.

For example, application program # 1 uses process I / O group # 1, and application program # 2 uses process I / O group # 2.

Also, each process I / O group 402
Means that the master interface 401 has its own group 4
02, the process I / O 30 to be accessed with the processor 311 or the like based on the lower address 413 of the address 411 issued by the processor 311.
3 is determined.

The master interface 401 is provided with a comparator 404 and a register 403 corresponding to each of the process I / O groups 402.

That is, the register 403 and the comparator 4
At least one master interface 401 is provided for each process I / O group 402.

The comparator 404 compares a part or all of the address information from the processor 311 with the output information from the register 403, and when both match, outputs a match detection signal 414 to the corresponding specific group 403. Output as a selection signal for process I / O.

The register 403 corresponds to each process I / O group 402 and can be set by the processor 311. The register 403 stores information corresponding to the upper address of the addresses issued by the processor 311.

When the application program is started, the processor 311 stores, in the register 403 corresponding to the application program in the master interface 401, a higher-order address among addresses used when the application program specifies a process I / O. Set the address. Further, the processor 311 sets an invalid value for the register 403 corresponding to the process I / O group 402 not selected by the application program.

The value set in each register 403, that is, the address in the memory space used in the control program shown in FIG. 2 is always set to the same value or a close value independent of the group at the time of initialization. As a result, the process I / O area 405 in the memory space becomes a predetermined area where the process I / O groups 402 overlap as shown in FIG.

Next, the operation of the programmable controller according to the embodiment of the present invention configured as described above will be described.

First, when the processor 411 activates a certain application program, at that time, the upper address 412 corresponds to the register 403 corresponding to the process I / O group 402 storing the process I / O group used by the application program. And the other registers 403 store invalid values.

Next, when the processor 411 executes the application program, the process I / O3 to be accessed is
When 16 addresses 411 are output, the upper address 412 is taken into the master interface 401,
The remaining lower address 413 is taken into the process I / O group.

In the master interface 401, the upper address 412 is input to each comparator 404, and the information stored in each register 403 is input to the corresponding comparator 404.

As a result, in one comparator 404,
When the value from the register 403 matches the contents of the upper address 412, the comparator 404 sends a match detection signal 41 to the corresponding specific process I / O group 402.
4 is output. In this case, in the other sets of the comparator 404 and the register 403, the value from the register 403 does not match the contents of the upper address 412, so that the corresponding process I / O group 402 is not selected.

On the other hand, the process I / O group 402 that has received the match detection signal 414 uses the lower address 413 of the addresses 411 input via the bus 312 to process I / Os to be used by the application program.
/ O316 is specified.

Here, since there are a plurality of types of application programs that can be used by the programmable controller, when another application program is used, the above operation is executed again from the beginning, that is, from the register setting corresponding to the application program.

For example, assume that application program # 1 uses process I / O group # 1 and application program # 2 uses process I / O group # 2.

In this case, when the application program # 1 is started, the process I / O group # 1 is stored in the register 403 of the master interface 401 corresponding to the process I / O group # 1.
The upper address of the / O area 405 is set.

When the application program # 2 is started, the process I / O area 40 is stored in the register 403 of the master interface 401 of the process I / O group # 2.
5 is set.

As described above, although the application programs # 1 and # 2 use different process I / O groups # 1 and # 2, they are called the same process I / O area 405 in the memory space of the processor. The same address range can be specified.

The control program of the controller is as follows:
Essentially, data access to memory and process I / O is extremely large.

FIG. 3 is a diagram showing an example of a command word format of a control language.

For this reason, the format of the control instruction is shown in FIG.
In many cases, an address field is provided as shown in (1), and the longer the address field, the longer the word length of the control instruction.

As shown in FIG. 2, the fact that the process I / O area can be concentrated in a certain narrow range corresponds to shortening the address field. Therefore, if the instruction word length becomes short, many instruction words can be stored in the program memory of a limited size.

As described above, the programmable controller according to the embodiment of the present invention includes the register 403 and the comparator 404 corresponding to each process I / O group 402.
Is provided, and the comparator 404 outputs the match detection signal 404 for the process I / O group, that is, the selection signal. Therefore, even if the number of process I / O groups increases, the control language can be changed. The length can be prevented, and the basic instruction word length of the control language can be reduced. As a result, the efficiency of use of the memory storing the control program can be improved, and further advantages such as an increase in capacity and a reduction in material cost can be obtained.

(Second Embodiment of the Invention) In the programmable controller of this embodiment, an address information conversion means is provided between the processor 311 and the process I / O 316.

This address information conversion means is means for converting the address information 411 output from the processor 311 into address information corresponding to the process I / O 316 in FIG. In addition, the processor 311 or the application I / O 316 specifies a process I / O 316.
As the O selection means, the method shown in the first embodiment may be used, or the method shown in FIG. 21 in the related art may be used.

FIG. 4 is a block diagram showing a configuration example of a process address information conversion unit of a programmable controller according to a second embodiment of the present invention.

The address information conversion means includes a processor 31
1 to provide address translation information to memory 1
And process I / O to process I / O group 402 etc.
And an address conversion memory for outputting an address.

The address conversion memory 422 is a memory element that functions as a converter between a processor address and a process I / O address. The address translation memory 422 is composed of a normal memory element and some data buffers.
The processor address 431 is connected to the address input terminal, the processor data 432 is connected to the data input terminal, and the process I / O address 433 is connected to the data output terminal. In many ordinary memory elements, the data terminal is used for both input and output. In this case, an external buffer element allows the processor data signal line and the process I / O address signal line to be appropriately connected. ing. Although it is essential that the processor data signal line is connected to the data input terminal of the address translation memory, the programmable controller has a configuration in which this signal line may also serve as the data output of the address translation memory 422. .

The high reliability memory 421 includes a ROM, a RAM,
Alternatively, the storage device is a storage device in a broad sense such as a magnetic disk or an optical disk, and includes an error detection and recovery element, or has excellent environmental resistance performance.

The processor 311 has a high reliability memory 421.
, The address conversion information used by the address conversion memory 422 is periodically read out, and the information is written as it is or in the address conversion memory 422 periodically after performing necessary processing.

Next, the operation of the programmable controller according to the embodiment of the present invention configured as described above will be described.

FIG. 5 is a flowchart showing a process related to the address conversion memory setting to which the present embodiment is applied.

As shown in the figure, in this embodiment, the processor address 4 is periodically stored in the address conversion memory 422.
Information for converting the S.31 into the process I / O address 433 is set (ST1).

Therefore, even when the application program is being executed (ST2), the contents of the address translation memory 422 are updated at appropriate timing (ST2).
1).

FIG. 6 shows how the contents of the address translation memory are restored when a failure occurs in the address translation memory.

In the case shown in the figure, the address conversion information read from the high-reliability memory 421 is transmitted at regular intervals at timings T1, T2, T3, T4, T5, T6, T7,. .
In, the address is written and updated in the address conversion memory 422.

Here, it is assumed that the content of the address translation memory 422 is lost due to the occurrence of some trouble between the timings T3 and T4. For this reason, the address conversion is not performed normally, and the address cannot be properly converted until the timing T4. However, at timing T4, backup from the highly reliable memory 421 is performed, and the address conversion returns to a normal state.

As described above, the programmable controller according to the embodiment of the present invention has a high reliability memory 421.
Is provided so that the contents of the address translation memory 422 are periodically backed up. For example, even when the contents of the address translation memory 422 are destroyed due to a disturbance due to disturbance such as noise as shown in FIG. The address conversion memory 422 can be restored at the beginning of the next cycle.

As a result, the influence of the destruction of the address translation memory 422 can be suppressed.
In many cases, it is possible to prevent the programmable controller from going down due to an abnormality in the system, which contributes to an improvement in the operation rate.

(Third Embodiment of the Invention) The programmable controller of this embodiment includes a battery as a secondary battery and a capacitor as its auxiliary power supply.

The electromotive force of the battery is set to be lower than the main power supply voltage. On the other hand, the capacitor is charged from the main power supply, and at the time of discharging, the current flows from the capacitor or the secondary battery, whichever has the higher voltage. A rectifier or switching element is provided to be supplied.

FIG. 7 is a block diagram showing a configuration example of a battery consumption reduction device portion of a programmable controller according to a third embodiment of the present invention.

This device for reducing battery consumption comprises a main power supply 12 for supplying a power supply voltage to all elements in the controller at normal times.
1 and a backup power supply 122 that supplies a power supply voltage only for holding data in the RAM element 313 when the main power supply 121 is turned off.
It is composed of The backup power supply 122 includes
Large capacity capacitor 123 and battery 124 (secondary battery)
Are OR-connected via diodes 125 and 126, respectively, and are grounded.

Further, at the time of normal operation, current flows from the main power supply 121 side to the backup power supply 122 side.
The main power supply 121 and the backup power supply 122 are connected via the switching element 127 and the diode 128 in order to control the current not to flow into the side 21. The switching element 127 is connected to the main power supply 1
The diode 128 is connected between the main power supply 121 and the diode 125 and the capacitor 123.

Each voltage value, that is, main power supply voltage VM
, Backup output voltage VOUT, switching element voltage drop VS, capacitor voltage VC, battery voltage VB,
The diode D1 voltage drop VD1, the diode D2 voltage drop VD2, and the diode D3 voltage drop VD3 are as shown in FIG.

Next, the operation of the programmable controller according to the embodiment of the present invention configured as described above will be described.

FIG. 8 is a voltage / current characteristic diagram of a capacitor and a battery showing the operation of the present apparatus. In addition, FIG.
Shows a voltage characteristic diagram, and FIG. 4B shows a current characteristic diagram.

Hereinafter, referring to FIGS. 7 and 8, the operation of the battery consumption reduction device will be described in terms of periods 13A, 13B, 13C, 13C.
The description will be given in order along the time lapse of D.

** Period 13A Capacitor Charging Period First, when the voltage VM is supplied to the main power supply 121, charging of the capacitor 123 is started. Since the backflow prevention diode D2 is provided, no current flows from the battery 124. Thereafter, when the charging time 13A elapses, the capacitor voltage VC reaches VM-VD3, and the charging is completed.

During this period, the switching element 127 is ON.
Therefore, the voltage VOUT = VM-VS is supplied to the backup power supply 122 from the main power supply 121 side. Since this voltage is higher than the capacitor voltage VC and the battery voltage VB, the capacitor current and the battery current do not flow during this period, and the capacitor and the battery are not consumed.

** Period 13B Normal operation period In this period, as long as the voltage VM is continuously supplied to the main power supply 121, the backup output voltage VOUT and the capacitor voltage V
C and the battery voltage VB remain in the last state of the period 13A. Therefore, neither the capacitor current nor the battery current flows during this period, and the capacitor and the battery are not consumed.

** Period 13C Main power supply 0FF period (power is supplied only to the capacitor) When the main power supply is turned off, the voltage VM becomes “0”, and the voltage is not supplied from the main power supply 121 to the backup power supply 122. Instead, the charged capacitor 123 starts discharging, and VM-VD3-VD2 is supplied to the backup power supply 122. Since VC> VB, the capacitor 123 starts supplying power first, and then VC
The power supply of only the capacitor continues until the voltage becomes VB. The backup current during this period is only the capacitor current. Further, since there are the backflow prevention diodes Dl and D3 and the switching element 127, the capacitor current does not flow into the battery 124 or the main power supply 121 side.

** Period 13D Main power supply OFF period (power supply for both battery and capacitor) When the capacitor voltage VC decreases and becomes equal to the battery voltage VB, the voltage is supplied to the backup power source 122 from both the battery 124 and the capacitor 123. The backup current during this period is represented by the sum of the capacitor current and the battery current. Similarly, backflow prevention diodes D1 to D1
Since there is D3 and the switching element 127, the backup current does not flow into another power supply line.

As described above, the programmable controller according to the embodiment of the present invention includes the backup power supply 1
22, a battery 123, a capacitor 123, a backflow prevention diode D1 to D3, and a switching element 127.
Is provided, the current is discharged from the capacitor 123 first, and then the battery 124 is used. Therefore, the consumption current of the battery 124 can be prevented from flowing at all immediately after the main power is turned off. Further, even after the capacitor voltage drops, the current consumption can be greatly reduced as compared with the conventional case of backing up only the battery. That is, the current consumed in the region A and the region B in FIG. 8 is reduced by this configuration. Also, during charging of the capacitor, it is possible to prevent a current from flowing from the battery 124.

As described above, since the battery consumption is reduced, the number of times of battery replacement at the time of maintenance can be suppressed.

(Fourth Embodiment of the Invention) In the present embodiment, a description will be given of a programmable controller having a voltage detecting device and a display device provided at an intermediate portion of an electric circuit between a terminal block inside a power supply device and a power switch.

FIG. 9 is a block diagram showing a configuration example of a power supply unit of a programmable controller according to a fourth embodiment of the present invention.

In the figure, a primary power supply 442 is connected to a power supply 441 via a main switch 443.
The secondary voltage is supplied to the main body 447 of the programmable controller. That is, the terminal block 4 is connected to the main switch 443.
The secondary voltage is supplied to the programmable controller main body 447 from the terminal block 444 via the power switch 445 and the power circuit 446.

In the vicinity of the terminal block 444, a voltage detector 16B is connected to the input power supply line 16A between the terminal block 444 and the power switch 445, and the detection result of the voltage detector 16B is displayed on the voltage display device 16C. It has become so.

FIG. 10 is a diagram showing a configuration example of the voltage detection / display unit in the present embodiment.

The voltage display device 16 includes an LED, a neon lamp, and the like.
5 ON. Regardless of the OFF state, the display is performed only in response to the power input to the terminal block 444.

Therefore, as the voltage detector 16B,
As shown in FIG. 10, a limiting resistor or the like is used. Although the physical position of the display device 16 is not particularly limited, it is desirable to place the display device 16 near the terminal block 444 or on the same side as the terminal block mounting surface in consideration of visibility.

Next, the operation of the programmable controller according to the embodiment of the present invention configured as described above will be described.

By providing the voltage display device 16C near the terminal block 444 for inputting the primary power supply 442, it is easy to determine whether the primary power supply 442 is input to the terminal block 444.
It is possible to make a reliable determination. The above input power line 1
6A is supplied with power, the limiting resistor 16B
LED 16C lights up because the current flows through
It is possible to easily confirm that the power is supplied from outside the power supply.

As described above, the power supply of the programmable controller according to the embodiment of the present invention is provided with the voltage detector 16B and the display 16C. Although a dedicated measuring device is separately required, this can be eliminated. Furthermore, since the operator can easily check the presence or absence of power input,
At the time of maintenance, etc., it is possible to prevent a dangerous maintenance operation from being performed by forgetting to measure and shut off the power supply input to the terminal block.

(Fifth Embodiment of the Invention) In this embodiment, a programmable controller provided with a voltage detector and a display connected to a high-voltage charging section inside a power supply device will be described.

FIG. 11 is a block diagram showing a configuration example of a power supply unit of a programmable controller according to a fifth embodiment of the present invention. The same parts as those in FIG. I do.

In the power supply device 451 of the programmable controller shown in FIG.
8A, a voltage detector 18B and a display 18C are provided. Note that the illustration of the terminal block is omitted in FIG.

Here, the voltage detector 18B determines the presence or absence of a high voltage in the high voltage charging section 18A. The display 18C
Displays the determination result of the voltage detection unit 18B.

FIG. 12 is a diagram showing a configuration example of the voltage detection / display unit in the present embodiment.

The voltage detector 18B and the display 1 of the present embodiment
8C has the same configuration as the voltage detector 16B and the display 16C in the fourth embodiment. That is, the fourth embodiment is different from the fourth embodiment in that the voltage detector 18B is connected to the high voltage charging unit 18A in the power supply circuit 446. The physical position of the display 18C is not particularly limited, but it is easy to see from the vicinity of the high-voltage charging unit 18A or from the position where the work required to expose the high-voltage charging unit 18A is performed. Considered positions are desirable.

Next, the operation of the programmable controller according to the embodiment of the present invention configured as described above will be described.

When the high voltage charging section 18A exists inside the power supply circuit 446, the display 18C emits light. Thereby, the high voltage charging section 18A inside the power supply circuit can be easily externally provided.
Can be checked. As shown in FIG.
By connecting the LED 18C to the 8A through the limiting resistor 18B, the charging state of the high voltage charging unit 18A is displayed, and the high voltage charging unit 18A can be operated as a discharge circuit.

As described above, since the power supply device of the programmable controller according to the embodiment of the present invention is provided with the voltage detector 18B and the display 18C, it is possible to easily check the charging status of the high voltage circuit inside the power supply. Can be. For this reason, the optimal start time of the maintenance work can be easily determined, and work efficiency and safety are improved.

(Sixth Embodiment of the Invention) In this embodiment, a programmable controller provided with a temperature measuring device and a display connected to a high-temperature portion inside a power supply device will be described.

FIG. 13 is a block diagram showing a configuration example of a power supply unit of a programmable controller according to a sixth embodiment of the present invention. The same parts as those in FIG. I do.

In the power supply device 461 of the programmable controller shown in FIG.
Is connected to a temperature detector 462, and a display 20D is connected to the output of the temperature detector. Note that the illustration of the terminal block is omitted in FIG.

FIG. 14 is a diagram showing a configuration example of the temperature detection / display unit in the present embodiment.

As shown in the figure, the temperature detector 462
Measures the temperature of the high temperature part and outputs a signal to the display when it is higher than a certain set temperature. The temperature detector 462 is connected to the high-temperature section 20.
A thermistor 20B is in contact with A, and a limiting resistor 20C is connected to the thermistor 20B.

The display 20D includes an LED or the like connected to the limiting resistor 20C. When the temperature of the high temperature section 20A is high and there is a signal output from the temperature detector 462, the display 20D turns on and displays the output result. The physical position of the display 20D is not particularly limited, but may be in the vicinity of the high temperature section 20A or in the high temperature section 20A.
It is desirable to have a position that is easy to see from the position where the work necessary for exposing A is performed, for example, a position considering the visibility such as the front panel side.

Next, the operation of the programmable controller according to the embodiment of the present invention configured as described above will be described.

When the high temperature section 20A is left inside the power supply circuit, the display 20D emits light, whereby the temperature inside the power supply circuit can be easily grasped from the outside. The thermistor 20B shown in FIG. 14 is installed so as to be in contact with or close to a heat-generating component and a circuit. When the temperature of the portion is high, a current flows through the limiting resistor 20C, so that the presence or absence of the high-temperature portion 20A can be easily checked from the outside.

As described above, the power supply of the programmable controller according to the embodiment of the present invention is provided with the high temperature detector 462 and the display 20D, so that the temperature condition of the power supply circuit can be easily confirmed. For this reason, the optimal start time of the maintenance work can be easily determined, and work efficiency and safety are improved.

(Seventh Embodiment of the Invention) In this embodiment, a diagnostic register is prepared as hardware, its read port 1 port is connected to a bus (processor bus) immediately below the processor 311 and the remaining port 2 These are connected to the bus (target bus) that performs the diagnosis, and these diagnostic registers are installed in each layer of the bus. By reading and writing the diagnostic registers by software, the part where the bus abnormality occurs The hierarchical bus diagnostic mechanism of the programmable controller that instantaneously estimates the threshold will be described.

FIG. 15 is a block diagram showing a configuration example of a hierarchical bus diagnostic mechanism of a programmable controller according to the seventh embodiment of the present invention.

The hierarchical bus diagnostic mechanism of the programmable controller includes a plurality of diagnostic registers 471 each having one read port, one write port, and one read / write port, and a target bus selection circuit 472.
And a diagnosis address selection circuit 473 and a diagnosis data selection circuit 474.

The bus 312 immediately below the processor 311
Is defined as a processor bus 475, and the target buses Xl. X2 ... Defined as Xn. The diagnosis registers 471 are arranged corresponding to target buses to be diagnosed.

The selection signal output of the target bus selection circuit 472 may be the same for all the diagnosis registers 471, but the selection signal output of the diagnosis address selection circuit 473 and the diagnosis data selection circuit 474 are output to the respective diagnosis registers 471. Are configured to be exclusive.

FIG. 16 is a diagram showing a signal flow in the diagnostic register of the present embodiment.

The diagnostic register 471 has three ports: a port having a read function (port A), a port having a write function (port B), and a port having a read / write function (port C). In each diagnostic register 471, A
The port is connected to the data bus of the processor bus 475, and the B port is the address bus of the corresponding target bus Xn.
Further, the C port is connected to the data bus of the corresponding target bus Xn.

In each diagnostic register 471, values written from the B port and the C port are held. The C port can read and write arbitrary data, and operates as if it were a unit of memory.
The B port can only be written. B port and C
The port operates when a BC port access permission signal is input.

The port A is read-only, and can only read the value written immediately before at the port B or C. At the time of reading, either a B port or a C port can be selected as a port to be read. When the B port read selection signal is valid, the value written to the B port immediately before is read from the A port, and when the C port read selection signal is valid, the value written to the C port immediately before the A port is read. The read value is read.

The target bus selection circuit 472 is used for controlling target bus access. The selection circuit 472 generates a target selection signal based on information from an address bus or the like of the processor bus 475. When the processor 311 specifies a specific address (target selection address), the target selection signal is enabled and the operation of the B port of the diagnostic register is enabled.

The B and C port read selection signals output from the diagnostic address selection circuit 473 and the diagnostic data selection circuit 474 permit the operation of the A port of the diagnostic register 471 as described above.

The diagnostic address selection circuit 473 generates a B port read selection signal based on information from an address bus or the like of the processor bus 475. When the processor 311 attempts to read by designating a specific address (selection address of the diagnostic address), the processor 311 accesses the diagnostic register 471 corresponding to the target bus Xn related to the address. That is, the diagnostic address selection circuit 47
3, an access permission signal is output to the corresponding diagnostic register 471, and the value (address of the target bus Xn) written immediately before to the B port is read.

The diagnostic data selection circuit 474 generates a C port read selection signal based on information from the address bus and the like of the processor bus 475. When the processor 311 attempts to read by specifying a specific address (selection address of the diagnostic data), the processor 311 accesses the diagnostic register 471 corresponding to the target bus Xn, as in the above case. An access permission signal is output from the diagnostic data selection circuit 474 to the corresponding diagnostic register 471, and the value (data of the target bus Xn) written to the C port immediately before is read.

Next, the operation of the programmable controller according to the embodiment of the present invention configured as described above will be described.

When an abnormality has occurred in the bus 312, the processor 311 starts inspecting the abnormal location. The diagnosis of the bus 312 is based on the target buses X1, X2,. . . The processing is performed from a logically short distance between Xn and the processor 311.

First, the microprocessor 311 writes to a preset address (target bus selection address) (diagnosis write cycle). This allows
The target bus selection circuit 472 becomes effective and each diagnostic register 4
The value of the connection destination of the B port and the C port for 71, that is, the value from the target bus Xn is written to the register 471. More specifically, an address on the target bus is written to the B port, and data on the target bus is written to the C port.

Next, the processor 311 reads an address set in advance (a selected address of a diagnostic address). Based on this operation of the processor 311, the B address read select signal of the diagnostic register 471 becomes valid by the diagnostic address selection circuit 473. This allows
The value of the port A of the diagnostic register 471 is taken into the processor 311 from the port A via the processor bus 475. The data at this time is the value just written to the B port, that is, the address at the time of writing the target bus (diagnosis address reading cycle).

Next, the processor 311 reads a preset address (diagnosis data selection address). Based on this operation of the processor 311, the diagnostic data selection circuit 474 makes the C port read selection signal of the diagnostic register 471 valid. Thereby, the value of the A port of the diagnostic register 471 is taken into the processor 311 from the A port via the processor bus 475. The data at this time is the value written to the C port immediately before, that is, the data at the time of writing the target bus (diagnosis data read cycle).

With respect to the result read by the processor 311, the address written in the diagnostic write cycle at normal time matches the data obtained in the diagnostic address read cycle. If these data do not match, it is determined that there is an error in the address bus in the target bus. Also,
By changing the combination of write address values in the diagnostic write cycle, it is possible to check in more detail which address line is abnormal.

Similarly, in a normal state, data written in the diagnostic write cycle matches data obtained in the diagnostic data read cycle. If the data do not match, it is determined that there is an abnormality in the data bus in the target bus. By changing the combination of write data values in the diagnostic write cycle, it is possible to examine in detail which data line is abnormal.

When it is determined that the target bus Xn is not abnormal, the diagnosis is advanced for the bus Xn + 1 farther from the processor 311 and the state of the bus 312 is sequentially inspected.

As described above, the programmable controller according to the embodiment of the present invention logically divides the bus 312 into target bus units, provides the diagnostic register 471 corresponding to the target bus Xn, and supplies the diagnostic register 471 to the bus 312. Inspection signals can be checked from the diagnostic register, so it is easy to detect abnormalities such as short-circuiting / opening of signal lines in hierarchical buses and failures in bus buffers between hierarchical buses, and to accurately and quickly identify the location of the failure. Can be identified.

Although the present embodiment has been described for the case where a bus abnormality of the control controller is detected, the present invention is not limited to the case where the present invention is applied to such a programmable controller. That is, it can be adapted to various computer devices having a hierarchical bus and a microprocessor. Also, from the principle of operation, the number of target buses in this embodiment can be adapted to any number, and the data length and address length of the target bus are different from the data length and address length of the processor bus. Can also be adapted.

(Eighth Embodiment of the Invention) In the programmable controller of this embodiment, the output of the WDT circuit as an abnormality detection circuit is connected to the system stop means and the system restart means to enable automatic restart. Things.

FIG. 17 is a block diagram showing a configuration example of an automatic restart circuit portion of a programmable controller according to an eighth embodiment of the present invention.

In this automatic restart circuit, the WDT circuit 231 (watchdog timer 318) which is a part of the abnormality occurrence detecting means 307 has a delay circuit 2 as a delay element.
34 and an NMI circuit 232 as a system stop unit are connected in parallel, and a reset circuit 235 as a system restart unit is connected to the delay circuit 234. Further, the reset circuit 235 and the NMI circuit 232
3 (microprocessor 311).

The WDT circuit 231 and FIGS.
WDT circuit 251 (watch dock timer 31
8), and notifies the delay circuit 234 and the NMI circuit 232 of the abnormality detection.

The NMI circuit 232 is a circuit for performing a non-maskable interrupt, and issues an NMI signal 2311 to the CPU 233 upon receiving a WDT error signal 2311 from the WDT circuit 231. The WDT circuit 231
Are configured to operate immediately after the abnormality is detected, and the signal 2311 from the WDT circuit 231 does not include a delay element.

The delay circuit 234 is a timer means,
During the period from the time of abnormality detection to the time of system shutdown, the CPU
233, the signal from the WDT circuit 231 is delayed, and then the delayed WDT error signal 23
13 is input to the reset circuit 235.

When receiving the delayed WDT error signal 2313 from the delay circuit 234, the reset circuit 235 outputs a reset signal 2314 to the CPU 233.

Next, the operation of the programmable controller according to the embodiment of the present invention configured as described above will be described.

First, when an error is detected by the WDT circuit 231, a WDT error signal 2313 is issued, and N
It is input to the MI circuit 232 and the delay circuit 234. As a result, the NMI circuit 232 issues the NMI signal 2312 to the CPU 233, and the CPU 233 performs the NMI process, the CPU becomes inactive, and the operation ends thereafter.

On the other hand, WDT input to delay circuit 234
The error signal 2313 is input to the reset circuit 235 as a delayed WDT error signal 2313 after a predetermined time. At this point, the NMI processing in the CPU 233 has ended, and the CPU operation has stopped. The reset circuit 235 receiving the signal 2313 generates a reset signal 231
4 is issued, and the CPU 233 receiving the
Restart is performed.

[0225] The above-mentioned WDT is a powerful abnormality judging means, but cannot always take in information which can completely repair the abnormality when the abnormality is detected. For this reason, the WDT has been used only as a means for stopping the system.

However, in a system having a relatively slow response, it is often practical even if the system is restarted by initialization.

Therefore, when the cause of the abnormality detected by the WDT is transient noise or the like, the cause of the failure can be removed by system reset using the apparatus of the present embodiment.

As described above, in the programmable controller according to the embodiment of the present invention, the signal from the WDT circuit 231 is input to the reset circuit 235 after being delayed by the delay circuit 234. By doing so, restarting can be performed, and what has been recovered from the abnormality can be automatically executed. That is, automatic restart becomes possible.

(Ninth Embodiment of the Invention) In the programmable controller according to the ninth embodiment, in the eighth embodiment, the signal of the signal is provided in the middle of the signal path connected from the WDT circuit to the reset circuit via the delay circuit. A gate means capable of controlling passage / blocking is provided.

FIG. 18 is a block diagram showing a configuration example of an automatic restart circuit of a programmable controller according to the ninth embodiment of the present invention.

In this automatic restart circuit, a WDT-linked reset control circuit 246 as a gate means to which a WDT-linked reset control signal 2416 is input is provided between the delay circuit 234 and the reset circuit 235.
The configuration is the same as that of the first embodiment.

The WDT-linked reset control circuit 246 outputs the W
By turning on / off the DT linked reset control signal 2416, the delayed WDT error signal 2 from the delay circuit 234 is output.
313 is transmitted to the reset circuit 235. That is, the signal 2313 from the delay circuit 234 is cut off when the WDT linked reset control signal 2416 is turned on, and the signal from the delay circuit 234 is cut when the WDT linked reset control signal 2416 is not reset due to the turning off of the WDT linked reset control signal 2416. 2313 is output to the reset circuit 235 as a controlled WDT error signal 2415.

The programmable controller according to the embodiment of the present invention configured as described above has the same configuration as that of the eighth embodiment when the WDT-linked reset is not used due to the turning off of the WDT-linked reset control signal 2416. Works. On the other hand, when the WDT-linked reset is used, the signal 2313 from the delay circuit 234 is cut, and the restart of the CPU 233 by the reset circuit 235 is not performed.

As described above, the programmable controller according to the embodiment of the present invention has the same configuration as that of the eighth embodiment, and also has the WDT-linked reset control circuit 246 provided with the CPU 233 by the reset circuit 235.
To enable / disable restart function of WDT
The use or non-use of the interlock reset can be selected, and even in the event of a permanent failure that requires the system to be stopped, the loop from stop to restart can be broken by function selection by the signal 2416.

The present invention is not limited to the above embodiments, but can be variously modified without departing from the gist thereof.

The method described in the embodiment can be executed by a computer as a program such as a magnetic disk (floppy disk, hard disk, etc.), an optical disk (CD-ROM, DVD, etc.), or a storage medium such as a semiconductor memory. And can also be transmitted and distributed via a communication medium. A computer that implements the present apparatus reads a program recorded on a storage medium, and executes the above-described processing by controlling the operation of the program.

[0237]

As described above, the present invention has the following effects.

According to the first aspect of the present invention, since the basic instruction word length of the control language can be reduced, it is possible to provide a programmable controller capable of improving the use efficiency of the memory storing the control program. . As a result, the capacity of the system can be easily increased, and advantages such as reduced material costs can be obtained.

According to the second aspect of the present invention, even if the contents of the address translation memory are destroyed, the address is quickly restored, and in many cases, the programmable controller can be prevented from being down due to an abnormal process I / O. Can be provided. This also contributes to improving the operation rate of the system.

According to the third aspect of the present invention, the battery consumption current of the auxiliary power supply can be reduced. Therefore, it is possible to provide a power supply device of a programmable controller capable of performing backup for a longer time or backup of a larger capacity. Further, the frequency of battery replacement is reduced, which contributes to the reduction of hazardous waste.

According to the fourth aspect of the present invention, it is possible to easily confirm whether or not the primary side of the power supply terminal block is at a high voltage without using another measuring device. It is possible to provide a power supply device for a programmable controller capable of improving the power supply. Thereby, danger to the human body can be reduced and the efficiency of maintenance work can be improved.

According to the fifth aspect of the present invention, it is possible to provide a power supply device for a programmable controller which can reduce a risk of an electric shock accident caused by touching a high voltage charging section inside a power supply device during maintenance work. As a result, the extra discharge time, which was conventionally taken for safety, can be minimized, and the work efficiency is improved.

According to the sixth aspect of the present invention, it is possible to provide a power supply device for a programmable controller which can reduce the risk of burns caused by touching a high-temperature portion inside the power supply device during maintenance work. This allows
The extra heat radiation time taken for safety can be minimized, and work efficiency is improved.

According to the seventh aspect of the present invention, by arranging the diagnostic register in the hierarchical bus of the existing controller, a short circuit / opening of a signal line in the hierarchical bus, and an abnormality due to a failure of a bus buffer between the hierarchical buses or the like. Can be provided.

According to the eighth aspect of the present invention, it is possible to provide a restart device for a programmable controller which can restart the system even when an abnormality occurs, which had to stop the system in the past.

According to the ninth aspect of the present invention, the automatic restart function of the eighth aspect can be prohibited when necessary. For example, when a permanent failure occurs, the system is stopped by cutting the loop from stop to restart. The restart device of the programmable controller which can be provided.

According to the tenth aspect of the present invention, by arranging the diagnostic register in the bus, it is possible to easily detect an abnormality due to a short circuit / opening of a signal line in the bus, a failure of a bus buffer between hierarchical buses, and the like. A calculator can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a process I / O selection device portion of a programmable controller according to a first embodiment of the present invention.

FIG. 2 is an exemplary view showing a resource map of a memory space of the programmable controller according to the embodiment;

FIG. 3 is a diagram showing an example of a command language format of a control language.

FIG. 4 is a block diagram showing a configuration example of a process address information conversion unit of a programmable controller according to a second embodiment of the present invention.

FIG. 5 is a flowchart showing processing relating to address translation memory settings to which the embodiment is applied.

FIG. 6 is a diagram showing how the contents of the address translation memory are restored when a failure occurs in the address translation memory.

FIG. 7 is a block diagram showing a configuration example of a battery consumption reduction device portion of a programmable controller according to a third embodiment of the present invention.

FIG. 8 is a voltage / current characteristic diagram of a capacitor and a battery showing the operation of the device of the embodiment.

FIG. 9 is a block diagram showing a configuration example of a power supply unit of a programmable controller according to a fourth embodiment of the present invention.

FIG. 10 is an exemplary view showing a configuration example of a voltage detection / display unit in the embodiment.

FIG. 11 is a block diagram showing a configuration example of a power supply unit of a programmable controller according to a fifth embodiment of the present invention.

FIG. 12 is a view showing a configuration example of a voltage detection / display unit in the embodiment.

FIG. 13 is a block diagram showing a configuration example of a power supply unit of a programmable controller according to a sixth embodiment of the present invention.

FIG. 14 is a diagram showing a configuration example of a temperature detection / display unit in the embodiment.

FIG. 15 is a block diagram showing a configuration example of a hierarchical bus diagnostic mechanism of a programmable controller according to a seventh embodiment of the present invention.

FIG. 16 is a view showing a signal flow in the diagnostic register of the embodiment.

FIG. 17 is a block diagram showing a configuration example of an automatic restart circuit part of a programmable controller according to an eighth embodiment of the present invention.

FIG. 18 is a block diagram showing a configuration example of an automatic restart circuit of a programmable controller according to a ninth embodiment of the present invention.

FIG. 19 is a functional conceptual configuration diagram of a general programmable controller.

FIG. 20 is a diagram showing a specific hardware configuration example corresponding to the programmable controller shown in FIG. 19;

FIG. 21 is a diagram showing a conventional process I / O selection device.

FIG. 22 is a diagram showing a conventional resource map.

FIG. 23 is a diagram showing a conventional address translation memory setting method.

FIG. 24 is a diagram showing a configuration example of a conventional power supply device.

FIG. 25 is a diagram showing a configuration example of a portion related to stopping an abnormality detection system in a conventional programmable controller.

[Explanation of symbols]

 121 ... Main power supply 122 ... Backup power supply 123 ... Capacitor 124 ... Battery 125 ... Diode D2 126 ... Diode D1 127 ... Switching element 128 ... Diode D3 13A ... Capacitor charging period 13B ... Normal operation period 13C ... Capacitor discharging period 13D ... Capacitor battery Discharge period 16A Input power line 16B Voltage detector 16C Display 18A Input power line 18B Voltage detector 18C Display 20A Power supply 20B Thermistor 20C Limiting resistor 20D Display 231 WDT circuit 233 NMI circuit 233 CPU 234 Delay circuit 235 Reset circuit 2311 WDT error signal 2312 NMI signal 2313 Delayed WDT error signal 2314 Reset signal 246 WDT linked reset system Control circuit 2416 WDT linked reset control signal 311 Microprocessor 312 Bus 401 Master interface 402 Process I / O group 403 Register 404 Comparator 405 Process I / O area 421 Highly reliable memory 422 Address conversion Memory 441, 451, 461 Power supply device 444 Terminal block 445 Power switch 462 Power supply circuit 462 High temperature detector 471 Diagnostic register 472 Target bus selection circuit 473 Diagnostic address selection circuit 474 Diagnostic data selection circuit 475 Processor bus

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihiro Yamamoto 1 Toshiba-cho, Fuchu-shi, Tokyo Toshiba Corporation Fuchu Plant (72) Inventor Shinji Kuno 1-Toshiba-cho, Fuchu-shi Tokyo

Claims (10)

[Claims] 1. A programmable controller for controlling an object to be controlled, comprising: a plurality of process I / O means for inputting / outputting data to / from the object to be controlled; and when receiving a selection signal, a process corresponding to input address information. Plural sets of process I / O groups for selecting I / O means, rewritable register means provided for each of the process I / O groups, and the process I / O means to be selected Processor means for writing at least a group-designated portion of the address information into register means corresponding to the process I / O group having: and outputting the address information when a process I / O means is selected; All or part of the information is compared with the information written in the register means, and both are compared. Programmable controller for relative process I / O group corresponding to the register means, characterized in that a judgment selection means for outputting the selection signal in the case of. 2. Process I / O addresses allocated to a plurality of process I / O means for controlling a control target and performing input / output with respect to the control target, and processor means for controlling the process I / O means In a programmable controller having a processor address different from that used when designating the process I / O means, address conversion information for converting the processor address into the process I / O address is stored, and the processor means First memory means used to perform address conversion when designating / O means, and address conversion information for converting the processor address into the process I / O address, and the first memory A second method configured to reduce the probability of losing the held information as compared with the means. Programmable controller, characterized in that a re unit, updates the contents of the first memory means at a predetermined cycle by the said address translation information stored in the second memory means. 3. A power supply device for a programmable controller comprising a main power supply means and an auxiliary power supply means, wherein the auxiliary power supply means is supplied from a plurality of sub auxiliary power supply means and from each of the sub auxiliary power supply means. And a selection output means for controlling a current value from each of the sub-auxiliary power supply means so that the time change of each current value follows a predetermined function. 4. A power supply device for a programmable controller, which obtains a high-voltage input from outside and converts the high-voltage input to supply power, determines whether the high-voltage input is supplied. A power supply device for a programmable controller, comprising: a determination unit that performs the determination; and an output unit that outputs the determination result to the outside. 5. A power supply device for a programmable controller having a high voltage input from the outside, converting the high voltage input to supply power, and having a charge storage unit for storing charges during the conversion. 3. The power supply device for a programmable controller according to claim 1, further comprising: a determination unit configured to determine an amount of charge stored in the charge storage unit; and an output unit configured to output the determination result to the outside. 6. A power supply device for a programmable controller having a high-voltage input from the outside, converting the high-voltage input to supply power, and having a high-temperature portion that becomes high temperature for the conversion. A power supply device for a programmable controller, comprising: determination means for determining the temperature of the high-temperature portion; and output means for outputting the determination result to the outside. 7. A programmable controller for controlling a control target, wherein the programmable controller is connected to processor means for executing various processes.
And a signal transmission path that is sequentially divided into a plurality of sections from the processor means, and a signal transmission path provided corresponding to the section, and each of the plurality of sections corresponds to a section closest to the processor means and a section corresponding to the section. And at least one register configured to store a test signal transmitted in the corresponding section and output the stored content to the processor means through a connection with the closest section. Means for outputting an inspection signal to the transmission line when an abnormality occurs in the signal transmission line, and detecting an abnormality in the transmission line based on information stored in the register unit. Programmable controller characterized by detecting locations. 8. A restart device for a programmable controller for controlling an object to be controlled, comprising: an abnormality detecting means for detecting occurrence of an abnormality; and a system stop for stopping an operation of the programmable controller based on an abnormality detection signal from the abnormality detecting means. Means, delay means for delaying the abnormality detection signal, and system restart means for initializing the whole or a part of the programmable controller when receiving the abnormality detection signal delayed by the delay means. A restart device for a programmable controller. 9. The restart device for a programmable controller according to claim 8, further comprising control means for prohibiting or permitting operation of said system restart means in response to a predetermined input signal. 10. A signal transmission path which is connected to processor means for executing various processes and is divided into a plurality of sections in order from said processor means. Are connected to the section closest to the processor means and the section corresponding to the section, and store the test signal transmitted to the corresponding section, and connect through the connection to the closest section. At least one register means configured to be able to output the stored contents to a processor means, and when an abnormality occurs in the signal transmission path, the processor means outputs the inspection signal to the transmission path. A computer that detects an abnormal portion of the transmission path based on information stored in the register means.