JPH10247954A - Clock extract circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a clock extract circuit employing a digital PLL circuit to extract a clock signal stably and quickly in an interrupting information transmission system. SOLUTION: The circuit is provided with a synchronization pattern detection circuit 2 that receives an input digital signal 501, a reception level signal 502, and an extracted clock signal 301, a Q value control circuit 4 connecting to the synchronization pattern detection circuit 2 and a digital PLL circuit 3, and an IF conversion circuit 1 that provides the input digital signal 501 and the reception level signal 502. When the reception level signal 502 is at a low level (a level of an input high frequency signal 1701 is low), the operation of the digital PLL circuit 3 and the synchronization pattern detection circuit 2 is stopped. When the reception level signal 502 is at a high level (a level of the input high frequency signal 1701 is high), the synchronization pattern detection circuit 2 receives the input digital signal 501, detects a specific synchronization pattern to provide an output of synchronization information 201. The Q value control circuit 4 controls the Q value of the digital PLL circuit 3 to be low till the synchronization information 201 is received and controls the Q value of the digital PLL circuit 3 to be high after the synchronization information 201 is received.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock extraction circuit, and more particularly to a clock extraction circuit having a digital PLL circuit configuration for extracting a clock signal synchronized with an input digital signal.

[0002]

2. Description of the Related Art Conventionally, as a clock extracting circuit of this type, there is a circuit disclosed in, for example, Japanese Patent Application Laid-Open No. 8-288971, and this configuration is shown in FIG. 4, a limiter amplifier 8 which receives an input signal through an antenna 16, a first IF unit 6, and a second IF unit 7 outputs a signal obtained by converting a received high-frequency signal into digital data to a digital demodulation circuit 9 and a symbol clock recovery circuit 10. . Also, the limiter amplifier 8 has an RS proportional to the strength of the received high-frequency signal.
An SI (Received Signal Strength Indicator) signal is output to the system controller 14.

The digital demodulation circuit 9 includes a limiter amplifier 8
Demodulates the signal output from the
The demodulated data is sampled at the timing of the symbol clock output from, and is output to the channel codec 11. The channel codec 11 measures the error rate of the input demodulated data and outputs it to the system controller 14. In the system controller 14, R input from the limiter amplifier 8
The characteristics and the like of the loop filter of the digital PLL in the symbol clock recovery circuit 10 are switched based on the SSI signal, the error rate input from the channel codec 11, and the like.

In such a clock extraction circuit, RSS
When the I signal is larger than a certain value (high signal strength) and the error rate of demodulated data is larger than a certain value (many errors), a loop filter having a large time constant is used to suppress the jitter of the symbol clock. select. In other cases, a loop filter having a small time constant is selected to establish high-speed timing synchronization.

[0005]

In the above-mentioned conventional clock extracting circuit for extracting a clock by making the time constant of the loop filter of the digital PLL circuit variable, the time constant of the loop filter is changed based on the measurement result of the error rate. Therefore, the loop filter cannot be changed while the error rate is being measured. Therefore, when the above-described circuit is applied to a system for intermittently transmitting information such as a TDMA (time division multiple access) system, the error rate is being measured immediately after the start of information reception. The loop filter has a small time constant and has a drawback that stable timing synchronization cannot be ensured.

An object of the present invention is to solve the above-mentioned disadvantages,
It is an object of the present invention to provide a clock extracting circuit capable of quickly and stably extracting a clock signal even in a communication system in which information is intermittently transmitted like a TDMA system.

[0007]

The present invention has the following means in order to achieve the above object. That is, the clock extraction circuit according to the present invention is a clock extraction circuit having a digital PLL circuit configuration for extracting a clock signal synchronized with an input digital signal obtained by IF-converting a digital input high frequency signal, wherein Synchronization pattern detection means for detecting a pattern and outputting synchronization information; Q value control means for performing Q value control of the digital PLL circuit based on the synchronization information and a reception level signal indicating a reception intensity of the input high-frequency signal; It has the structure provided with.

Further, in the clock extraction circuit according to the present invention, the synchronization pattern detecting means detects the synchronization pattern based on the detection of the synchronization pattern having a fixed length and a fixed pattern transmitted prior to transmission information included in the input digital signal. It has a configuration that generates a pulse as synchronization information.

Further, in the clock extraction circuit according to the present invention, the synchronization pattern detecting means detects the synchronization pattern only when the reception level of the input high-frequency signal exceeds a threshold for determining spatial noise in advance. A configuration is provided in which clock extraction processing is performed, and when the threshold value is not exceeded, the operation together with the digital PLL circuit is stopped.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a conventional clock extracting circuit having a digital PLL circuit configuration for extracting a clock signal synchronized with an input digital signal, a time constant of a loop filter is changed based on a measurement result of an error rate. Clock jitter is suppressed. For this reason, the time constant of the loop filter cannot be changed during the error rate measurement. Therefore, when the present invention is applied to a system that transmits information intermittently, such as a TDMA system, the error rate cannot be changed immediately after information reception is started. During the measurement, the loop filter has a small time constant, and there is a disadvantage that stable timing synchronization cannot be ensured.

According to the present invention, a clock extracting circuit which avoids the above-mentioned disadvantages is realized as follows. That is, in the present invention, when the reception level of an input signal is lower than a predetermined value set in advance as a spatial noise determination threshold value, the input digital signal is determined as spatial noise, and a synchronous pattern detection and a digital PLL circuit are performed. Are stopped to stop the output of the extracted clock signal. By such a measure, it is possible to avoid occurrence of erroneous synchronization when trying to detect a synchronization pattern from spatial noise. When the input reception level signal becomes higher than a predetermined value set as a spatial noise determination threshold value, the input digital signal is determined as correct transmission information provided from the transmission side, and clock extraction processing is performed as follows. Do.

In the clock extracting process according to the present invention, the Q value of the digital PLL circuit is reduced to reduce the synchronization pull-in time before detecting a synchronization pattern composed of a fixed length fixed pattern from the input digital signal. If a synchronization pattern is detected from the input digital signal, the digital PL
The Q value of the L circuit is increased to improve the synchronization holding ability and perform stable clock extraction. By such an extraction operation, no spatial noise is input at the stage of the synchronization pattern detection processing,
Therefore, occurrence of erroneous synchronization can be avoided, the length of the synchronization pattern can be reduced, and synchronization can be established in a short time. In this manner, the embodiment of the present invention is such that even when intermittent information is received as in the TDMA system, clock extraction can be performed in a short time after the start of information reception.

[0013]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. The embodiment of FIG. 1 includes an IF conversion circuit 1 that performs IF conversion on an input high-frequency signal to output an input digital signal having a desired intermediate frequency and outputs a reception level signal indicating the reception level of the input high-frequency signal. , A synchronization pattern detection circuit 2 for detecting a synchronization pattern from an input digital signal output from the IF conversion circuit 1 and transmitting synchronization information indicating detection timing, a digital PLL circuit 3, and controlling a Q value of the digital PLL circuit 3. Q value control circuit 4
And a waveform shaping circuit 5 for shaping the waveform of the input digital signal output from the IF conversion circuit 1. An antenna 17 is also shown in FIG. In these configurations, the IF conversion circuit 1 and the synchronization pattern detection circuit 2 constitute a synchronization pattern detection means, and the digital PLL circuit 3 and the Q value control circuit 4
Constitute the Q value control means.

Next, the operation of this embodiment will be described.
In the present embodiment, a receiving system operated by the TDMA method is taken as an example, and an input high-frequency signal 1701 input through the antenna 17 is input.
Is IF-converted to a predetermined frequency by the IF conversion circuit 1 and sent out as an input digital signal 501 to the synchronization pattern detection circuit 2, the digital PLL circuit 3 and the waveform shaping circuit 5, and displays the reception level of the input high-frequency signal 1701. The reception level signal 502 is sent to the synchronization pattern detection circuit 2 and the digital PLL circuit 3. The basic operation is that the input digital signal 501 is input to the digital PLL circuit 3 to extract a clock component, and the input digital signal is waveform-shaped by the waveform shaping circuit 5 based on the extracted clock signal 301 and output. .

In this embodiment, the following functions are added to automatically control the Q value expressing the selectivity of the digital PLL circuit 3 and the synchronization processing of the digital PLL circuit 3. That is, the reception level signal 502 indicating the reception level of the input high-frequency signal 1701 is input to the digital PLL circuit 3 and the synchronization pattern detection circuit 2. Receive level signal
If 502 is lower than a fixed value as a spatial noise determination threshold value, it is determined that the input digital signal 501 is spatial noise, and the digital PLL circuit 3 and the synchronous pattern detection are controlled under the control of a system CPU (not shown). Circuit 2
Thus, even when the input digital signal 501 obtained by demodulating the spatial noise includes the same pattern as the synchronization pattern, it is possible to avoid erroneous synchronization detection.

On the other hand, in the input digital signal 501, a synchronization pattern is detected by the synchronization pattern detection circuit 2, and synchronization information 201 synchronized with the detected timing is generated and transmitted. The synchronization information 201 is input to the Q value control circuit 4, and a Q value control signal 401 for controlling the level of the Q value of the digital PLL circuit 3 is output. That is, before the synchronization information 201 is input to the Q value control circuit 4, the Q value of the digital PLL circuit 3 is set low to shorten the synchronization pull-in time. Further, when the synchronization information 201 is input to the Q value control circuit 4, the Q value of the digital PLL circuit 3 is set high to improve the synchronization holding ability.

FIG. 2 is a timing chart showing an example of the operation of the embodiment of FIG. Immediately after the reception of the input digital signal 501, the input digital signal 501 is represented as a time series preceded by spatial noise a and followed by a synchronization pattern b and transmission information c as shown in FIG. , The reception level signal 502 is expressed as shown in FIG. That is, before the input high-frequency signal 1701 is input, the spatial noise a is input as the input digital signal 501, and the reception level signal 502 is indicated as a low value d as shown in FIG. Thereafter, when the high frequency signal is received, the synchronization pattern b and the transmission information c are input to the input digital signal 501. Further, the reception level signal 502 becomes the high value e, and the clock extraction processing is started. At this point, the Q value of the digital PLL circuit 3 has been set to a low value f as shown in FIG. 2D, and a quick clock extraction process is performed. When the synchronization pattern b is input to the input digital signal 501, the synchronization pattern detection circuit 2 outputs synchronization information 201 indicated by a pulse p as shown in FIG.

In the Q value control circuit 4, when the synchronization information 201 provided from the synchronization pattern detection circuit 2 is input,
As shown in (d), the Q value of the digital PLL circuit 3 is set to a high value from a low value f to a high value g. As a result, it is possible to perform a stable clock extraction process that is not easily affected by the jitter of the input digital signal 501 and the bias of the pattern. FIG. 2E shows the digital PLL circuit 3 described above.
This indicates the Q value setting status of the input digital signal.
When 501 is spatial noise a, synchronization processing h is set, when synchronization pattern b is set, Q value is low i, and in transmission information c, Q value is high j.

For controlling the Q value of the digital PLL circuit 3, a well-known technique as disclosed in, for example, Japanese Patent Application Laid-Open No. 3-97318 can be used.
This will be described with reference to FIG. FIG. 3 is a block diagram showing an example of the digital PLL circuit 3. Generally, a one-chip general-purpose I / O
A commercially available circuit can be used as C. For example, “CD74HC297E” (manufactured by Harris: HARRI)
S company) makes it possible to set the Q value from the outside of the IC, which is shown as a Q value control signal 401 in FIG. 3 and which is output from the Q value control circuit 4 in FIG. It is.

The phase comparison circuit 31 shown in FIG. 3 compares the phase of the input digital signal 501 with the phase of the extracted clock signal 301, finds the difference, and outputs it as a phase error signal 311. U /
The D (up / down) counter 32 counts up / down the clock provided from the reference clock generation circuit 34. The up / down switching is performed by a phase error signal 311 provided from the phase comparison circuit 31. Done. Each time the value of the U / D counter 32 exceeds or falls below a certain range, a control signal (U) 321 is sent to the frequency dividing circuit 33.
Or (D) 322 is output. The Q value control signal 401 is
The U / D counter 32 controls a certain range.

The frequency dividing circuit 33 divides the frequency of the clock supplied from the reference clock generating circuit 34 and generates an extracted clock signal 301 having the same frequency as the input digital signal.
During this frequency division operation, the phase of the extracted clock signal 301 to be output is changed by the control signals (U) 321 and (D) 322 input from the U / D counter 32, and thus the pulse of the extracted clock is changed according to the control signal. Operate to make the number ± 1.

Thus, the digital PLL circuit 3
When the Q-value control signal 401 input to the counter is low, the fixed range in the U / D counter 32 is reduced, and the control signal to the frequency dividing circuit 33 is frequently generated. And the synchronization of the digital PLL circuit 3 is facilitated. Further, when the Q-value control signal 401 is high, the fixed range in the U / D counter 32 is increased to suppress the generation of the control signal, thereby making it difficult for the phase change of the extracted clock signal 301 to occur. The synchronization holding capability of the digital PLL circuit 3 is improved. Thus,
Even in a system that intermittently transmits information, a clock extraction circuit that quickly and stably extracts a clock signal can be realized.

[0023]

As described above, according to the present invention, in a clock extraction circuit for extracting a clock signal synchronized with an input digital signal, a reception level signal proportional to the reception intensity of the input high-frequency signal and a synchronization pattern included in the reception signal. By controlling the Q value of the digital PLL circuit based on the above, there is an effect that a clock extraction circuit that can quickly and stably extract a clock signal can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing an example of the operation of the embodiment of FIG.

FIG. 3 is a block diagram illustrating a configuration example of a digital PLL circuit 3 in FIG. 1;

FIG. 4 is a block diagram showing a configuration of a conventional clock extraction circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 IF conversion circuit 2 Synchronization pattern detection circuit 3 Digital PLL circuit 4 Q value control circuit 5 Waveform shaping circuit 31 Phase comparison circuit 32 U / D counter 33 Divider circuit 34 Reference clock generation circuit

Claims (3)

[Claims] 1. An input high-frequency signal in a digital format is IF
A clock extraction circuit having a digital PLL circuit configuration for extracting a clock signal synchronized with the converted input digital signal, comprising: a synchronization pattern detection means for detecting a synchronization pattern included in the input digital signal and outputting synchronization information; A clock extraction circuit comprising: a Q value control unit that controls a Q value of the digital PLL circuit based on information and a reception level signal indicating a reception intensity of the input high-frequency signal. 2. The synchronization pattern detection means generates a pulse as the synchronization information based on detection of a synchronization pattern of a fixed length fixed pattern transmitted prior to transmission information included in the input digital signal. 2. The clock extracting circuit according to claim 1, wherein the clock extracting circuit has a configuration. 3. The synchronization pattern detection means detects the synchronization pattern and performs a clock extraction process only when the reception level of the input high-frequency signal exceeds a threshold value for determining spatial noise in advance. 3. The clock extracting circuit according to claim 1, wherein the clock extracting circuit is configured to stop the operation together with the digital PLL circuit when the threshold value is not exceeded.