JPH10247074A - Gas discharge display method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an equipment cost without the needs for IC dedicated to gradation display by displaying gradations by dividing a raster period into sub-rasters with different lengths from each other and designating in which sub-raster period in the basic unit to emit light. SOLUTION: A basic unit for gradation display is composed of two, 1st and 2nd frames, and one raster period in each frame is divided into three sub- rasters 31-33, 34-36. In such a case, each sub-raster is weighted with a different weight as, in a 1st frame, a 1st sub-raster 31 is weighted with 9/16H, a 2nd sub-raster 32 with 4/16H, and a 3rd sub-raster 33 with 3/16H, and in a 2nd frame, a 1st sub-raster 34 is weighted with 5/8H, a 2nd sub-raster 35 with 2/8H, and a 3rd sub-raster with 1/8H, and gradations are displayed by determining a lighting time according to a combination of selected sub-rasters in a same area during two frame periods.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat and thin gas discharge display method, such as a plasma display, used for a display portion of a laptop computer, a ticket vending machine at a station, or the like.

[0002]

2. Description of the Related Art FIG. 5 is a perspective view showing a display panel of an apparatus for implementing a conventional gas discharge display method, and FIG. 6 is a cross-sectional view of the display panel. In the figure, reference numeral 1 denotes a surface glass of a display panel in the gas discharge display device, and reference numeral 2 denotes a back glass of the display panel, which is opposed to the surface glass 1 at a predetermined interval.

A plurality of display anodes 3 are provided in parallel with the inner surface of the surface glass 1, and a plurality of anodes 4 are provided on the inner surface of the back glass 2 in a direction perpendicular to the direction in which the anodes 3 are arranged. The cathode 3 forms a display cell at the intersection with the anode 3 and the anode 3 and the cathode 4 constitute a discharge electrode. Reference numeral 5 denotes barrier ribs disposed between the anodes 3.

FIG. 7 is a block diagram showing a driving circuit for driving the display panel thus configured. In the figure, reference numeral 6 denotes the above-mentioned display panel, 7 denotes an anode driving IC for driving the anode 3, and 8 denotes a cathode driving IC for driving the cathode 4 similarly. Hereinafter, the anode driving IC 7 and the cathode driving IC 8 may be referred to as an electrode driving IC.

In the anode driving IC 7, reference numeral 71 denotes a shift register for transferring display data to a predetermined position.
Reference numeral 72 denotes a latch circuit for holding the display data shifted in the shift register 71, and reference numeral 73 denotes the latch circuit 7.
2 is a high breakdown voltage PNP type output transistor which drives the anode 3 of the display panel 6 based on the latch output of the PNP 2.

In the cathode driving IC 8, reference numeral 81 denotes a shift register for sequentially shifting the display control signal.
Reference numeral 83 denotes a high breakdown voltage NPN type output transistor for driving the cathode 4 of the display panel 6 based on the output of the shift register 81. Reference numeral 83 denotes an external transistor of the cathode drive IC 8 for maintaining the cathode 4 at a non-discharge voltage during non-display. With each output transistor 8
2 is a pull-up resistor connected to the collector.

FIG. 8 is a block diagram showing a circuit configuration of a display control system for converting a signal format, generating various timings, and the like. In the drawing, reference numeral 9 denotes an interface unit which converts a control signal, display data, and the like input from the outside into a format that can be displayed on the display panel 6 and supplies it to the anode driving IC 7 or the cathode driving IC 8.

In this interface unit 9, 91
, A data multiplexer / data buffer for dividing and storing data; 92, an anode timing generator for generating anode drive timing; 93, a modulation clock generator; 94, a cathode timing generator for generating anode drive timing; A panel clock generator that generates a clock signal for display timing control and supplies the generated clock signal to the anode timing generator 92, the modulation clock generator 93, and the cathode timing generator 94.

Next, the operation will be described. Here, FIG.
FIG. 10 is a configuration diagram showing a configuration of the shift register 71 in the anode driving IC 7, and FIG. 10 is a data configuration diagram showing a conversion format of the input data.

A display signal input from the outside is input to the interface unit 9 shown in FIG. 8 and processed into a signal for displaying on the display panel 6. That is, one line of display data input serially is first divided into even address data and odd address data by the data multiplexer / data buffer 91 as shown in FIG. Are divided into even address data and odd address data to form four series of data.

The four series of data processed in this manner are supplied to the anode drive I as shown in FIG.
The data is sent to the shift registers 71 in each of the first to fourth columns in C7.

When one line of display data is transferred to the shift register 71, a latch signal is output from the anode timing generator 92. The display data is transferred from the shift register 71 to the latch circuit 72 and held by the latch signal, and drives each anode 3 via the output transistor 73.

On the other hand, a clock signal and a display control signal are output from the cathode timing generator 94 in synchronization with the drive timing of the anode 3. This display control signal is sequentially shifted in the shift register 81 and drives the cathodes 4 one by one via the output transistor 82 in order.

The above control is performed in synchronization with the clock signal output from the panel clock generator 95. At the intersection of the driven anode 3 and cathode 4, gas discharge is generated to emit light. By these series of operations, characters and graphic information are displayed as dots.

FIG. 11 is a block diagram showing a configuration of an anode drive IC 7 for displaying a gradation on the display panel 6. As shown in FIG. In the figure, reference numeral 74 denotes a counter for counting the number of gradation control clocks from the display control system. Reference numeral 75 denotes a display time based on a comparison result between the data stored in the latch circuit 72 and the count value of the counter 74. This is a gradation control circuit for controlling. In this case, the output transistor 73 drives the anode 3 at a constant current, and 76 is a reference unit for determining the output current value.

Next, the operation will be described. Here, gradation display is performed by utilizing the fact that the light emission luminance is determined by the light emission duty per unit time, and the operation timing when displaying 16 gradations is shown in FIG.

In the case of performing 16-gradation display, gradation data for one display dot has a 4-bit configuration, and eight shift registers 71 are prepared to transfer data for two dots of display dots. ing. The grayscale data transferred to a predetermined position by these shift registers 71 is held in a latch circuit 72 according to a latch signal from the display control circuit side.

On the other hand, the counter 74 counts a gradation control clock (CCK) in hexadecimal, and sends the 4-bit count value to the gradation control circuit 75. The gradation control circuit 75 compares the count data from the counter 74 with the 4-bit gradation data latched by the latch circuit 72 for each display dot, and determines the combination with a signal (CL) indicating the entire time. , A drive signal (VHO _n ) for turning on the output transistor 73 only during a period when the gradation data is larger than the count data.

The output transistor 73 corresponding to each display dot conducts only during the period specified by the drive signal generated by the gradation control circuit 75 in this way, and the output current of the value specified by the reference unit 76 is output. Anode 3 for that period
And emits light at each intersection with the driven cathode 4 for that period, thereby realizing a luminance display corresponding to the gradation.

FIG. 13 is a connection diagram showing the connection between the display panel 6 and the electrode driving IC 7 (8). In the figure, reference numeral 10 denotes a circuit board such as a printed wiring board for mounting and wiring the electrode driving ICs 7 (8), and 11
Are electrodes for extracting the anode 3 or the cathode 4 formed in the display panel 6 to the outside. 12 is this electrode 11
It is a flexible wiring material such as a flexible wiring cable or a heat seal for connecting the circuit board 10 to the wiring board.

As shown in the figure, the signal lines in the display panel 6 are connected by mounting an electrode driving IC 7 (8) on a circuit board 10 by soldering or the like, and connecting the circuit board 10 and the electrodes 11 of the display panel 6 to each other. The two are connected by soldering a flexible wiring material 12. Also, the circuit board 1
The connection between 0 and the display control circuit is made via a connector using an electric wire such as a flexible flat cable because the number of signals to be transferred is small.

A document in which the technology related to such a conventional gas discharge display device is stored is, for example, "Flat Panel Display '90" (Nikkei BP, Nov. 1, 1989).

[0023]

The apparatus for implementing the conventional gas discharge display method is configured as described above.
The connection between the electrode 11 of the display panel 6 and the output of the electrode driving IC 7 (8) is made via the electrodes formed on the wiring material 12 as the number of display electrodes (for example, 1040 in the display panel 6 of 640 × 400 dots). However, it is necessary to solder or press-contact with almost the dimensional accuracy of the display dot, and the workability is extremely poor. In order to form a wiring terminal having a display pitch or the like, a wiring material 12 having a high dimensional accuracy is required. In the data line of the anode driving IC 7, a plurality of data are simultaneously transferred in order to increase the data transfer efficiency, and because of the cascade connection, the number of wirings between the ICs becomes extremely large and wiring becomes difficult. Since the display data is serial-parallel converted and transferred by a plurality of series of shift registers, it is necessary to deal with an increase in the number of display data. Increase the transfer rate by increasing the frequency of the clock signal for data shift, serial -
When the frequency of the data transfer clock must be increased and the frequency of the data transfer clock must be increased, the problem of electromagnetic noise is more likely to occur. Since the number of data transferred in the anode drive IC 7 is (number of bits required for gradation expression) × (data series), the number of shift registers 71 in the anode drive IC 7 becomes very large, Not only are there problems such as an increase in chip size and cost,
In the case of performing gradation display, a dedicated control mechanism for generating a clock signal for gradation control, display luminance control, a signal for display time control, and the like is necessary, and the cost is high. Since the tone display is performed every line by comparing the tone data composed of n bits with the count value of the tone control clock input from the outside, the anode drive IC 7
And a counter 74 for counting the clock for gradation control and a gradation control circuit 75 for comparing the display data and the counter value for each output terminal must be prepared. In the semiconductor manufacturing process for forming the output transistor 73, a large-scale logic circuit must be built, and there are problems such as an increase in the size of the IC chip and an increase in cost.

The present invention has been made to solve the above-described problems, and does not require a dedicated IC for gray scale display, and can flexibly cope with a change in the number of display gray scales. The purpose is to obtain a display method.

[0025]

According to the gas discharge display method of the present invention, n consecutive frames are used as basic units for completing gradation display, and one raster period in each frame in the basic unit is set to be longer than each other. The image is divided into m sub-rasters of different sizes, and gradation display is performed by designating which period of the n × m sub-rasters in the basic unit to emit light.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.

Embodiment 1 1 and 2 are block diagrams showing a first embodiment of the present invention. FIG. 1 is a block diagram of a signal processing circuit for performing data processing for gradation display, and FIG. 2 is a memory of the signal processing circuit. It is a block diagram which shows a structure and data arrangement.

In the drawing, reference numeral 7 denotes an anode driving IC for binary,
Reference numeral 71 denotes a shift register, reference numeral 72 denotes a latch circuit, reference numeral 73 denotes a constant current type output transistor, and reference numeral 76 denotes a reference unit, which is equivalent to the conventional one shown in FIGS. I do.

Reference numeral 21 denotes a data conversion unit for converting display data input from the outside into data for controlling the anode drive IC 7, and 22 for selecting data to be transferred and controlling the anode drive IC 7. Is a timing pulse generation unit that generates the above pulse.

Reference numeral 23 denotes a plurality of memories for storing the display data converted by the data conversion unit 21, each of which is constituted by a first-in first-out type memory element. Reference numeral 24 denotes a memory controller for controlling writing and reading of each memory 23;
3 is a 3 to 1 selector for selecting the data read out from the 3.

In FIG. 2, reference numeral 26 denotes a read control unit for determining from which of the memories 23 data is to be read, and reference numeral 27 denotes a write control unit for determining to which of the memories 23 data is to be written.

Next, the operation will be described. When performing 16-level gray scale display using the binary anode drive IC 7, as shown in FIG. 3, a basic unit for gray scale display is composed of two frames, a first frame and a second frame. Then, one raster period in each frame is divided into three sub rasters 31 to 33 and 34 to 36, respectively.

In this case, in the first frame, (9/16) H is applied to the first sub raster 31, (4/16) H is applied to the second sub raster 32, and (3/16) is applied to the third sub raster 33.
H, and in the second frame, (5/8) H for the first sub raster 34 and (2/8) for the second sub raster 35
H and the third sub-raster 36 are given different weights (time widths) of (1/8) H, and the lighting time is determined by the combination of the selected sub-rasters in the same display area during two frame periods. Thus, gradation display is performed.

When such a display means is employed, if a luminance difference between two frames as a unit of gradation display is large, the display is recognized as flicker and flicker of display, so that high-quality gradation display is obtained. Hateful. Therefore, it is necessary to set the luminance difference between the two frames to be equal to or less than a certain level.

When the above-described gradation display method is used, the brightness perceived by a human as the light emission luminance is expressed by the following equation (1).

[0036]

(Equation 1)

At this time, the luminance difference between frames is defined by the following equation (2), and it has been confirmed that flicker is hardly recognized if the luminance difference is 15% or less at a frame frequency of 70 Hz.

[0038]

(Equation 2)

Accordingly, by setting the difference in light emission luminance between frames at each gradation display to be within 15% of the maximum luminance when all the sub rasters 31 to 36 are selected, high-quality gradation display is achieved. It is possible. FIG. 3 shows an example of such a combination.

Data transfer and display control processing for gradation display are executed by the circuits shown in FIGS. In this circuit, display data of 16 bits and 16 bits inputted from the outside is converted into 3-bit data corresponding to display and non-display of a sub-raster in three sections in a corresponding frame. An example of a conversion table used for this conversion is shown in Table 1 below.

[0041]

[Table 1]

This data is stored in the memory 23 for each block so as to correspond to the block configuration of the anode drive IC 7. At this time, the frame switching selector determines which frame the data conversion weight corresponds to.

The data arranged and stored in correspondence with the block configuration of the anode drive IC 7 is read out in the next raster period, and the data of which sub raster 31 to 36 in one raster is read by the 2-bit 3-to-1 selector 25. It is determined whether or not there is, and is output to the anode drive IC 7 in synchronization with the shift clock generated by the timing pulse generator 22. FIG.
Shows the timing of data input from outside and data transfer to the anode drive IC 7.

In this method, since the data transfer rate is restricted by the minimum display period, the data is displayed in order from the display period having the longest display period so that the minimum display period is the last display period of one raster. Is performed including the blanking period. By adopting this method, the data transfer load is reduced.

The transfer of data to the anode drive IC 7 is delayed by one raster at the time of transfer and two rasters at the time of display, compared to the time of input, due to buffering by the memory 23. The data transfer to the corresponding raster (n-th raster) is to transfer the display data in the first sub-raster period of the n-th raster during the last minimum display period of the (n-1) -th raster, and to display the data of the second sub-raster when displaying the first sub-raster. In the transfer, the data transfer of the third sub-raster (the sub-raster of the minimum display period) is performed during the display of the second sub-raster.

The switching of the display by these data is performed by the shift register 71 of the anode drive IC 7 and the latch circuit 72.
A special circuit for switching the display is not required because the transfer is performed by transferring the data to the memory.

In order to perform gradation display in two frames, generally, 4-bit display input data for performing data conversion needs to be the same between two frames of gradation display. However, it is considered that the time for performing the display and being recognized as the gradation display is considered to be two frames or more, and it was confirmed that the change period of the actual display data was sufficiently longer than the display time of two frames.

Therefore, the two data conversion tables are switched for each frame irrespective of external factors, and the input display data is converted, whereby a sufficient gradation display can be performed. Even when the gradation data changes within the display unit, the gradation display of one frame at the time of the change is distorted, but since the display units before and after are held for a considerable time, the change in the gradation is hardly recognized. This eliminates the need for a frame memory.

As described above, according to the first embodiment, one raster period in each claim is set to m
By dividing into sub rasters, a dedicated IC for gradation display is not required, the apparatus cost can be reduced, and the number of display gradations can be changed.

Embodiment 2 In the first embodiment, 16-gradation display is performed using the binary anode driving IC. However, the present method may be adopted using a multi-gradation anode driving IC such as 4,16. By doing so, more gradation expression can be performed.

[0051]

As described above, according to the present invention, n consecutive frames are used as basic units for completing gradation display, and one raster period in each frame is divided into m sub rasters having different times from each other. And n × m in the basic unit
Since it is configured to specify which period of the sub-raster is to emit light, gradation display can be performed without the need for a dedicated IC for gradation display, and device cost can be reduced. In addition, there is an effect that a gas discharge display method that can flexibly cope with a change in the number of display gradations is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a signal processing circuit that performs data processing related to gradation display according to Embodiment 1 of the present invention;

FIG. 2 is a block diagram showing a memory configuration and a data arrangement in the signal processing circuit.

FIG. 3 is an explanatory diagram showing an example of a sub-raster division in a case where 16 frames are displayed in two frames as a basic unit in the embodiment.

FIG. 4 is a timing chart for explaining the operation of the embodiment.

FIG. 5 is a perspective view showing a main part of a structure of a display panel of an apparatus for performing a conventional gas discharge display method.

FIG. 6 is a sectional view of a main part of the display panel.

FIG. 7 is a block diagram showing a drive system of a conventional apparatus for performing gas discharge display.

FIG. 8 is a block diagram showing a conventional apparatus for performing gas discharge display.

FIG. 9 is a block diagram showing a configuration of the shift register.

FIG. 10 is a data configuration diagram showing a conversion format of display data in a conventional apparatus for performing gas discharge display.

FIG. 11 shows a conventional anode drive IC for performing gray scale display.
FIG.

FIG. 12 is a timing chart for explaining the operation.

FIG. 13 is a connection configuration diagram showing a connection between a display panel and a drive system in a conventional device for performing gas discharge display.

[Explanation of symbols]

3 anode, 4 cathode, 6 display panel, 7 anode drive I
C, 31-36 sub raster.

Claims (1)

[Claims] 1. A method according to claim 1, wherein a voltage corresponding to display data is selectively applied between a plurality of anodes and cathodes opposed to each other in a matrix with a predetermined discharge space in which a discharge luminous gas is sealed. In the gas discharge display method of causing the discharge luminous gas between the anode and the cathode to discharge and emit light to display characters and graphic information in gradations,
The n frames of the n-th frame are set as basic units for completing the gradation display, and one raster period in each frame in the basic unit is divided into m sub-rasters having different lengths from each other. A gas discharge display method characterized by performing gradation display by designating which period of the n × m sub-rasters in a unit to emit light.