JPH10242288A - Semiconductor device and system - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To enable defect relief after product shipment of a logic integrated circuit device LSI or the like on which a random access memory RAM or the like is mounted, and to enhance the reliability of the logic integrated circuit device or the like and a computer including the same. . Further, the function test and defect remedy of a logic integrated circuit device and the like are made more efficient, and the test cost is reduced. SOLUTION: A logic integrated circuit device LSI or the like on which a semiconductor memory such as a random access memory RAM is mounted is provided with a built-in self-test circuit BIST and a failure according to a function test result at the time of power-on reset by the built-in self-test circuit BIST, for example. A defect relieving circuit for automatically replacing the defective element with a redundant element, that is, a redundant address switching circuit RAXC is provided. Further, the built-in self-test circuit BIST and the redundant address switching circuit RAXC are used for a functional test and a defect relief in a predetermined manufacturing process of a logic integrated circuit device or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a system, for example, a logic integrated circuit device having a random access memory and a built-in self-test circuit, and a technique particularly effective when used in a computer including the same. .

[0002]

2. Description of the Related Art An ASIC (Application Splicing) having a semiconductor memory such as a random access memory mounted thereon
effective Integrated Circuit
s) and the like. In such a logic integrated circuit device or the like, for example, a predetermined number of redundant elements are provided in a memory array of a random access memory, and these redundant elements are replaced with defective elements detected in a test process, thereby making the logic integrated circuit device or the like. A so-called defect remedy technique for increasing the product yield is known.

On the other hand, there is a system such as a computer including a logic integrated circuit device equipped with a random access memory as described above. By providing a built-in self-test circuit in a logic integrated circuit device or the like as a component of the computer, for example, A so-called BIST that effectively realizes a system functional test at the time of on-reset
(Biult In Self Test) technology is known.

[0004]

In a conventional logic integrated circuit device or the like in which a semiconductor memory such as a random access memory is mounted, replacement of a defective element with a redundant element is performed in a predetermined test process at the time of manufacturing. By selectively cutting fuses corresponding to each bit of the address signal, allocation of redundant elements is realized. For this reason, if a logic integrated circuit device or the like has a deteriorating / progressive defect and becomes a failure after being shipped as a product, it cannot be remedied by a redundant element.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to relieve a defect of a logic integrated circuit device or the like having a random access memory or the like after the product is shipped, and to improve the reliability of the logic integrated circuit device or the like and a computer or the like including the same. is there. Another object of the present invention is to improve the efficiency of defect repair of a logic integrated circuit device or the like equipped with a random access memory and a built-in self-test circuit, and to reduce the test cost.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a built-in self-test circuit and a defective element that has failed according to a function test result at the time of power-on reset by, for example, a built-in self-test circuit are automatically added to a logic integrated circuit device equipped with a semiconductor memory such as a random access memory. And a defect relieving circuit for replacing the redundant element. Further, the built-in self-test circuit and the defect rescue circuit are used for a functional test and a defect remedy in a predetermined manufacturing process of a logic integrated circuit device or the like.

According to the above-described means, even if a logic integrated circuit device or the like has a degradable or progressive defect and fails after shipment of the product, the defect can be remedied by the defect rescue circuit. The reliability of the logic integrated circuit device and the like, and furthermore, the computer and the like including the same can be improved. In addition, by utilizing the built-in self-test circuit and the defect rescue circuit for the function test and the defect rescue at the time of manufacturing, the function test and the defect rescue of the logic integrated circuit device and the like can be efficiently performed, and the test cost can be reduced.

[0009]

FIG. 1 is a block diagram showing one embodiment of a logic integrated circuit device LSI (semiconductor device) to which the present invention is applied. First, the outline of the configuration and operation of the logic integrated circuit device LSI of this embodiment will be described with reference to FIG. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, known MOSFETs (metal oxide semiconductor type field effect transistors. In this specification, MOSFETs are collectively referred to as insulated gate type field effect transistors). A) It is formed on one semiconductor substrate such as single crystal silicon by an integrated circuit manufacturing technique. Although not particularly limited, the logic integrated circuit device LSI of this embodiment constitutes a predetermined computer system together with a plurality of other functional blocks.

In FIG. 1, a logic integrated circuit device LSI of this embodiment includes a semiconductor memory, that is, a random access memory RAM as an internal circuit, and a logic circuit LC formed by combining a large number of gate array cells or standard cells, for example. . Further, the logic integrated circuit device LSI
It includes a test circuit provided between the random access memory RAM and the logic circuit LC, ie, a built-in self-test circuit BIST, and a defect repair circuit, ie, a redundant address switching circuit RAXC.

Here, a random access memory RAM
Includes four redundant word lines serving as redundant elements, as described later. A redundant address switching circuit RAXC
Includes four redundant address latches and redundant address comparison circuits provided corresponding to these redundant word lines,
The built-in self-test circuit BIST includes an address counter and a pattern generator for autonomously performing a function test of the random access memory RAM at the time of a power-on reset or the like.

The logic circuit LC is connected to a central processing unit (not shown) of the computer via an address bus ADD, a data bus DATA and a control bus CTL. Address signals supplied via these buses,
Data and control signals are transmitted to the random access memory RAM via the built-in self test circuit BIST and the redundant address switching circuit RAXC.

FIG. 2 shows the logic integrated circuit device LSI shown in FIG.
Is a block diagram of an embodiment of a random access memory RAM included in the RAM. The configuration and operation of the random access memory RAM will be described with reference to FIG.

In FIG. 2, a random access memory R
The AM has a memory array MARY arranged so as to occupy most of the layout area as its basic component. The memory array MARY includes a predetermined number of word lines and four redundant word lines WR0 to WR0 arranged in parallel in the vertical direction in FIG.
WR3, a predetermined number of complementary bit lines arranged in parallel in the horizontal direction, and a large number of static memory cells arranged in a grid at intersections of these word lines and complementary bit lines.

The word lines and redundant word lines WR0 to WR3 forming memory array MARY are connected above to X address decoder XD. The X address decoder XD is supplied with a predetermined bit of an address signal via an address bus ADD. Further, 4-bit redundancy selection signals XR0 to XR3 are supplied from a redundancy address switching circuit RAXC to be described later, and an internal control signal for decoding operation control is supplied from the memory controller MCTL.

X address decoder XD is selectively activated in response to a high level of an internal control signal supplied from memory controller MCTL. At this time, the X address decoder XD decodes a predetermined bit of the address signal and selectively sets a corresponding word line of the memory array MARY to a predetermined selection level. When any of the redundancy selection signals XR0 to XR3 is set to a high level, the decoding operation of these address signals is stopped, and the corresponding redundancy word lines WR0 to WR3 of the memory array MARY are selectively selected. And

On the other hand, the complementary bit lines constituting the memory array MARY are coupled to the Y switch circuit YS on the left side, and are selectively connected to each unit circuit of the read / write circuit RW by a predetermined set. Y switch circuit YS has Y
A bit line selection signal of a predetermined bit is supplied from the address decoder YD, and an internal control signal for controlling a write or read operation is supplied from the memory controller MCTL to the read / write circuit RW. Further, another predetermined bit of the address signal is supplied to the Y address decoder YD via the address bus ADD, and an internal control signal for controlling a decoding operation is supplied from the memory controller MCTL.

The Y address decoder YD is selectively activated by receiving a high level of an internal control signal supplied from the memory controller MCTL. At this time, the Y address decoder YD decodes another predetermined bit of the address signal and selectively sets the corresponding bit line selection signal to a high level.

The Y switch circuit YS includes a memory array MA
A predetermined set of switch MOSFETs provided corresponding to each complementary bit line of RY is included. These switches MOSF
ET are selectively turned on by predetermined groups in response to the high level of the corresponding bit line selection signal, and the memory array M
The connection between the corresponding set of complementary bit lines of the ARY and the corresponding unit circuit of the read / write circuit RW is selectively connected.

The read / write circuit RW includes a data bus DA.
It includes a predetermined number of unit circuits provided corresponding to each bit of TA, and each of these unit circuits includes a write amplifier and a read amplifier. Of these, the write amplifier of each unit circuit operates the memory controller M when the random access memory RAM is selected in the write mode.
In response to the high level of the internal control signal supplied from the CTL, the operation state is selectively and simultaneously performed, and the data bus DA
Write data supplied via the TA is written to a predetermined number of selected memory cells of the memory array MARY.
Further, when the random access memory RAM is set to the selected state in the read mode, the read amplifier of each unit circuit selectively operates in response to the high level of another internal control signal supplied from the memory controller MCTL, A read signal output from a predetermined number of selected memory cells of the memory array MARY via the Y switch circuit YS is amplified, and the data bus DA is read as read data.
Output to TA.

The memory controller MCTL determines the operation modes of the random access memory RAM based on various activation control signals supplied via the control bus CTL, and controls various internal controls necessary for controlling these operation modes. A signal is selectively formed and supplied to each part of the random access memory RAM.

FIG. 3 shows the logic integrated circuit device LSI of FIG.
Is a block diagram of an embodiment of a redundant address switching circuit RAXC included in the embodiment. The outline of the configuration and operation of the redundant address switching circuit RAXC will be described with reference to FIG.

In FIG. 3, a redundant address switching circuit RAXC is connected to a redundant word line WR of a memory array MARY.
It includes four redundant address comparison circuits RAC0 to RAC3 and redundant address latches RAL0 to RAL3 provided corresponding to 0 to WR3. Further, it includes four edge-triggered flip-flops RF0 to RF3 provided corresponding to each redundant address latch, and further includes another flip-flop RFE serially coupled to the end of these flip-flops.

The logic "0", that is, the ground potential of the circuit is constantly supplied to the data input terminal D of the flip-flop RF0.
The data input terminal D of E is supplied with the non-inverted output signals Q of the preceding flip-flops RF0 to RF3. A reset signal RRST is commonly supplied to the set input terminal S of the flip-flop RF0 and the reset input terminals R of the flip-flops RF1 to RF3 and RFE from the built-in self-test circuit BIST.
The flip-flops RF0 to RF3 and the clock input terminal CK of the RFE are connected to an AND gate AG5.
Are commonly supplied. As a result, the flip-flops RF0 to RF3 and RFE act as a shift register that performs a shift operation according to the output signal of the AND gate AG5.

The non-inverted output signal Q of the flip-flops RF0 to RF3 is further applied to the corresponding AND gates AG1 to AG.
It is supplied to one input terminal of G4. The non-inverted output signal Q of the flip-flop RFE is used as a redundant error signal RR as a built-in self-test circuit BIS.
After being supplied to T and inverted by the inverter V1, it is supplied to one input terminal of the AND gate AG5. A redundant clock signal RCK is supplied from the built-in self-test circuit BIST to the other input terminal of the AND gate AG5. Also, And Gate AG
Redundancy request signal RREQ is commonly supplied from built-in self-test circuit BIST to the other input terminals of 1 to AG4, and output signals of AND gates AG1 to AG4 are supplied to corresponding redundant address latches RAL0 to RAL3, respectively. .

The output signals of redundant address latches RAL0 to RAL3 are supplied to corresponding redundant address comparing circuits RAC0 to RAC0.
It is supplied to one input terminal of RAC3. A predetermined bit for selecting a word line of an address signal, that is, an X address signal is commonly supplied to the other input terminals of these redundant address comparison circuits via an address bus ADD. Each of redundant address latches RAL0 to RAL3 further includes a redundancy enable circuit (not shown), and output signals thereof, that is, redundant enable signals REN0 to REN3, are supplied to corresponding redundant address comparison circuits RAC0 to RAC3.

The reset signal RRST is set to a high level for a predetermined period when a reset signal is issued by a computer including the logic integrated circuit device LSI, for example, during a power-on reset. Also, the redundancy request signal RREQ
Is a built-in self-test circuit BI
When any abnormality is detected in the memory array MARY of the random access memory RAM in the functional test by the ST and the defect relief by the redundant word lines WR0 to WR3 is required, the level is selectively set to the high level. Further, the redundancy clock signal RCK is temporarily set to the high level immediately after the redundancy request signal RREQ which has been set to the high level under the above conditions is returned to the low level, and the redundancy enable signals REN0 to REN
EN3 is a corresponding redundant address latch RAL0-RA
When a defective address is assigned to L3, it is selectively set to the high level.

From these, first, the reset signal RR
When ST goes high, flip-flop RF
When 0 is set, the non-inverted output signal Q becomes logic "1", that is, at a high level, and the other flip-flops RF1 to RF3 and RFE are both reset and the non-inverted output signal Q becomes logic "1". 0 ", that is, low level. Redundant address latches RAL0-R
AL3 is reset simultaneously upon receiving the high level of the reset signal RRST. Also, the output signal of the redundancy enable circuit, that is, the redundancy enable signal REN0-REN0
REN3 is also all at low level, and the address comparison and collation operation by the redundant address comparison circuits RAC0 to RAC3 is stopped. Therefore, the redundancy selection signals XR0 to XR3
Become low level, and the X address decoder XD of the random access memory RAM can perform a normal X address signal decoding operation.

When any abnormality is detected in the memory array MARY of the random access memory RAM in the function test by the built-in self test circuit BIST and the redundancy request signal RREQ is set to the high level, first, the flip-flop RF0 in the set state is not inverted. The output signal of AND gate AG1 receiving the high level of output signal Q is set to the high level in synchronization with redundancy request signal RREQ. Therefore, the address input via the address bus ADD, in other words, the defective address corresponding to the portion where the abnormality of the memory array MARY is detected, is taken into the redundant address latch RAL0 and held. In response to this, the output signal of the redundancy enable circuit of the redundancy address latch RAL0, that is, the redundancy enable signal REN0 is set to the high level, and the redundancy address comparison circuit RAC0 is made operable.

In a subsequent access, redundant address comparison circuit RAC0 provides a redundant address latch R corresponding to the access address input via address bus ADD.
The bit is compared with the defective address held in AL0 bit by bit, and on condition that both bits match all bits,
The output signal, that is, the redundancy selection signal XR0 is selectively set to a high level. As described above, in the random access memory RAM, the decoding operation of the normal X address signal by the X address decoder XD is stopped in response to the high level of the redundancy selection signal XR0, and the selection of the designated word line including the defect of the memory array MARY is stopped. Operation is prohibited,
Instead, the redundant word line WR0 is alternatively set to a high level, thereby realizing defect relief.

The redundant address switching circuit RA
In XC, as described above, when the redundancy request signal RREQ is returned to a low level, the redundancy clock signal RCK is temporarily set to a high level. Therefore, AND gate A
The output signal of G5 goes high in synchronization with the redundant clock signal RCK, and the shift register including the flip-flops RF0 to RF3 and RFE performs a shift operation of one bit. That is, the flip-flop RF0
Is reset because the data input terminal D receives the ground potential of the circuit, and the non-inverted output signal Q changes to low level. Also, the flip-flop RF1
Receives a high level immediately before the non-inverted output signal Q of the flip-flop RF0, and enters a set state, and the non-inverted output signal Q changes to a high level. Further, the flip-flop RF2 receives the low level immediately before the non-inverted output signal Q of the flip-flop RF1 and is reset as it is, and the non-inverted output signal Q remains at the low level. For the same reason, the flip-flops RF3 and RFE are also kept in the reset state, and their non-inverted output signals Q are both kept at the low level.

When two or more abnormalities are detected in the memory array MARY of the random access memory RAM in the function test by the built-in self-test circuit BIST, and the redundancy request signal RREQ is set to the high level again, the flip-flop in the set state is set. The output signal of AND gate AG2 receiving the high level of non-inverted output signal Q of transistor RF1 is set to the high level in synchronization with redundancy request signal RREQ. For this reason, the address input via the address bus ADD, that is, the defective address corresponding to the second portion where the abnormality of the memory array MARY is detected is fetched and held in the redundant address latch RAL1.
In response to this, the redundancy enable signal REN1 is set to the high level, and the redundancy address comparison circuit RAC1 is made operable together with the redundancy address comparison circuit RAC0. Needless to say, the redundancy request signal RREQ is returned to the low level and the redundancy clock signal RCK is set to the high level, so that the flip-flops RF0 to RF3 and RF
The shift register made of E performs a shift operation for one bit again to prepare for the next abnormality detection.

Hereinafter, similarly, the random access memory R is subjected to a function test by the built-in self-test circuit BIST.
Each time an abnormality is detected in the AM memory array MARY, the redundancy request signal RREQ is set to the high level, and the corresponding defective address is sequentially taken into the redundant address latches RAC2 to RAC3. Also, the redundancy enable signals REN2 to REN3 sequentially become high level in response to the fetch of the defective address, and the flip-flops RF0 to RF3 and RFE in response to the high level of the redundancy clock signal RCK.
Is repeated.
Then, the four redundant address latches RAL0 to RAL3
Of defective address for, in other words, 4
When all of the redundant word lines WR0 to WR3 have been subjected to defect relief, when the flip-flop RFE is set, the output signal thereof, that is, the redundant error signal RER becomes high level, and the built-in self-test circuit BIST
Is notified that all redundant elements are in use.

FIG. 4 shows the logic integrated circuit device LSI of FIG.
Is a block diagram of an embodiment of a built-in self-test circuit BIST included in the present embodiment. FIG. 5 is a block diagram of one embodiment of the test control circuit TCTL included in the built-in self-test circuit BIST of FIG. 4, and FIGS. 6 and 7 show the test control circuit TCTL of FIG.
1 shows a processing flow and a truth diagram of one embodiment. With reference to these figures, the configuration and operation of the built-in self-test circuit BIST of the logic integrated circuit device LSI of this embodiment, the outline of the functional test by this and the features thereof will be described. Note that the truth table of FIG. 7 will not be particularly described and will not be described, but it should be referred to when necessary in the description of other drawings.

Referring to FIG. 4, a built-in self-test circuit BIST includes a test control circuit TCT which is a central part thereof.
L, address counter ACTR, address selection circuit A
SEL, a pattern generator PATG, a data selection circuit DSEL, and a test data comparison circuit TSTC. The test control circuit TCTL includes a control signal CTL, a test request signal REQ,
Clock signal CK and system reset signal RST
Is supplied, a redundant error signal RR is supplied from the redundant address switching circuit RAXC, and a test fail signal FA is supplied from the test data comparing circuit TSTC.
An IL is provided.

Next, a built-in self-test circuit BIS
The T address counter ACTR, the pattern generator PATG, and the test data comparison circuit TSTC include:
The reset signal BRST and the clock signal BCK are commonly supplied from the test control circuit TCTL, and the selection control signal SC is commonly supplied to the address selection circuit ASEL and the data selection circuit DSEL. Further, an address signal of a predetermined bit is supplied to one input terminal of the address selection circuit ASEL via the address bus ADD, and an output signal of the address counter ACTR, that is, a test address signal TAD is supplied to the other input terminal. Is done. Further, one input terminal of the data selection circuit DSEL is coupled to the data bus DATA, and the other input terminal is
Test data TDT from pattern generator PATG
Is supplied. The test data TDT is also supplied to one input terminal of the test data comparison circuit TSTC. The other input terminal of the test data comparison circuit TSTC receives a data bus DATA from the redundant address switching circuit RAXC.
In addition, test read data of the random access memory RAM is supplied via the data selection circuit DSEL.

The test control circuit TCTL is selectively activated in response to a high level of a test request signal REQ supplied from the system side, for example, at the time of a power-on reset, and a random access memory formed on the same semiconductor substrate. The function test of the RAM is started and controlled according to the clock signal CK. Then, the test data comparison circuit TS
The function test result is determined based on the test fail signal FAIL output from the TC, and the test confirmation signal A
CK, a test result signal RES and test error signals ER0 and ER1 are selectively formed to form a logic circuit LC.
, The redundancy request signal RREQ and the redundancy clock signal R
CK and a reset signal RRST are selectively formed and output to the redundant address switching circuit RAXC.

On the other hand, the address counter ACTR is initialized according to the reset signal BRST, then sequentially generates a test address signal TAD required for a functional test according to a clock signal BCK by a predetermined algorithm, and is connected to one input of an address selection circuit ASEL. Supply to terminal. Further, the pattern generator PATG also outputs the reset signal B
After being initialized according to the RST, test data TDT necessary for a functional test is generated according to the clock signal BCK,
The data is supplied to the data selection circuit DSEL.

The address selection circuit ASEL generates a test address signal TAD output from the address counter ACTR or an address bus ADD according to the selection control signal SC.
And supplies it to the redundant address switching circuit RAXC via the address bus ADD. Also, the data selection circuit DSE
L selects test data TDT output from the pattern generator PATG or normal write data supplied via the data bus DATA in accordance with the selection control signal SC, and supplies it to the redundant address switching circuit RAXC via the data bus DATA. . The test data comparison circuit TSTC includes the test data TDT supplied from the pattern generator PATG and the random access memory R
The test read data supplied from the AM via the data selection circuit DSEL is compared and collated bit by bit to determine the normality of the function test. As a result, when the two data match and the function test ends normally, the test control circuit TCT
The test fail signal FAIL for L is set to a low level, and when both data do not match and an abnormality occurs in the function test, the test fail signal FAIL is set to a high level.

Here, the test control circuit TCTL is not particularly limited, but as shown in FIG. 5, a test control logic circuit CL serving as a control center of the function test, a 4-bit status register SREG, and a 3-bit And a flag register FREG. The test control logic circuit CL is connected to the logic circuit LC via the control bus CTL.
And a clock signal CK, a test request signal REQ, and a system reset signal RST are supplied from the logic circuit LC. The test control logic circuit CL is further supplied with a test fail signal FAIL from the test data comparison circuit TSTC. Further, a redundant error signal RR is supplied from the redundant address switching circuit RAXC, and an output signal Q is output from the status register SREG.
0 to P3 are supplied as status signals PS0 to PS3.

The status register SREG is composed of a 4-bit D-type flip-flop DFF, and the corresponding status signals S0 to S3 are supplied from the test control logic circuit CL to the data input terminals D0 to D3 of the respective bits. . The output signals Q0 to Q3 of each bit are
As described above, the status signals PS0 to PS3 are supplied to the test control logic circuit CL. The clock signal CK is commonly supplied to the clock input terminal CK of the status register SREG, and the reset input terminal R
The system reset signal RST is commonly supplied.

On the other hand, the flag register FREG is made up of a 3-bit set-reset flip-flop. The set input terminals S0 to S3 of the respective bits are supplied with corresponding flag signals FLGR and FLG from the test control logic circuit CL.
E0 or FLGE1 is supplied, respectively. A system reset signal RST is commonly supplied to a reset input terminal R of each bit of the flag register FREG.

The test control logic circuit CL includes a logic circuit LC
Control signal CTL and test request signal REQ supplied from
, A function test at the time of, for example, power-on reset is selectively started and controlled. The status register SREG includes a built-in self-test circuit BIST.
And the flag register FREG outputs the test result to the test result signal RES.
Alternatively, the error is reported to the logic circuit LC as the test error signal ER0 or ER1. As shown in FIG. 7, the function test by the test control circuit TCTL is performed in the status register SR.
Sequence is performed according to the set value of EG, and step control is performed.

Here, a processing procedure and an outline of a functional test by the test control circuit TCTL of the built-in self-test circuit BIST will be described with reference to FIG.

In FIG. 6, when a power supply of a computer including a logic integrated circuit device LSI is turned on, an initialization instruction is first issued from a power-on reset circuit (not shown).
System reset signal RST and reset signal BR
ST and RRST are subsequently set to the high level. In the built-in self-test circuit BIST, the reset signal BR
In response to the high level of ST, the address counter ACTR
And the pattern generator PATG is initialized. In the redundant address switching circuit RAXC, as described above, the flip-flop RFn is initialized in response to the high level of the reset signal RRST, that is, the flip-flop RF0 is set, and the flip-flop RF0 is set.
F1 to RF3 and RFE are reset.

Next, when the test request signal REQ is set to the high level to request the start of the function test, the built-in self-test circuit BIST starts the first function test for all the addresses of the memory array MARY, ie, test 1. Is done. At this time, the address counter ACTR
Performs a step-by-step operation to sequentially specify the addresses of the memory array MARY, and the pattern generator PATG generates a predetermined test pattern. Among them, the test address signal T generated by the address counter ACTR is used.
AD is transmitted to the random access memory RAM via the address selection circuit ASEL as described above, and the test data TDT generated by the pattern generator PATG is transmitted from the data selection circuit DSEL to the data bus DA.
It is transmitted to the random access memory RAM via TA.

The test data TDT written at the specified address of the random access memory RAM is read from the specified address of the memory array MARY by a subsequent test read operation, and then written by the test data comparison circuit TSTC. This is compared with the test data TDT. As a result, if both match and the test result is determined to be good, the built-in self-test circuit BIST sets the test confirmation signal ACK to a high level and reports a normal test end to the system. If they do not match, the redundancy request signal RR
The redundancy address switching circuit RA with the EQ set to high level
Request XC for defect relief. Further, on the condition that the flip-flop RFE of the redundant address switching circuit RAXC is not in the ON state, in other words, the memory array M
All redundant word lines WR0-WR prepared in ARY
Test 2 is executed on condition that 3 is not already used, and the normality of the redundant word line newly used for defect repair is confirmed.

As a result, when the redundant word line newly used for defect repair is normal, the built-in self-test circuit BIST sets the test confirmation signal ACK to high level and reports the normal end of the test to the system side. All redundant word lines WR0 prepared in memory array MARY
When WR3 to WR3 are used and the redundant error signal RR is set to the high level, or when any abnormality occurs in the test result, the built-in self-test circuit BIST
The test error signal ERn, that is, ER0 or ER1 is selectively set to a high level to notify the system of abnormal termination.

As described above, the logic integrated circuit device LSI of this embodiment has a relatively large-capacity random access memory RAM, a built-in self-test circuit BIST and a redundancy circuit formed on the same semiconductor substrate. An address switching circuit RAXC is mounted. The built-in self-test circuit BIST performs a functional test on all addresses of the memory array MARY constituting the random access memory RAM at the time of, for example, power-on reset, and determines whether or not the test is successful by the redundant address switching circuit RAX.
Notify C. The redundant address switching circuit RAXC is
Based on the result of the function test by the built-in self-test circuit BIST, the redundant word lines WR0 to WR3 are selectively assigned to addresses where a failure has been detected in the memory array MARY and replaced. As a result, in the logic integrated circuit device LSI of this embodiment, even after it has been shipped as a product and incorporated into the system, it is possible to relieve abnormalities caused by, for example, degradable / progressive defects. The reliability of the integrated circuit device LSI and the computer including the same can be improved.

The built-in self-test circuit BIS
Since the function test and the defect remedy by the T and the redundant address switching circuit RAXC can be utilized also during the manufacture of the logic integrated circuit device LSI, the function test and the defect remedy in the test process are made more efficient, and the test cost of the logic integrated circuit device LSI is reduced. Can be reduced.

FIG. 8 is a system configuration diagram of an embodiment of a computer including the logic integrated circuit device LSI of FIGS. 1 to 7. The outline of the application system of the logic integrated circuit device of this embodiment and its features will be described with reference to FIG.

In FIG. 8, the computer of this embodiment has a central processing unit CPU of a stored program system as its basic component. In this central processing unit CPU,
A random access memory R composed of the logic integrated circuit device LSI of FIGS. 1 to 7 via a system bus SBUS.
The read only memory ROM, the display controller DPYC and the peripheral device controller P separately formed as another semiconductor device while the AM is coupled.
The ERC is combined. Display controller DPY
A display device DPY is connected to C, and a keyboard KBD and an external storage device EXM are connected to the peripheral device controller PERC.

The central processing unit CPU operates stepwise according to the control program stored in the read-only memory ROM, and controls and controls each section of the computer. The random access memory RAM temporarily stores and relays, for example, a control program, arithmetic data, and the like transmitted from the read-only memory ROM to the central processing unit CPU. Further, the display controller DPYC is provided for display control of the display device DPY, and the peripheral device controller PERC controls peripheral devices such as the keyboard KBD and the external storage device EXM. The computer further includes a power supply unit POWU for forming a stable predetermined DC power supply voltage based on the predetermined AC input power supply voltage and supplying the stable DC power supply voltage to each unit of the computer.

In this embodiment, the memory array MARY of the random access memory RAM has four redundant word lines WR0 to WR3 as redundant elements as described above.
Is prepared. The logic integrated circuit device LSI is provided with a built-in self-test circuit BIST and a redundant address switching circuit RAXC. For example, a necessary function test is performed autonomously at power-on reset, and the redundant word lines WR0 to WR3 are used. Defect relief is performed autonomously. As a result, even if the logic integrated circuit device LSI has a deteriorating / progressive defect and fails after shipment of the product, the failure can be automatically remedied, whereby the logic integrated circuit device LSI and the The reliability of the computer including the above can be improved.

The built-in self-test circuit BIS
Although not particularly limited, T is also provided in each unit of the computer including the central processing unit CPU, and thereby, for example, a function test of each unit at the time of power-on reset is performed autonomously.

The operation and effect obtained from the above embodiment are as follows. (1) A built-in self-test circuit and, for example, a defect which has failed according to a function test result at the time of power-on reset by a built-in self-test circuit in a logic integrated circuit device or the like on which a semiconductor memory such as a random access memory is mounted. By providing a defect relief circuit that automatically replaces the element with a redundant element, even if a logic integrated circuit device or the like has a degradable or progressive defect and fails after shipping the product, the defect relief circuit can Can be saved. (2) According to the above item (1), there is obtained an effect that the reliability of the logic integrated circuit device and the like, and furthermore, the computer and the like including the same can be improved. (3) In the above items (1) and (2), the built-in self-test circuit and the defect rescue circuit are utilized for a function test and a defect remedy in a predetermined manufacturing process of the logic integrated circuit device or the like, so that the logic integrated circuit is used. The effect is obtained that the efficiency of the function test and the defect remedy of the device can be improved. (4) According to the above item (3), an effect is obtained that the test cost at the time of manufacturing a logic integrated circuit device or the like can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is. For example, in FIG. 1, the logic integrated circuit device LSI can mount a plurality of random access memories RAM, and its block configuration and bus configuration can adopt various embodiments. In FIG. 2, a random access memory R
Any number of redundant word lines can be provided in the AM memory array MARY. Further, in this embodiment, only the defect in the redundant word line, that is, the defect in the X address direction is rescued. For example, only the defect rescue in the Y address direction may be performed, or the defect rescue in the X and Y address directions may be performed. May be performed simultaneously. Memory array M of random access memory RAM
The ARY can be directly divided into a plurality of sub-memory arrays including peripheral circuits, and the block configuration is arbitrary.

In FIG. 3, random access memory R
When an AM functional test result is output corresponding to a word line or a bit line after decoding an address signal, the redundant address switching circuit RAXC needs to include an encoder for converting this into a binary signal. . The redundant address switching circuit RAXC can take various block configurations, and its bus configuration, the effective level of each signal, and the like are not restricted by this embodiment. 4 and 5, the built-in self-test circuit BIST and its test control circuit TCTL can be replaced with, for example, a processing device of a stored program system, and the block configuration and the bus configuration can also adopt various embodiments. In FIG. 6, the processing flow of the function test by the test control circuit TCTL is only an example, and does not limit the present invention.

In FIG. 8, the computer system configuration can take various embodiments. In this embodiment, the logic integrated circuit device LSI is provided with a built-in self-test circuit BIST for a function test. However, as illustrated in FIG. 9, the built-in self-test circuit BIST provided in the central processing unit CPU is provided. A function test of the random access memory RAM may be performed under the control of the BIST, and the result may be notified to the redundant address switching circuit RAXC. Further, as exemplified in FIG. 10, the central processing unit CPU, the built-in self-test circuit BIST,
The redundant address switching circuit RAXC and the random access memory RAM may be formed as a single logic integrated circuit device LSI on a common semiconductor substrate.

In the above description, the case where the invention made by the present inventor is mainly applied to a random access memory and a computer including the same, which are fields of application, has been described. However, the present invention is not limited to this. For example, the present invention can be applied to various semiconductor memories such as a read-only memory and various digital integrated circuit devices equipped with the same. The present invention can be widely applied to a semiconductor device including at least a redundant element and an apparatus or a system including such a semiconductor device.

[0061]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a built-in self-test circuit and a defective element that has failed according to a function test result at the time of power-on reset by, for example, a built-in self-test circuit are automatically added to a logic integrated circuit device equipped with a semiconductor memory such as a random access memory. And a defect relieving circuit for replacing the redundant element. Further, the built-in self-test circuit and the defect rescue circuit are used for a functional test and a defect remedy in a predetermined manufacturing process of a logic integrated circuit device or the like. Thus, even if a logic integrated circuit device or the like has a deteriorating or progressive defect and fails after shipment of a product, the defect can be remedied by the defect rescue circuit. Thus, the reliability of a computer or the like including the same can be improved. In addition, by utilizing the built-in self-test circuit and the defect rescue circuit for the function test and the defect rescue at the time of manufacturing, the function test and the defect rescue of the logic integrated circuit device and the like can be efficiently performed, and the test cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a logic integrated circuit device to which the present invention is applied.

FIG. 2 is a block diagram showing one embodiment of a random access memory included in the logic integrated circuit device of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of a redundant address switching circuit included in the logic integrated circuit device of FIG. 1;

FIG. 4 is a block diagram showing one embodiment of a built-in self-test circuit included in the logic integrated circuit device of FIG. 1;

FIG. 5 is a block diagram showing one embodiment of a test control circuit included in the built-in self-test circuit of FIG. 4;

FIG. 6 is a processing flowchart showing one embodiment of the test control circuit of FIG. 5;

FIG. 7 is a truth diagram illustrating an embodiment of the test control circuit of FIG. 5;

FIG. 8 is a system configuration diagram showing one embodiment of a computer including the logic integrated circuit device of FIG. 1;

FIG. 9 is a system configuration diagram showing a second embodiment of a computer including a logic integrated circuit device to which the present invention is applied.

FIG. 10 is a system configuration diagram showing a third embodiment of a computer including a logic integrated circuit device to which the present invention is applied.

[Explanation of symbols]

LSI: logic integrated circuit device, RAM: random access memory, RAXC: redundant address switching circuit,
BIST: Built-in self-test circuit, LC: Logic circuit, ADD: Address bus or address signal, D
ATA: Data bus or data, CTL: Control bus or control signal. MARY: Memory array, W
R0-WR3 ... redundant word line, XD ... X address decoder, RW ... read / write circuit, YS ... Y switch circuit, YD ... Y address decoder, MCTL ... memory controller, XR0-XR3 ... redundant selection signal.
RF0 to RF3, RFE: D-type flip-flop, R
AL0-RAL3 ... redundant address latch, RAC0
RAC3 ... redundant address comparison circuit, AG1 to AG5 ...
... AND gate, V1 ... inverter. TC
TL: Test control circuit, ACTR: Address counter, ASEL: Address selection circuit, PATG: Pattern generator, DSEL: Data selection circuit, TS
TC: Test data comparison circuit. CL: Test control logic circuit, SREG: Status register, FREG:
... Flag register. CPU: Central processing unit, SBUS
…… System bus, ROM …… Read-only memory, D
PYC: Display controller, DPY: Display device, PERC: Peripheral device controller, K
BD: Keyboard, EXM: External storage device, POW
U: Power supply unit.

Claims (7)

[Claims] 1. A semiconductor device comprising: a predetermined internal circuit including a redundant element; and a defect relief circuit for selectively replacing a defective portion with the redundant element according to a result of a function test of the internal circuit. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the semiconductor device includes a test circuit that autonomously executes a function test of the internal circuit. 3. The semiconductor device according to claim 1, wherein the semiconductor device is included in a predetermined system including a processing device of a stored program system, and the functional test of the internal circuit is performed by controlling the processing device. A semiconductor device characterized in that the semiconductor device is used. 4. The method according to claim 1, wherein the function test of the internal circuit and the replacement of the internal circuit with a redundant element are performed as follows.
A semiconductor device, which is performed when the power of the semiconductor device is turned on. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a logic integrated circuit device equipped with a semiconductor memory, and the internal circuit is the semiconductor memory. A semiconductor device characterized by the above-mentioned. 6. An internal circuit according to claim 1, wherein said internal circuit includes a predetermined number of said redundant elements, and said defect repair circuit comprises: A semiconductor device having a function of identifying and displaying that the semiconductor device has become unable to repair defects when the number of redundant elements replaced with the defective portions exceeds the predetermined number. . 7. A semiconductor device comprising: a predetermined internal circuit including a redundant element; and a defect relief circuit for selectively replacing a defective portion with the redundant element according to a result of a function test of the internal circuit. A system characterized by becoming.