JPH10242015A - Clad silicon substrate and its manufacture - Google Patents
Clad silicon substrate and its manufactureInfo
- Publication number
- JPH10242015A JPH10242015A JP6186597A JP6186597A JPH10242015A JP H10242015 A JPH10242015 A JP H10242015A JP 6186597 A JP6186597 A JP 6186597A JP 6186597 A JP6186597 A JP 6186597A JP H10242015 A JPH10242015 A JP H10242015A
- Authority
- JP
- Japan
- Prior art keywords
- bonded
- wafer
- polishing
- silicon
- silicon wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 89
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 89
- 239000010703 silicon Substances 0.000 title claims abstract description 89
- 239000000758 substrate Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000005498 polishing Methods 0.000 claims abstract description 53
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 16
- 235000012431 wafers Nutrition 0.000 claims description 84
- 238000000034 method Methods 0.000 claims description 8
- 238000010030 laminating Methods 0.000 claims description 2
- 230000003746 surface roughness Effects 0.000 abstract description 10
- 230000002950 deficient Effects 0.000 abstract description 5
- 239000007788 liquid Substances 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 5
- 229920002635 polyurethane Polymers 0.000 description 4
- 239000004814 polyurethane Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000006260 foam Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、例えばシリコン
面同士を直接張り合わせた張り合わせシリコン基板、酸
化膜を間に介在させたＳＯＩ（Ｓｉｌｉｃｏｎ ｏｎ
Ｉｎｓｕｌａｔｏｒ）基板およびその製造方法、特にウ
ェーハ同士の張り合わせ強度を大きくした張り合わせシ
リコン基板およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonded silicon substrate having silicon surfaces directly bonded to each other, and an SOI (silicon on silicon) having an oxide film interposed therebetween.
TECHNICAL FIELD The present invention relates to a bonded silicon substrate having increased bonding strength between wafers and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、例えばシリコン面同士を直接に張
り合わせた張り合わせシリコン基板、また、間に絶縁膜
を介在させたＳＯＩ基板のように、接着剤などを使わず
に２枚のシリコンウェーハ同士を張り合わせて一体化す
る技術が開発されている。直接張り合わせは、シリコン
ウェーハを洗浄して張り合わせ面（シリコン面）を親水
性化処理し、次いで、室温大気中において張り合わせ面
同士を重ね合わせて張り合わせ、それから加熱炉で張り
合わせ熱処理を施すものである。2. Description of the Related Art In recent years, for example, two silicon wafers are bonded together without using an adhesive, such as a bonded silicon substrate in which silicon surfaces are directly bonded to each other or an SOI substrate having an insulating film interposed therebetween. A technology for bonding and integrating has been developed. In the direct bonding, the silicon wafer is cleaned and the bonding surface (silicon surface) is made hydrophilic, then the bonding surfaces are stacked and bonded in the air at room temperature, and then the bonding heat treatment is performed in a heating furnace.
【０００３】張り合わせシリコン基板の活性層側基板に
あっては、デバイス作製上の要請により、シリコンウェ
ーハの鏡面研磨後の張り合わせ面に、例えばＳｂ（アン
チモン）などの不純物を所定の濃度プロファイルで拡散
する場合がある。このとき、鏡面研磨された張り合わせ
面は不純物の拡散により、例えばヘイズレベルで１．５
ｐｐｍ、Ｐ−Ｖ（Ｐｅａｋ ｔｏ Ｖａｌｌｅｙ）値で
５ｎｍ程度の面荒れが生じている。なお、Ｐ−Ｖ値は、
原子間力顕微鏡（ＡＦＭ：Ａｔｏｍｉｃ Ｆｏｒｃｅ
Ｍｉｃｒｏｓｃｏｐｙ）により測定した。In the substrate on the active layer side of the bonded silicon substrate, an impurity such as Sb (antimony) is diffused in a predetermined concentration profile to the bonded surface after mirror polishing of the silicon wafer due to a request in device fabrication. There are cases. At this time, the mirror-polished bonding surface is diffused by impurities, for example, at a haze level of 1.5.
The surface roughness is about 5 nm in ppm and PV (Peak to Valley) value. The PV value is
Atomic force microscope (AFM: Atomic Force)
Microscope).
【０００４】[0004]
【発明が解決しようとする課題】ところで、この張り合
わせシリコン基板のウェーハ間の接着力（接合力）は、
ウェーハ表面（張り合わせ界面）のマイクロラフネスが
大きく関与する。マイクロラフネスが悪化すると、熱処
理後、高い接合強度が得られない。よって、さらには、
ウェーハに未接合部分（未接着部分）であるボイドが発
生し、デバイス作製の各工程時にシリコンウェーハの剥
がれなどの不都合が生じるおそれがある。The adhesive force (bonding force) between the bonded silicon substrates between the wafers is as follows.
Micro-roughness on the wafer surface (bonding interface) greatly contributes. If the micro roughness is deteriorated, high bonding strength cannot be obtained after the heat treatment. So, furthermore,
Voids, which are unbonded portions (unbonded portions), are generated in the wafer, and inconveniences such as peeling of the silicon wafer may occur during each device manufacturing process.
【０００５】[0005]
【発明の目的】そこで、この発明は、シリコンウェーハ
の張り合わせ面をさらに仕上げ研磨することにより、ウ
ェーハの接合強度（接着強度）を従来よりも大きくする
ことができる張り合わせシリコン基板およびその製造方
法を提供することを、その目的としている。SUMMARY OF THE INVENTION Accordingly, the present invention provides a bonded silicon substrate and a method for manufacturing the same, which can further increase the bonding strength (adhesion strength) of the silicon wafer by finishing and polishing the bonded surface of the silicon wafer. Its purpose is to do.
【０００６】[0006]
【課題を解決するための手段】請求項１に記載の発明
は、鏡面研磨された張り合わせ面を有する２枚のシリコ
ンウェーハ同士を張り合わせた張り合わせシリコン基板
において、上記２枚のシリコンウェーハの少なくとも一
方のシリコンウェーハの張り合わせ面に、不純物の拡散
後に研磨量が０．１μｍ未満の仕上げ研磨が施され、こ
の研磨面を残りの他方のシリコンウェーハの張り合わせ
面に重ね合わせることにより張り合わされた張り合わせ
シリコン基板である。上記仕上げ研磨では、その研磨量
を０．１μｍ未満としたので、拡散された不純物の濃度
プロファイルに影響を与えることがない。ここでいう張
り合わせシリコン基板は、例えばベアシリコンウェーハ
同士を張り合わせたもの（直接張り合わせ）、表面にＳ
ｉＯ2膜を有するシリコンウェーハとベアシリコンウェ
ーハを張り合わせたもの（ＳＯＩ）、また、表面にＳｉ
Ｏ2膜を有するシリコンウェーハ同士を張り合わせたも
の（ＳＯＩ）を含む。According to a first aspect of the present invention, there is provided a bonded silicon substrate in which two silicon wafers having a mirror-polished bonded surface are bonded to each other, wherein at least one of the two silicon wafers is bonded. The bonded surface of the silicon wafer is subjected to finish polishing with a polishing amount of less than 0.1 μm after the diffusion of the impurity, and the polished surface is bonded to the bonded surface of the other silicon wafer by the bonded silicon substrate. is there. In the above-mentioned finish polishing, since the polishing amount is less than 0.1 μm, it does not affect the concentration profile of the diffused impurities. The bonded silicon substrate referred to here is, for example, a substrate obtained by bonding bare silicon wafers together (direct bonding),
A silicon wafer having an iO 2 film and a bare silicon wafer bonded together (SOI)
Includes silicon wafers having an O 2 film bonded together (SOI).
【０００７】また、ここでいう仕上げ研磨とは、研磨
布、研磨液などを用いた機械的化学的研磨（メカノケミ
カル研磨）をいう。この機械的化学的研磨は、表面基準
の研磨であり、例えばワックスレスマウント方式による
研磨である。使用する研磨剤は、例えば（株）フジミイ
ンコーポレーテッド製「ＦＧＬ−７００８」とする。使
用する研磨布は、ポリエステルフェルトにポリウレタン
を含浸させた基材に、ポリウレタンをコートし、ポリウ
レタン内に発泡層を成長させ、表面部位を除去し発泡層
に開口部を設けたものである。発泡層内に保持された研
磨剤がウェーハと発泡層内面との間で作用することによ
り、研磨が追行する。[0007] The term "final polishing" as used herein refers to mechanical chemical polishing (mechanochemical polishing) using a polishing cloth, a polishing liquid or the like. This mechanical chemical polishing is polishing based on a surface, for example, polishing by a waxless mounting method. The abrasive used is, for example, "FGL-7008" manufactured by Fujimi Incorporated. The polishing cloth to be used is one obtained by coating a polyurethane impregnated polyester with a polyurethane, coating a polyurethane, growing a foamed layer in the polyurethane, removing the surface portion, and providing an opening in the foamed layer. The polishing is carried out by the abrasive held in the foam layer acting between the wafer and the inner surface of the foam layer.
【０００８】好ましいシリコンウェーハの張り合わせ面
の研磨量は、０．１μｍ未満であり、０．１μｍ以上を
研磨するとなれば、拡散した不純物濃度プロファイルに
影響を与えるおそれがある。よって、所定深さまで不純
物を拡散しなければならず、その拡散工程が長期にわた
る結果となるという不具合がある。シリコンウェーハの
張り合わせ面に拡散される不純物としては、例えばＰ型
不純物としてＢ（ホウ素）、Ｉｎ（インジウム）など、
Ｎ型不純物としてはＰ（リン）、Ａｓ（ヒ素）、Ｓｂ
（アンチモン）などがある。これらの事項は、請求項２
〜請求項４に記載の張り合わせシリコン基板およびその
製法の場合も同様である。The preferable polishing amount of the bonded surface of the silicon wafer is less than 0.1 μm. If the polishing amount is 0.1 μm or more, there is a possibility that the diffused impurity concentration profile may be affected. Therefore, there is a problem that the impurity must be diffused to a predetermined depth, and the diffusion process results in a long-term result. Examples of impurities diffused on the bonding surface of the silicon wafer include P-type impurities such as B (boron) and In (indium).
P (phosphorus), As (arsenic), Sb
(Antimony). These matters are described in claim 2
The same applies to the case of the bonded silicon substrate and the method of manufacturing the same.
【０００９】請求項２に記載の発明は、上記仕上げ研磨
は、研磨面をヘイズレベルで０．５ｐｐｍ以下またはＰ
−Ｖ値で４ｎｍ以下とする研磨である請求項１に記載の
張り合わせシリコン基板である。シリコンウェーハの研
磨によるウェーハ表面の粗さの成分であって、数〜数十
μｍの周期をもった微小な表面粗さであるヘイズ値の好
ましい値は、レーザ光が垂直に入射する方式のパーティ
クルカウンタ、例えば（株）テンコール社「ＳＦＳ６２
００」による測定値で０．２ｐｐｍ未満である。このヘ
イズ値が大きくなると、例えば０．５ｐｐｍを超える
と、ＳＣ１液での面荒れが大きくなり、張り合わせでの
接合強度が低下する。また、Ｐ−Ｖ値では４ｎｍ以下で
あり、４ｎｍを超えると同じく強度低下、面荒れを生じ
る。[0009] In the invention described in claim 2, in the finish polishing, the polished surface has a haze level of 0.5 ppm or less or P
2. The bonded silicon substrate according to claim 1, wherein the polishing is performed so that the −V value is 4 nm or less. 3. A preferable value of the haze value, which is a component of the wafer surface roughness due to polishing of a silicon wafer and is a minute surface roughness having a period of several to several tens of μm, is a particle of a system in which laser light is vertically incident. Counter, for example, Tencor Co., Ltd. “SFS62
00 "is less than 0.2 ppm. If the haze value is large, for example, if it exceeds 0.5 ppm, the surface roughness in the SC1 solution will be large, and the bonding strength in bonding will be reduced. Further, the PV value is 4 nm or less, and if it exceeds 4 nm, the strength is reduced and the surface is roughened.
【００１０】請求項３に記載の発明は、第１のシリコン
ウェーハの鏡面研磨された張り合わせ面に不純物を拡散
する工程と、この不純物拡散後の張り合わせ面に研磨量
が０．１μｍ未満の仕上げ研磨を施す工程と、この仕上
げ研磨面を第２のシリコンウェーハの張り合わせ面に重
ね合わせることにより、張り合わせシリコン基板を製造
する張り合わせ工程と、を備えた張り合わせシリコン基
板の製造方法である。なお、この室温での張り合わせ
後、所定の張り合わせ熱処理を施す。According to a third aspect of the present invention, there is provided a method for diffusing an impurity on a mirror-polished bonding surface of a first silicon wafer, and a finishing polishing process with a polishing amount of less than 0.1 μm on the bonding surface after the impurity diffusion. And a bonding step of manufacturing a bonded silicon substrate by laminating the finished polished surface to the bonded surface of the second silicon wafer. After the bonding at room temperature, a predetermined bonding heat treatment is performed.
【００１１】ここでＳＣ１洗浄とは、例えばＮＨ4Ｏ
Ｈ：Ｈ2Ｏ2： Ｈ2Ｏ＝１：１：５というアンモニアと
過酸化水素水との混合液（８０℃）を用いて、シリコン
ウェーハの表面を薄くエッチングすることにより、この
ウェーハ表面のパーティクルを除去する洗浄のことであ
る。Here, SC1 cleaning means, for example, NH 4 O
The surface of the silicon wafer is thinly etched by using a mixed solution (80 ° C.) of ammonia and hydrogen peroxide solution of H: H 2 O 2 : H 2 O = 1: 1: 5. Cleaning to remove particles.
【００１２】請求項４に記載の発明は、上記仕上げ研磨
は、研磨面がヘイズレベルで０．５ｐｐｍ以下またはＰ
−Ｖ値で４ｎｍ以下とする研磨である請求項３に記載の
張り合わせシリコン基板の製造方法である。According to a fourth aspect of the present invention, in the finish polishing, the polished surface has a haze level of 0.5 ppm or less or P
4. The method for manufacturing a bonded silicon substrate according to claim 3, wherein the polishing is performed to make the -V value 4 nm or less.
【００１３】[0013]
【作用】張り合わされるシリコンウェーハの作製工程に
おいて、通常は、シリコンウェーハの張り合わせ面に不
純物を拡散することにより表面が荒れてしまう。ウェー
ハ表面の粗さは、例えばテンコール（株）の「ＳＦＳ６
２００」で測定したヘイズレベルで１．５ｐｐｍ、ＡＦ
Ｍで測定したＰ−Ｖ値で５ｎｍ程度であった。しかしな
がら、この発明にあっては、不純物拡散後に、拡散面に
対して高精度の仕上げ研磨を施す。このため、ウェーハ
表面の粗さが、「ＳＦＳ６２００」でのヘイズレベルで
０．２ｐｐｍ以下、ＡＦＭによるＰ−Ｖ値で２ｎｍ以下
まで低減された、マイクロラフネスの低いシリコンウェ
ーハが得られる。In the manufacturing process of a bonded silicon wafer, the surface is usually roughened by diffusing impurities into the bonded surface of the silicon wafer. The roughness of the wafer surface can be measured by, for example, “SFS6” of Tencor Corporation.
1.5 ppm at haze level measured at 200 ", AF
The PV value measured by M was about 5 nm. However, in the present invention, after the impurity diffusion, a highly accurate finish polishing is performed on the diffusion surface. Therefore, a silicon wafer with low micro roughness can be obtained in which the roughness of the wafer surface is reduced to 0.2 ppm or less in the haze level of “SFS6200” and 2 nm or less in PV value by AFM.
【００１４】上記従来技術の欄で説明したように、ウェ
ーハ間の接合力はウェーハ表面のマイクロラフネスが大
きく関与するので、この発明によれば、２枚のシリコン
ウェーハ同士を張り合わせたときに、ウェーハ間に未接
合部分（ボイド）を発生させず、より大きなウェーハ接
合強度が得られる。したがって、ユーザーによる例えば
ＬＳＩの製造工程でのシリコンウェーハの剥がれを原因
とした不良品の発生を低減することができる。ここで、
図１および図２のグラフを参照して、この発明をより具
体的に説明する。As described in the section of the prior art, since the bonding strength between wafers is greatly affected by the micro roughness of the wafer surface, according to the present invention, when two silicon wafers are bonded together, An unbonded portion (void) is not generated therebetween, and higher wafer bonding strength can be obtained. Therefore, it is possible to reduce the occurrence of defective products caused by peeling of the silicon wafer in the LSI manufacturing process, for example, by the user. here,
The present invention will be described more specifically with reference to the graphs of FIGS.
【００１５】図１は、各種シリコンウェーハのＰ−Ｖ値
を基準にした比較を示すグラフである。また、図２は、
各種シリコンウェーハのヘイズ値を基準にした比較を示
すグラフである。 （１）シリコンウェーハに例えば不純物であるＳｂが高
濃度に拡散され（例えば２０〜３０Ω／□）、かつ機械
的化学的研磨である仕上げ研磨を施していない従来のａ
ｓ拡散ウェーハと、（２）同じくＳｂが拡散され、かつ
仕上げ研磨を施したこの発明と、（３）Ｓｂ拡散なしの
一般的な鏡面シリコンウェーハとを、シリコンウェーハ
の張り合わせ面のＰ−Ｖ値およびヘイズ値について比較
する。図１、図２のグラフから明らかなように、仕上げ
研磨を行わない従来手段に比べて、仕上げ研磨を行うこ
の発明のものは、Ｓｂ拡散がない手段のものとほぼ同程
度の低さだった。FIG. 1 is a graph showing a comparison based on PV values of various silicon wafers. Also, FIG.
4 is a graph showing a comparison based on haze values of various silicon wafers. (1) The conventional a, in which Sb, which is an impurity, for example, is diffused in a silicon wafer at a high concentration (for example, 20 to 30 Ω / □), and is not subjected to finish polishing, which is mechanical and chemical polishing.
The S-diffusion wafer, (2) the present invention in which Sb is also diffused and finish polished, and (3) a general mirror-surface silicon wafer without Sb diffusion, the PV value of the bonding surface of the silicon wafer And the haze value. As is clear from the graphs of FIGS. 1 and 2, compared with the conventional means which does not perform the finish polishing, the present invention which performs the finish polishing is almost as low as the means which does not have the Sb diffusion. .
【００１６】また、図３の各種シリコンウェーハの接合
強度を示すグラフから明らかなように、その後、（１）
および（２）の場合について、この仕上げ研磨された２
枚のシリコンウェーハを、室温大気中において張り合わ
せ面同士を重ね合わせて張り合わせた。接合強度の測定
は、以下のようにして行った。張り合わせウェーハの一
部を劈開し、ＨＦに浸漬し、埋め込み酸化膜（張り合わ
せ界面）への染み込み量を測定することによった。一定
時間での染み込み量の大小で判定した。張り合わせ後の
シリコンウェーハ間の接合強度は、（１）のａｓ拡散ウ
ェーハによる張り合わせシリコン基板に比べて、（２）
の仕上げ研磨を施したこの発明の張り合わせシリコン基
板の方が約５倍に増大した。シリコンウェーハの張り合
わせ面に、研磨量が０．１μｍ未満で仕上げ研磨を施す
ので、ウェーハ表面の粗さを不純物拡散なしの鏡面研磨
ウェーハと同等程度にまで低減でき、これによりウェー
ハ接合強度をさらに増大できる。Further, as is clear from the graph showing the bonding strength of various silicon wafers in FIG.
And for case (2), this finished polished 2
Two silicon wafers were bonded together in a room-temperature atmosphere with their bonding surfaces overlapped. The measurement of the bonding strength was performed as follows. A part of the bonded wafer was cleaved, immersed in HF, and the amount of penetration into a buried oxide film (bonded interface) was measured. Judgment was made based on the magnitude of the permeation amount over a certain period of time. The bonding strength between the bonded silicon wafers is (2) as compared with the bonded silicon substrate using the as diffusion wafer of (1).
The bonded silicon substrate of the present invention, which has been subjected to the finish polishing described above, has increased about five times. Finish polishing is performed on the bonded surface of the silicon wafer with a polishing amount of less than 0.1 μm, so that the surface roughness of the wafer can be reduced to the same level as a mirror-polished wafer without impurity diffusion, thereby further increasing the wafer bonding strength it can.
【００１７】特に、請求項２、請求項４に記載の発明の
場合には、この仕上げ研磨面のマイクロラフネスをヘイ
ズレベルで０．５ｐｐｍ以下またはＰ−Ｖ値で４ｎｍ以
下としたので、これによりウェーハ接合強度をより大き
くすることができる。In particular, in the case of the second and fourth aspects of the present invention, the micro-roughness of the finished polished surface is 0.5 ppm or less at a haze level or 4 nm or less at a PV value. The wafer bonding strength can be further increased.
【００１８】さらに、請求項３に記載の発明の場合に
は、シリコンウェーハが、ベアウェーハであっても、そ
の張り合わせ面の最終的な研磨工程が、研磨量０．１μ
ｍ未満という表面基準の研磨である仕上げ研磨であるの
で、ウェーハ表面の粗さが、ヘイズレベルで０．５ｐｐ
ｍ以下、Ｐ−Ｖ値で４ｎｍ以下まで低減される。また、
表面にＳｉＯ2膜を有するウェーハでも、Ｐ−Ｖ値で４
ｎｍ以下まで低減される。これにより、いずれのシリコ
ンウェーハの品種であっても、ウェーハ接合強度を大き
くすることができる。Further, in the case of the invention described in claim 3, even if the silicon wafer is a bare wafer, the final polishing step of the bonded surface requires a polishing amount of 0.1 μm.
m, so that the surface roughness of the wafer is 0.5 pp at the haze level.
m or less, and the PV value is reduced to 4 nm or less. Also,
Even a wafer having a SiO 2 film on its surface has a PV value of 4
nm or less. This makes it possible to increase the wafer bonding strength regardless of the type of silicon wafer.
【００１９】[0019]
【発明の実施の形態】以下にこの発明の実施例を挙げて
この発明をより具体的に説明する。ただし、この発明は
これに限定されないのはいうまでもない。 〈実施例１、比較例１〉実施例１として、表面にＳｂが
高濃度に拡散され、ＡＦＭ測定での表面粗さＰ−Ｖ値が
５ｎｍ、「ＳＦＳ６２００」のヘイズ値が１．５ｐｐｍ
のシリコンウェーハを、ウェーハ保持テーブル上に載置
する。なお、シリコンウェーハ表面に拡散されたＳｂに
よる抵抗値は、例えば２０〜３０Ω／□とする。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described more specifically with reference to examples of the present invention. However, it goes without saying that the present invention is not limited to this. <Example 1, Comparative Example 1> In Example 1, Sb was diffused at a high concentration on the surface, the surface roughness PV value by AFM measurement was 5 nm, and the haze value of "SFS6200" was 1.5 ppm.
Is placed on the wafer holding table. The resistance value of Sb diffused on the surface of the silicon wafer is, for example, 20 to 30 Ω / □.
【００２０】このシリコンウェーハを、バックパッドを
用いた表面基準研磨方式で、その張り合わせ面を研磨量
０．１μｍだけ仕上げ研磨を施した。張り合わせ面のＰ
−Ｖ値は２ｎｍ、ヘイズ値は０．２ｐｐｍとなった。ま
た、比較例１として仕上げ研磨を施していない場合を示
す。そして、これらのシリコンウェーハを同一条件でそ
れぞれ張り合わせ、熱処理を施した。その結果製造され
た張り合わせ基板について、それぞれ、上記エッチング
液の浸食による接合強度の測定を行った。その結果を表
１に示す。The bonded surface of the silicon wafer was subjected to finish polishing by a polishing amount of 0.1 μm by a surface reference polishing method using a back pad. P of bonding surface
The -V value was 2 nm, and the haze value was 0.2 ppm. Comparative Example 1 shows a case where finish polishing is not performed. Then, these silicon wafers were bonded to each other under the same conditions, and subjected to a heat treatment. With respect to the bonded substrates manufactured as a result, the bonding strength due to the erosion of the etching solution was measured. Table 1 shows the results.
【００２１】[0021]
【表１】 [Table 1]
【００２２】表１から明らかなように、実施例１の張り
合わせシリコン基板は、不純物の拡散により表面が粗く
なったシリコンウェーハの張り合わせ面を、その後、さ
らに高精度の機械的化学的研磨である仕上げ研磨を施し
て平滑化するようにしたので、高濃度の不純物が拡散さ
れたシリコンウェーハであっても、不純物の拡散がない
シリコンウェーハの場合と同等の表面粗さとなった。こ
れにより接合強度が増大し、よって製品出荷後、ユーザ
ーが例えばＬＳＩを製造する際に、張り合わされたシリ
コンウェーハが取り扱い中に剥がれて、不良品が発生す
る虞れが低減できた。これに対して、比較例１の仕上げ
研磨を施していない張り合わせシリコン基板の場合に
は、シリコンウェーハの張り合わせ面の表面粗さがＰ−
Ｖ値およびヘイズ値とも比較的に大きい。これにより接
合強度が小さくなり、したがってユーザー取り扱い時
に、シリコンウェーハが剥がれて不良品となる率が比較
的高い。As can be seen from Table 1, the bonded silicon substrate of Example 1 finishes the bonded surface of the silicon wafer whose surface has been roughened by the diffusion of impurities, and thereafter, is subjected to higher precision mechanical chemical polishing. Since the surface was polished and smoothed, even a silicon wafer in which a high-concentration impurity was diffused had a surface roughness equivalent to that of a silicon wafer in which no impurity was diffused. As a result, the bonding strength is increased, and thus, when the user manufactures an LSI, for example, after shipping the product, the possibility that the bonded silicon wafer is peeled off during handling and a defective product can be reduced. On the other hand, in the case of the bonded silicon substrate not subjected to the final polishing in Comparative Example 1, the surface roughness of the bonded surface of the silicon wafer is P-
Both the V value and the haze value are relatively large. As a result, the bonding strength is reduced, and the rate at which the silicon wafer is peeled off and becomes a defective product during handling by the user is relatively high.
【００２３】[0023]
【発明の効果】以上説明してきたように、この発明の張
り合わせシリコン基板およびその製造方法は、張り合わ
されるシリコンウェーハの作製工程において、不純物の
拡散により粗くなった張り合わせ面を、研磨量０．１μ
ｍ未満の仕上げ研磨を施すようにしたので、ウェーハ表
面の粗さが低減して、マイクロラフネスの高いシリコン
ウェーハが得られる。これにより、ウェーハ張り合わせ
強度の増大が図れ、したがってユーザーによる例えばＬ
ＳＩの製造工程でのシリコンウェーハの剥がれに起因し
た不良品の発生を低減できる。As described above, the bonded silicon substrate and the method of manufacturing the same according to the present invention, in the manufacturing process of the bonded silicon wafer, remove the bonded surface roughened by diffusion of impurities by a polishing amount of 0.1 μm.
Since the final polishing of less than m is performed, the roughness of the wafer surface is reduced, and a silicon wafer with high micro roughness is obtained. As a result, the wafer bonding strength can be increased.
It is possible to reduce the occurrence of defective products due to peeling of the silicon wafer in the SI manufacturing process.
【図１】この発明の一実施例に係る張り合わせシリコン
ウェーハのＰ−Ｖ値を他の張り合わせウェーハと比較し
て示すグラフである。FIG. 1 is a graph showing a PV value of a bonded silicon wafer according to one embodiment of the present invention in comparison with other bonded wafers.
【図２】この発明の一実施例に係る張り合わせシリコン
ウェーハのヘイズ値を他の張り合わせウェーハと比較し
て示すグラフである。FIG. 2 is a graph showing a haze value of a bonded silicon wafer according to one embodiment of the present invention in comparison with other bonded wafers.
【図３】この発明の一実施例に係る張り合わせシリコン
ウェーハの接合強度を他の張り合わせウェーハと比較し
て示すグラフである。FIG. 3 is a graph showing the bonding strength of a bonded silicon wafer according to one embodiment of the present invention as compared with other bonded wafers.
Claims (4)
枚のシリコンウェーハ同士を張り合わせた張り合わせシ
リコン基板において、 上記２枚のシリコンウェーハの少なくとも一方のシリコ
ンウェーハの張り合わせ面に、不純物を拡散した後、研
磨量が０．１μｍ未満の仕上げ研磨が施され、この研磨
面を残りの他方のシリコンウェーハの張り合わせ面に重
ね合わせることにより張り合わされた張り合わせシリコ
ン基板。1. A mirror-finished bonded surface 2
In a bonded silicon substrate in which two silicon wafers are bonded to each other, a bonding surface of at least one of the two silicon wafers is diffused with impurities, and then a final polishing with a polishing amount of less than 0.1 μm is performed. A bonded silicon substrate bonded by laminating the polished surface to the bonded surface of the other silicon wafer.
ルで０．５ｐｐｍ以下またはＰ−Ｖ値で４ｎｍ以下とす
る研磨である請求項１に記載の張り合わせシリコン基
板。2. The bonded silicon substrate according to claim 1, wherein the finish polishing is a polishing in which a polished surface is 0.5 ppm or less in haze level or 4 nm or less in PV value.
た張り合わせ面に不純物を拡散する工程と、 この不純物拡散後の張り合わせ面に研磨量が０．１μｍ
未満の仕上げ研磨を施す工程と、 この仕上げ研磨面を第２のシリコンウェーハの張り合わ
せ面に重ね合わせることにより、張り合わせシリコン基
板を製造する張り合わせ工程と、を備えた張り合わせシ
リコン基板の製造方法。3. A step of diffusing an impurity into the mirror-polished bonding surface of the first silicon wafer, and a step of polishing the bonding surface after the impurity diffusion to a polishing amount of 0.1 μm.
A method for manufacturing a bonded silicon substrate, comprising: a step of performing less than a final polishing; and a bonding step of manufacturing a bonded silicon substrate by overlapping the final polished surface with a bonding surface of the second silicon wafer.
レベルで０．５ｐｐｍ以下またはＰ−Ｖ値で４ｎｍ以下
とする研磨である請求項３に記載の張り合わせシリコン
基板の製造方法。4. The method for manufacturing a bonded silicon substrate according to claim 3, wherein the final polishing is a polishing in which the polished surface is 0.5 ppm or less in haze level or 4 nm or less in PV value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06186597A JP3604026B2 (en) | 1997-02-27 | 1997-02-27 | Manufacturing method of bonded silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06186597A JP3604026B2 (en) | 1997-02-27 | 1997-02-27 | Manufacturing method of bonded silicon substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10242015A true JPH10242015A (en) | 1998-09-11 |
| JP3604026B2 JP3604026B2 (en) | 2004-12-22 |
Family
ID=13183453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06186597A Expired - Fee Related JP3604026B2 (en) | 1997-02-27 | 1997-02-27 | Manufacturing method of bonded silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3604026B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004021433A1 (en) * | 2002-08-27 | 2004-03-11 | Shin-Etsu Handotai Co.,Ltd. | Method for manufacturing soi wafer |
| JP2008263010A (en) * | 2007-04-11 | 2008-10-30 | Shin Etsu Chem Co Ltd | Method for manufacturing soi substrate |
| JP5223998B2 (en) * | 2010-11-29 | 2013-06-26 | 大日本印刷株式会社 | Evaluation board |
| JP2014013898A (en) * | 2000-02-16 | 2014-01-23 | Ziptronix Inc | Low temperature bonding method and bonding constituent |
-
1997
- 1997-02-27 JP JP06186597A patent/JP3604026B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014013898A (en) * | 2000-02-16 | 2014-01-23 | Ziptronix Inc | Low temperature bonding method and bonding constituent |
| WO2004021433A1 (en) * | 2002-08-27 | 2004-03-11 | Shin-Etsu Handotai Co.,Ltd. | Method for manufacturing soi wafer |
| JP2008263010A (en) * | 2007-04-11 | 2008-10-30 | Shin Etsu Chem Co Ltd | Method for manufacturing soi substrate |
| JP5223998B2 (en) * | 2010-11-29 | 2013-06-26 | 大日本印刷株式会社 | Evaluation board |
| US9176073B2 (en) | 2010-11-29 | 2015-11-03 | Dai Nippon Printing Co., Ltd. | Evaluation substrate, defect examination method and defect detection device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3604026B2 (en) | 2004-12-22 |
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