JPH1023368A - Video reproducing device and base band memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video reproducing device for operating a field exchanging processing, and operating proper video data reproduction corresponding to a demanded arbitrary reproducing speed and arbitrary reproducing direction. SOLUTION: Each frame of inputted video data is alternately recorded in a bank A and a bank B constituted of a first frame memory 21 and a second frame memory 22 in a base band memory part 18. At that time, the first field is recorded in an even field area, and the second field is recorded in an odd field area. At the time of variable speed reproduction at ×1/2 variable speed, the odd field areas are continuously read twice, and then the odd field areas are continuously read twice based on a field operational sequence recorded in an RAM 33. Thus, output video data in which the same frames are continued by two each, and the fields are lined up like the even field/even field/odd field/ odd field can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video reproducing apparatus capable of appropriately performing arbitrary variable-speed reproduction, and a baseband memory apparatus capable of easily exchanging fields when performing such variable-speed reproducing.

[0002]

2. Description of the Related Art Advances in image processing technology and digital processing technology have made it possible to compress video data without significant deterioration in image quality, and to record such video data on a randomly accessible recording medium to meet demands. AV server devices and the like that can be easily reproduced in response thereto are being put into practical use. By using such an AV server device, it is possible to easily reproduce an arbitrary video portion immediately or to perform various advanced image processing.

[0003] If a digital video processing device such as an AV server device is used, processing of video data in image units is facilitated, so that variable speed reproduction and reverse reproduction of video data can be easily performed. it is conceivable that. For example, when reproducing at 1/2 times, the same frame may be reproduced or output twice, and when reproducing at the opposite direction, video data is recorded at random access. Since this is a simple recording medium, the order of frames to be read may be simply changed.

However, in such simple variable speed reproduction and reverse reproduction, the image quality may be deteriorated. NTSC
In the case of the video data of the system, one frame is composed of two fields. First, an even field is reproduced, then an odd field is reproduced, and one frame is reproduced. In such a case, if one frame is simply played twice in an attempt to play back at 1/2 times,
The video is reproduced in the order of (even field)-(odd field)-(even field)-(odd field), and the (odd field) of the same frame is reproduced.
The video may be reproduced in the order of (even field). In this state, reproduction is performed in the reverse direction in terms of time, which causes a visual problem. That is, the image quality of the reproduced image is degraded.

[0005] Further, even when the data is reproduced in the reverse direction,
Even if the image is played back backward in frame units, the image is played back in the order of (even field)-(odd field) within each frame, so that an image which is purely reversed cannot be obtained. , Proper reverse playback is not possible. Therefore, in order to appropriately perform such variable-speed reproduction or reproduction in the reverse direction, it is necessary to exchange fields.

[0006]

However, such a field exchange process needs to be performed appropriately in accordance with reproduction conditions such as a reproduction speed and a reproduction direction. There is a problem that a field exchange means is required according to the reproduction direction, and the configuration of the apparatus becomes complicated. In addition, there is a problem that, in order to adapt to new reproduction conditions, it is necessary to add a field exchange means for that.

Accordingly, an object of the present invention is to provide a video reproducing apparatus which appropriately performs field exchange processing and reproduces appropriate video data in accordance with a required arbitrary reproducing speed and an arbitrary reproducing direction. To provide. Also,
Another object of the present invention is to provide a baseband memory device that is a memory device that can easily exchange fields of video data in accordance with various conditions.

[0008]

In order to solve the above problem, video data is temporarily stored in a plurality of frame memories,
Arbitrary fields of the frame memory can be selectively output. Furthermore, as a method of the selection,
A selection procedure corresponding to the playback condition to be handled is recorded in a table format in advance, and the output data is switched based on the table by a control unit such as a processor.

Therefore, the video reproducing apparatus of the present invention has a recording means for recording compression-encoded video data, and reproduces and decodes the recorded video data to obtain video data for each frame. Playback means for generating a sequence of video data for each frame corresponding to the playback speed of the frame, and temporarily storing the generated sequence of video data for each frame in a frame memory, and storing the recorded video data in a field. Baseband memory means for generating reproduced video data of a desired reproduction speed and reproduction direction by selectively reading the data in units.

More specifically, the baseband memory means includes a plurality of frame memories each divided into a plurality of areas for storing video data for each field, and a plurality of video data for each of the generated and input frames. Input switching means for sequentially and cyclically inputting the video data to the plurality of frame memories, and video data for each of the fields of the plurality of frame memories so that video data is reproduced at a desired reproduction speed in a desired reproduction direction. Output selection means for selectively reading out the stored plurality of areas. More specifically, the output selecting means includes an output switching means for selecting and outputting video data for each field stored in any one of the divided areas of the plurality of frame memories, A switching rule storing means for storing switching rules of the output switching means in a table format so that video data of an appropriate field is appropriately output based on the direction and the reproduction speed; And control means for controlling the output switching means based on the

More specifically, the switching rule storage means further stores a switching rule of the input switching means based on a reproduction direction and a reproduction speed in a table format, and the control means stores the switching rule stored in the table. The output switching means and the input switching means are controlled based on Preferably, the switching rule storage unit stores the switching rule in a format that can be updated as appropriate.

Further, the baseband memory device of the present invention is divided into a plurality of areas for storing video data for each field, and a plurality of frame memories for storing video data for each frame; An input switching unit for selecting and inputting and storing a data string by selecting one of the plurality of frame memories; and selecting one of the divided regions of the plurality of frame memories and selecting one of the divided regions. Output switching means for reading and outputting the stored video data for each field; and outputting the video data based on the reproduction direction and the reproduction speed such that appropriate video data is output in accordance with a desired reproduction direction and reproduction speed. Rules for selecting a frame memory for storing video data input by the input switching means, and selecting and outputting by the output switching means The selection rule of the video data, a selection rule storing means for storing in a table format, based on a selection rule that is the storage, and control means for controlling the input switching means and said output switching means.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an AV data recording / reproducing apparatus according to one embodiment of the video reproducing apparatus of the present invention using the baseband memory device of the present invention.
The AV data recording / reproducing apparatus 1 includes a D1 decoder 11, a compression circuit 12, an input switch 13, a memory unit 14, a hard disk unit 15, an output switch 16, an expansion circuit 1.
7, baseband memory unit 18 and D1 encoder 1
9

In the AV data recording / reproducing apparatus 1, D
A video signal input in one format is decoded by a D1 decoder 11 to generate a baseband video signal, and is compressed and recorded by a compression circuit 12 according to a predetermined compression encoding method.

The recording section for actually recording video data has a memory section 14 for temporarily storing input / output video data and a hard disk section 15. The memory unit 14 and the hard disk unit 15 are respectively composed of four memories 14 _{-1 to} 14 _-4 and hard disks 15 _-1 to 15 _-4 , which are associated with each other to form one recording system. ing. And the input changeover switch 13 is
The video data compressed by the compression circuit 12 is sequentially input to four recording systems. The input video data is temporarily stored in the memory 14 _-i (i = 1 to 4) of each recording system and then stored in the corresponding hard disk 15 _-i . In the AV data recording / reproducing apparatus 1, the memory 14 _{-1 is} thus used.
By performing substantially parallel conversion of the data using the -14 _-4 as a buffer, the access speed of the hard disk 15 _-i for the input rate of the video data inputted from the compression circuit 12 is covered slowness .

Similarly, when reproducing the video data stored in the hard disk unit 15, the four hard disks 1
The video data is read in parallel from 5 _-1 to 15 _-4 and temporarily stored in the memories 14 _{-1 to} 14 _-4 . Then, the output changeover switch 16 sequentially selects the data stored in the four memories 14 _{-1 to} 14 _-4 and outputs the data as one piece of reproduced video data. At this time, the memory unit 14, the hard disk unit 15, and the output changeover switch 16 are controlled based on a control signal from a control unit (not shown) to obtain a required reproduction speed,
The recorded video data is read and output so that the video data can be reproduced in the reproduction direction. That is, in the case of normal real-time reproduction, data transfer and data selection by the output switch 16 are performed so that output can be performed at a normal speed. For example, when reproduction at 1/2 speed is required, the transfer rate from the hard disk unit 15 is substantially reduced and output. When reverse playback is required, the video data is played back in such an order.

The compressed video data selected and output by the output changeover switch 16 is decompressed by a decompression circuit 17,
Baseband video data is generated. The generated video data is input to the baseband memory unit 18 and a field exchange process is performed so as to be appropriate as reproduced video data. The configuration and operation of the baseband memory unit 18 will be described later. Then, the obtained reproduced video data is again converted into the D1 format by the D1 encoder 19 and output.

Next, the baseband memory section 18 will be described in detail. FIG. 2 shows the baseband memory unit 1
8 is a block diagram showing the configuration of FIG. The baseband memory unit 18 includes a first frame memory 21, a second frame memory 22, first to seventh changeover switches Sw1 to Sw
7, input signal switching circuit 30, output signal switching circuit 31, R
It has an OM 32, a RAM 33, a PIO 34, and a CPU 35.

First, the configuration of each unit will be described. First
Frame memory 21 and second frame memory 22
Is a memory for storing baseband image data for one frame each, a first area for storing a first field (even field) in each frame, and a second field (odd field) for each frame. ) And a second area for storing the same. Hereinafter, the first frame memory 21 will be referred to as bank A, and the second frame memory 22
Are referred to as a bank B, the first area is called an even field area, and the second area is called an odd field area.

First to fourth changeover switches Sw1 to Sw4
Is a switch for selecting in which area of the first frame memory 21 and the second frame memory 22 the input video data Pin is to be input and stored. First
Of the second switch Sw1 in response to the switching signal SC- ₁ output from the input signal switching circuit 30.
2 is switched by a switching signal SC- ₂ , and the third and fourth switching switches Sw3 and Sw4 are switched by a switching signal SC- ₃ . Further, fifth to seventh changeover switches Sw5 to Sw7
Is a switch for selecting in which area of the first frame memory 21 and the second frame memory 22 the video data for each field is output as the video data Pout to be output. The fifth and sixth changeover switches Sw5 and Sw6 are connected to the output signal changeover circuit 3
The seventh changeover switch Sw7 is switched by the changeover signal SC- _{7 in} response to the changeover signal SC- ₅ output from No. 1.

The input signal switching circuit 30 includes a CPU
Control signal SCin inputted from PIO 35 through PIO 34
When the video data Pin of one frame (two fields) to be input next is input to the first frame memory 21 or the second frame memory 22,
It generates switching signals SC _{-1 to} SC _-3 to be applied to the fourth changeover switches Sw1 to Sw4. At that time, in the input signal switching circuit 30, the clock signal CLK, the VD signal VD and the frame pulse signal FP input from the outside are input.
Determines the switching timing. This switching timing will be described later.

The input control signal SCin in the input signal switching circuit 30 and the generated switching signals SC _{-1 to} SC _-1 .
FIG. 3 shows the relationship of _-3 . As shown in FIG. 3, the control signal S
Cin is composed of four control lines. The control line No. 1 controls the first changeover switch Sw1, and when this is at L, the first changeover switch Sw1 is open and the input video data is not written anywhere. The control line No. 2 controls the second changeover switch Sw2. When this switch is L, the video data input to the bank A is written. When it is H, the video data input to the bank B is written. The control lines Nos. 3 and 4 control the areas for recording the video data of the two fields of the next frame by their combination as shown in FIG. Thus, for example, the control signal SCin
The signal “HLLH” is input to the input signal switching circuit 3.
When it is input to 0, the input signal switching circuit 30 turns on the switching switch Sw1, switches the switching switch Sw2 so that data is input to the bank A, and switches the switching switch Sw3 and the switching switch Sw4. The first field is switched to be input to the even area, and the second field is switched to be input to the odd area.

Similarly, the output signal switching circuit 31
5 from the control signal SCout input via the PIO 34
, The fifth to seventh changeover switches Sw5 to Sw7
Generating a switching signal SC _-5, SC _-7 applied to, select the video data of a predetermined area of the first frame memory 21 or the second frame memory 22, the next one frame (two fields) Output video data Pout. At that time, the output signal switching circuit 31 also determines the switching timing based on the clock signal CLK, VD signal VD, and frame pulse signal FP input from the outside. This switching timing will be described later.

In the output signal switching circuit 31, the input control signal SCout and the generated switching signals SC _-5 and S
FIG. 4 shows the relationship of C _-7 . As shown in FIG. 4, the control signal SCout is composed of three control lines. The control line No. 1 controls the seventh changeover switch Sw7. When this switch is L, the video data stored in the bank A is read, and when it is H, the video data stored in the bank B is read. The control lines Nos. 2 and 3 control the output of the video data of the two fields of the next frame by their combination as shown in FIG. Thus, for example, as the control signal SCout, "
When the signal “LHL” is input to the output signal switching circuit 31, the output signal switching circuit 31
w7 is switched to output data to the bank A, and the changeover switches Sw5 and Sw6 are
The first field outputs the data of the odd area, and the second field
The field is switched so that the data of the odd number area is output.

The ROM 32 is a read-only memory in which an operation program of the CPU 35 is recorded.

The RAM 33 is a memory for storing a field operation procedure referred to by the CPU 35 at the time of a field exchange process of video data. In the present embodiment, a table indicating a field operation procedure as shown in FIG. 5 is recorded in the RAM 33, and the CPU 35 operates according to this table.

Here, the contents of the table shown in FIG. 5 will be described. This table stores a field operation procedure for each playback speed that the baseband memory unit 18 can support. In the example shown in FIG. 5, field operation procedures related to × 1 normal reproduction, × 1/2 speed reproduction, and × −1 / 2 speed reverse reproduction are stored. For example, in the case of normal reproduction of × 1, in the first frame, the procedure in which the frame number is written at 1 is followed.
That is, the input video data is written to the even field area of the bank B in the first field and to the odd field area of the bank B in the second field.

Output video data is obtained by reading data stored in the even field area of bank A as the first field and reading data stored in the odd field area of bank B as the second field. Then, in the next frame, the frame number is 2
Repeat the procedure described in the section. In the case of this normal reproduction, since the frame period FT is 2, the operation of these two frames may be repeated. For 1/2 × speed reproduction of × １ ／ and 1/2 × reverse reproduction of × − ／, it is sufficient to operate according to the procedure shown in FIG.

The PIO (parallel I / O) 34 is a CPU
This is a general-purpose parallel I / O interface connected to the bus. In the present embodiment, in particular, the CPU 35 supplies the input signal switching circuit 30 and the output signal switching circuit 31 with the output of the control signals SCin and SCout for switching. Used for

The CPU 35 operates the baseband memory unit 1 so that appropriate reproduced video data according to the request is output.
8 is a processor that controls each unit, and is configured by a general-purpose microcomputer, a DSP, or the like. The CPU 35 is a ROM
It operates in accordance with the program stored in 32. Also, from a control unit (not shown) of the AV data recording / reproducing apparatus 1,
A control signal for the reproduction speed of the video signal is input via a serial interface (not shown) in the baseband memory unit 18, and the field operation processing is selected according to the control signal. Further, a frame pulse signal FP is input to the CPU 35 as an interrupt signal as a signal for knowing the timing when performing the field operation.

The operation of the CPU 35 relating to the field operation will be described with reference to the flowchart of FIG. When video data is input, the serial I
A reproduction speed control signal input via the / F is read (step S1). Next, a field operation procedure corresponding to the read reproduction speed is read from the RAM 33 (step S2). Then, a variable FN for counting the frame number of the operation procedure is set to 1 (step S3), and waits for the input of the frame pulse FP (step S4). When the frame pulse FP is input, an operation for the next frame is determined according to the operation procedure read in step S2, and the control signal is transmitted to the PIO.
The signal is output to the input signal switching circuit 30 and the output signal switching circuit 31 via the switch 34 (step S5).

Then, the current frame number FN is compared with the frame period FT of the processing procedure of the reproduction speed (step S6). If the frame number FN is equal to the frame period FT, one cycle of the field operation procedure relating to the reproduction speed has been completed, so the frame number FN is returned to 1 again (step S3), and the field operation procedure is performed. repeat. If the frame number FN is not equal to the frame period FT in step S6, it is still in the middle of the field operation procedure, so the frame number FN
Is incremented by 1 (step S7), and processing for the next frame in the field operation procedure is performed. That is, the processing from step S4 is repeated.

The CPU 35 outputs the frame pulse signal F
The reason for setting the field operation control signal of the next frame instead of the current frame after the detection of P is that the CPU 35 detects the frame boundary, reads the field replacement procedure from the RAM 33, and operates the program for setting data in the PIO 34. Therefore, the input signal switching circuit 3
0 and the control signals SCin, SC
Out arrives because it takes a long time for these programs to operate from the boundary of the frame, and it is highly likely that the program is in the middle of the current frame. Therefore, the timing at which the switching signal is applied to each of the changeover switches Sw1 to Sw7 is different from the timing at which the CPU 35 outputs the control signal.

Next, the timing of each signal related to the field operation will be described with reference to FIG. When the frame pulse signal FP as shown in FIG. 7B input from the outside is detected, the input signal switching circuit 30 and the output signal switching circuit 31 have already passed through the PIO 34 as shown in FIG. Latches the field operation control signals SCin and SCout that have been input. Then, the switching signals SC _{-1 to} SC _{-7 of the} changeover switches Sw1 to Sw7 based on the latched SCin and SCout are output as shown in FIG. As a result, the first, second and seventh changeover switches Sw1, Sw2, SW7
Are switched as shown in FIG. 7D, and the third to sixth changeover switches Sw3 to Sw6 are switched as shown in FIG. 7C.

Then, the video data of 256 lines from the 10th line is recorded in the selected memory as the video data of the first field (even field), or is output from the selected memory. When the first field is completed, as shown in FIG. 7C, the third to sixth changeover switches Sw3 to Sw6 related to the switching of the areas of the first frame memory 21 and the second frame memory 22 are switched. Can be Then, the video data of 256 lines from the 273rd line is again recorded as the video data of the second field (odd field) in the selected memory, or is output from the selected memory. The timing of these 10th line and 273th line is
This can be detected by looking at the rising edge of the VD signal VD shown in FIG. Eight clocks after the rise of the VD signal VD is the beginning of the tenth line and the 273th line.

While the processing for a certain frame is being performed, the CPU 35 reads out the field replacement procedure from the RAM 33 based on the detection of the frame pulse signal FP and determines the field operation for the next frame. The control signal is sent to the input signal switching circuit 30 and the output signal switching circuit 3 via the PIO 34.
Apply to 1. This control signal is latched by the next frame pulse signal FP, becomes valid, and the processing for the next frame is sequentially performed.

Next, a specific operation of the baseband memory section 18 will be described with reference to FIGS. FIGS. 8A and 8B are diagrams showing input / output data of the baseband memory unit 18 at the time of performing a 1/2 speed change reproduction. FIG. 8A is a diagram showing video data for each input frame, and FIG. FIG. 4C shows a frame read / written to / from bank A, FIG. 5C shows an area read / written to / from bank A, FIG. 5D shows a frame read / written to / from bank B, and FIG. (E) is a diagram showing video data for each output frame.

As shown in FIG. 8A, in the case of x1 / 2 variable speed reproduction, two identical frames are input. In the baseband memory section 18, FIGS.
As shown in FIG. 7, the video data of the first frame that overlaps are alternately recorded in banks A and B. At this time, the first field is in the even field area,
Field is recorded in an odd field area. Then, at the time of reading, as shown in FIGS. 8C and 8E, the even field area is read twice consecutively, and then the odd field area is read twice consecutively. As a result, as shown in FIG. 8E, the same frame continues two by two, and the field is (even field)-(even field)-(odd field)-(odd field)
Is obtained.

FIG. 9 is a diagram showing input / output data of the baseband memory unit 18 when performing a x-1 / 2 variable speed reproduction. Also in this case, the processing is performed in the same manner as in the case of the variable speed reproduction of × 1/2 shown in FIG. That is, in this case, the output video data is controlled so as to be read in the order of (odd field)-(odd field)-(even field)-(even field).

FIG. 10 is a diagram showing input / output data of the baseband memory unit 18 in the case of performing x1 reproduction, that is, normal reproduction. When performing normal reproduction, the baseband memory unit 18 is not required, but by treating normal reproduction as one of variable-speed reproduction, it is not necessary to add a circuit dedicated to normal reproduction. Further, the delay from the input of a frame to the output of the frame can be constant (one frame in the case of the present embodiment). In the case of normal reproduction, as shown in FIG. 10, the banks A and B may be read and written alternately, and there is no need to exchange fields.

As described above, in the present embodiment, by controlling the method of switching banks and the order of reading fields, the baseband memory unit 18 can be stored in the baseband memory unit 18 without the need for a circuit corresponding to each reproduction speed. Can be built. Also, when a new variable-speed reproduction is to be supported, it can be easily coped with only by adding a table of the field processing procedure, that is, only by performing software processing.

[0042]

As described above, according to the video reproducing apparatus of the present invention, it is possible to cope with an arbitrary required reproducing speed and an arbitrary reproducing direction and to appropriately perform a field exchange process. Video data can be reproduced. Further, according to the baseband memory device of the present invention, it is possible to generate video data arranged in an appropriate order on a field-by-field basis from input video data for each frame. Therefore, when the present invention is applied to a video reproducing apparatus, it is possible to provide a device that outputs reproduced video data corresponding to a request for various reproduction conditions as described above. In addition, the present invention is applied to any video processing device that requires input of video data under desired conditions or is required to output video data under desired conditions, thereby simplifying the configuration of the device and increasing versatility. Enhance the processing performance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an AV data recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a baseband memory unit of the AV data recording / reproducing apparatus shown in FIG.

FIG. 3 shows a control signal SCin and a switching signal SC _{-1 in} the input signal switching circuit of the baseband memory unit shown in FIG.
It is a figure which shows the relationship of -SC- ₃ .

4 shows a control signal SCout and a switching signal SC in an output signal switching circuit of the baseband memory unit shown in FIG. 2;
FIG. ₅ is a diagram showing the relationship between SC- ₅ and SC- ₇ .

FIG. 5 is a diagram showing a table indicating a field operation procedure stored in a RAM of the baseband memory unit shown in FIG. 2;

FIG. 6 is a flowchart illustrating a processing procedure of a CPU of a baseband memory unit illustrated in FIG. 2;

7A and 7B are diagrams illustrating timings of signals related to a field operation in the baseband memory unit illustrated in FIG. 2, wherein FIG. 7A is a waveform diagram of a VD signal VD, and FIG. 7B is a waveform diagram of a frame pulse signal FP; , (C) shows signal switching in the third to sixth changeover switches Sw3 to Sw6, and (D) shows first, second, and seventh changeover switches Sw.
1, (E) shows the switching of the control signals SCin and SCout input to the input signal switching circuit and the output signal switching circuit, and (F) shows the first to seventh signals. Changeover switches Sw1 to S
FIG. 14 is a diagram showing switching of a switching signal of w7.

8A and 8B are diagrams showing input / output data of a baseband memory unit when performing a 1/2 speed change reproduction, wherein FIG. 8A is a diagram showing video data for each input frame, and FIG. A shows a frame read and written in A, (C) shows an area read and written in bank A, (D) shows a frame read and written in bank B, and (E) shows a read and write in bank B. FIG. 4E is a diagram showing an area, and FIG. 4E is a diagram showing video data for each output frame.

9A and 9B are diagrams showing input / output data of a baseband memory unit when performing a x-1 / 2 variable speed playback, wherein FIG. 9A is a diagram showing video data for each input frame, and FIG. FIG. 4C shows a frame read / written to / from bank A, FIG. 5C shows an area read / written to / from bank A, FIG. 5D shows a frame read / written to / from bank B, and FIG. (E) is a diagram showing video data for each output frame.

FIG. 10 is a diagram illustrating input / output data of a baseband memory unit when performing x1 variable speed reproduction (normal reproduction);
(A) is a diagram showing video data for each input frame, (B) is a diagram showing frames read and written in bank A, (C) is a diagram showing areas read and written in bank A, and (D) is a diagram showing areas read and written in bank A. FIG. 3E is a diagram showing a frame read / written in bank B, FIG. 2E is a diagram showing an area read / written in bank B, and FIG. 2E is a diagram showing video data for each output frame.

[Explanation of symbols]

1 ... AV data recording / reproducing device, 11 ... D1 decoder, 1
2 ... compression circuit, 13 ... input changeover switch, 14 ... memory section, 15 ... hard disk section, 16 ... output changeover switch, 17 ... extension circuit, 18 ... baseband memory section, 1
9 D1 encoder, 21 first frame memory, 2
2 ... second frame memory, 30 ... input signal switching circuit,
31: output signal switching circuit, 32: ROM, 33: RA
M, 34 ... PIO, 35 ... CPU, Sw1 to Sw7 ... First to seventh changeover switches

Claims (6)

[Claims] Recording means for recording compressed and encoded video data; reproducing and decoding the recorded video data to obtain video data for each frame; and a frame corresponding to a desired reproduction speed. Reproducing means for generating a sequence of video data for each frame, temporarily recording the generated sequence of video data for each frame in a frame memory, and selectively reading out the recorded video data in field units. And a baseband memory means for generating playback video data of a desired playback speed and playback direction. 2. The baseband memory means includes: a plurality of frame memories each divided into a plurality of areas for storing video data for each field; and the generated and input video data for each frame.
Input switching means for sequentially and cyclically inputting the data to the plurality of frame memories; and storing the video data for each of the fields of the plurality of frame memories so that the video data is reproduced at a desired reproduction speed in a desired reproduction direction. 2. The video reproducing apparatus according to claim 1, further comprising: output selecting means for selectively reading the plurality of areas. 3. An output switching means for selecting and outputting video data for each field stored in any one of the divided areas of the plurality of frame memories, and a reproduction direction. And a switching rule storing means in which switching rules of the output switching means are stored in a table format so that video data of an appropriate field is output as appropriate based on the playback speed. 3. The video reproducing apparatus according to claim 2, further comprising control means for controlling said output switching means based on said output switching means. 4. The switching rule storage means further stores a switching rule of the input switching means based on a reproduction direction and a reproduction speed in a table format, and the control means, based on the stored switching rule, 4. The video reproducing apparatus according to claim 3, wherein said video switching device controls said output switching means and said input switching means. 5. The video reproducing apparatus according to claim 4, wherein said switching rule storage means stores said switching rule in a format that can be updated as appropriate. 6. A plurality of frame memories, each of which is divided into a plurality of areas for storing video data for each field and stores video data for each frame, and a column of video data for each input frame, Input switching means for selecting and inputting and storing any one of the memories; and selecting one of the divided areas of the plurality of frame memories and storing image data for each field stored in the area. Output switching means for reading and outputting the video data, and video data input by the input switching means based on the reproduction direction and the reproduction speed so that appropriate video data is output corresponding to a desired reproduction direction and reproduction speed. And a rule for selecting video data to be selected and output by the output switching means in a table format. Selection rule storing means for storing, on the basis of the selection rules that are the storage, baseband memory device and a control means for controlling the input switching means and said output switching means.