JPH10233506A - Insulating gate type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To preferentially reduce the cost of an insulating gate type semiconductor device by using a MOSFET of the same single channel type as that of a transistor for output as the transistor of a voltage comparator circuit which is a part of a protective circuit. SOLUTION: A semiconductor device is provided with a transistor 10 for output comprising an NMOSFET and an NMOSFET transistor 20 which is a part of a voltage comparator circuit. Since only the NMOSFET is used as the transistor of the voltage comparator circuit in this semiconductor device, the manufacturing process of a PMOSFET can be reduced when the transistor 10 comprises an N-channel transistor. That is, when only the NMOSFET is used as the transistor of the voltage comparator circuit and the analog operations are utilized for the voltage comparing operations of the voltage comparator circuit, the cost of the semiconductor device can be reduced by suppressing the increase of the number of manufacturing processes, although the accuracy of the device becomes rough. Therefore, this semiconductor device is suitable in such a case that the cost must be reduced even at the sacrifice of the accuracy of the voltage comparator circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate type semiconductor device (MOS type semiconductor device), and in particular, to abnormal output transistors (eg, overcurrent, overvoltage, or overheating).
It relates to a MOS type semiconductor device in which a protection circuit for controlling the gate of an output transistor is sometimes mounted on the same chip as the output transistor, and includes an intelligent power MOS module and an intelligent power IG.
It is used for a BT (insulated gate bipolar transistor) or the like.

[0002]

2. Description of the Related Art In general, a power semiconductor device requiring a high-power switch output, for example, a main switch element composed of a voltage-driven power transistor having a multi-cell structure and a semiconductor element group for controlling the same are formed of the same semiconductor. 2. Description of the Related Art An intelligent high-voltage power semiconductor device integrated on a chip is provided with an overcurrent limiting circuit.

This overcurrent limiting circuit detects an overcurrent of the output switch element, outputs an overcurrent detection signal, and transmits the overcurrent detection signal to a drive circuit for the switch element, thereby controlling the output switch element. Controlling to the OFF state to prevent its destruction (protects the output switch element from overcurrent).

The protection circuit provided for controlling the gate of the MOS type output transistor at the time of overcurrent, overvoltage or overheating of the output transistor as described above is obtained by detecting the operation state of the output transistor. The voltage and the reference voltage are compared by a voltage comparison circuit, so that when the abnormality of the output transistor is detected, the conduction of the output transistor is controlled to be cut off.

FIG. 4 shows an example of a conventional overcurrent limiting circuit for a power MOS FET (insulated gate field effect transistor). In FIG. 4, reference numeral 10 denotes a DMOS (double diffusion type) power FET having a multi-source structure (first source 10a, second source 10b), the drain of which is connected to a power supply terminal 40, and the first source 10 The (current output terminal) 10a is connected to a current output terminal (external load connection terminal) 41 of the IC. Reference numeral 42 denotes a load circuit connected to the current output terminal 41.

Reference numeral 43 denotes a power F from a built-in current source 43a.
This is a power FET drive circuit for controlling the gate potential of the power FET by turning on / off the supply output of the charging current to the gate capacitance C of the ET according to the power FET drive control signal.

Reference numeral 44 is connected to the second source (current detection terminal) 10b of the power FET, and the current detection terminal 1
This is a resistance element that converts a current flowing through Ob into a voltage signal and outputs the voltage signal.

Reference numeral 45 denotes an input of the output from the resistance element 44. The input voltage is compared with a predetermined reference voltage Vref. When the input voltage becomes higher than the reference voltage (for detecting the current flowing through the current detection terminal 10b). This is a linear voltage comparison circuit that outputs a current corresponding to an overcurrent when the current is overcurrent.

Reference numeral 46 denotes an output NPN transistor to which the output current of the voltage comparison circuit 45 is given as a base current, and the power FE is provided between the collector and the emitter thereof.
It is connected between the output node of the T drive circuit 43 and the ground node.

The voltage comparison circuit 45 and the output transistor 46 detect an overcurrent of the power FET,
By extracting the output current of the power FET drive circuit 43 according to the overcurrent and flowing the same to the ground potential, the power FET
Voltage comparison type current control circuit 4 for controlling the gate potential of 10
7.

Next, the configuration and operation of the conventional voltage comparison circuit 45 will be described. This voltage comparison circuit 45 is provided with an input voltage Vin and a predetermined reference voltage Vref corresponding to each base, and has a PNP type first transistor Q41 whose emitters are directly connected to form a differential pair.
And a second transistor Q42, and a constant current source 48 connected between the emitter common connection node of the transistors Q41 and Q42 forming the differential pair and a first power supply potential (high-potential-side power supply potential Vcc). , The first transistor Q
An NPN-type third transistor Q43 having a collector and an emitter connected between the collector of the transistor 41 and a second power supply potential (lower power supply potential, ground potential Vss) and having a collector and a base connected to each other. , A collector connected to the collector of the second transistor Q42, an emitter connected to the ground potential Vss, and a base connected to the base of the third transistor Q43. The third transistor Q4
The third and fourth transistors Q44 constitute a current mirror circuit.

In the operation of the voltage comparison circuit 45, when the input voltage Vin is equal to the reference voltage Vref, an equal current flows through the transistors Q41 and Q42 forming a differential pair, so that no output current from the voltage comparison circuit 45 occurs. On the other hand, when the input voltage Vin is higher than the reference voltage Vref,
The currents of transistors Q41 and Q42 forming a differential pair decrease and increase correspondingly. At this time, the transistors Q43 and Q44 of the current mirror circuit decrease and the transistor Q4
2 and a current flowing through the transistor Q44 (a current corresponding to the overcurrent) is output.

Next, the operation of the overcurrent limiting circuit having the above configuration will be described. At the time of normal operation, the applied voltage of the power supply terminal 40 is, for example, 12 V, the pulse signal input of the power FET drive circuit 43 changes between 0 V and, for example, 5 V, and the pulse signal output changes between 0 V and, for example, 20 V. . At this time, when 20 V is applied to the gate of the power FET 10, 1A flows to the current output terminal 10a of the power FET 10, and about 1/1000 (about 1 mA) of the current flows to the current detection terminal 10b of the power FET 10. .

In this state, the input voltage Vin becomes the reference voltage V
Since a current equal to ref flows through transistors Q41 and Q42 forming a differential pair in voltage comparison circuit 45, no output current from voltage comparison circuit 45 occurs.

When the load impedance is reduced due to a load short circuit or the like, the output current of the power FET 10 and the detection current increase, and when the detection current exceeds the reference current (overcurrent), the resistance from the resistance element 21 is reduced. A small potential difference occurs between the input voltage Vin and the reference voltage Vref in a direction in which the input voltage Vin becomes slightly larger than the reference voltage Vref. Thus, the output NPN transistor 46 to which the output current of the voltage comparison circuit 45 is given as the base current is connected to the power FE.
The output current of the T drive circuit 43 is extracted and the power FET 1
By performing feedback control so that 0 is turned off, the power FET 10 is protected.

Conventionally, as the voltage comparison circuit 45 as described above, a bipolar structure or C
Although this is realized by the MOS structure, the number of manufacturing steps is increased as compared with the manufacturing steps of the output transistor.

That is, the output transistor is a CMO
Instead of S structure, M of one channel (usually N channel)
In most cases, the P-type semiconductor layer for insulating and separating the output transistor having the single-channel structure and the voltage comparison circuit having the bipolar structure or the CMOS structure as described above is used. Or CMOS
The number of steps for forming a P + or N + semiconductor layer in the structure is increased.

FIG. 5 shows a part of an example of a sectional structure of a conventional power MOS FET having a protection function. 5, reference numeral 50 denotes an output transistor having an NMOS structure; 51, a drain electrode of the output transistor;
Numeral 2 denotes an NPN-type bipolar transistor which is a part for a voltage comparison circuit. In addition to an N-type semiconductor region 53 and an N + semiconductor region 54, a P-type semiconductor region 55 for forming a base region of the NPN transistor 52 and an NMOS A P-type semiconductor layer 56 for insulating and separating the output transistor 50 and the bipolar 52 having the structure is required.

FIG. 6 shows a conventional power MO having a protection function.
14 shows a part of another example of the cross-sectional structure of the SFET. In FIG. 6, reference numeral 60 denotes an output transistor having an NMOS structure, 61 denotes a drain electrode of the output transistor, 62 denotes a CMOS transistor which is a part of a voltage comparison circuit, and includes an N-type semiconductor region 63 and an N + semiconductor region 64. In addition, a P + drain / source region 65 for forming a PMOS transistor and a P-type semiconductor layer 66 for insulating and isolating an output transistor 60 having a NMOS structure and a CMOS transistor 62 are required.

FIG. 7 shows the CMOS transistor 6 in FIG.
2 shows an example of a voltage comparison circuit using the second circuit. In FIG. 7, Q1 to Q5 are PMOS transistors and Q6 to Q5.
8 is an NMOS transistor, R is a resistance element, Vcc is a power supply voltage, Vi is an input voltage, Vref is a reference voltage, and Vout is an output voltage.

[0021]

As described above, the voltage comparison circuit of the protection circuit for controlling the gate of the output transistor when the output transistor is abnormal is realized by a CMOS structure or a Bi-CMOS structure and is the same as the output transistor. Conventional MOS type semiconductor devices mounted on a chip
There is a problem that the number of manufacturing steps increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a voltage comparison circuit of a protection circuit for controlling the gate of an output transistor when an output transistor is abnormal is mounted on the same chip as the output transistor. In this case, an object of the present invention is to provide an insulated gate semiconductor device that can be realized with priority given to cost reduction.

[0023]

According to the present invention, there is provided an insulated gate semiconductor device comprising: a single-channel output transistor;
A protection circuit that is mounted on the same chip as the output transistor and controls a gate of the output transistor when the output transistor is abnormal, wherein the output is a transistor of a voltage comparison circuit that is a part of the protection circuit. Single channel type MOS FET same as transistor
Is used.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a part of an example of a sectional structure of a power MOS FET having a protection function according to a first embodiment of a MOS type semiconductor device of the present invention.

In FIG. 1, reference numeral 10 denotes a double diffusion type NMO.
Reference numeral 11 denotes an output transistor comprising an SFET, 11 denotes an N + drain region of the output transistor, 12 denotes an N-type drain region of the output transistor, 13 denotes an N + source region of the output transistor, and 14 denotes a channel of the output transistor. A formation region, 15 is a gate insulating film on the surface of the semiconductor substrate, 16 is a source electrode of the output transistor, 17 is a gate electrode of the output transistor, and 18 is a drain electrode of the output transistor.

Reference numeral 20 denotes an NMO which is a part for a voltage comparison circuit.
Reference numeral 21 denotes a P-well for forming an NMOS transistor; 22, an N + drain region of the NMOS transistor; 23, an N + source region of the NMOS transistor; 24, a gate electrode of the NMOS transistor;
Is the drain electrode of the NMOS transistor, and 26 is the NMO
This is the source electrode of the S transistor.

FIG. 2 shows the NMOS transistor 2 in FIG.
5 shows an example of a voltage comparison circuit using 0. In FIG. 2, Q9 to Q11 are depletion type NMOSs.
Transistors, Q12 to Q18 are enhancement type NMOS transistors, R is a resistance element, R is a resistance element,
Vcc is the power supply voltage, Vi is the input voltage, Vref is the reference voltage,
Vout is an output voltage.

In FIG. 2, the current source circuit 21 has an enhancement-type NMOS transistor Q16 connected in series with a resistance element R and a drain / gate connected between a Vcc node and a ground node.

The differential amplifier circuit 22 has an enhancement-type NMOS transistor Q13 for inputting a comparison voltage (voltage to be detected) and a enhancement-type NMOS transistor Q14 for inputting a reference voltage. A current source NMOS transistor Q17 connected between the commonly connected node and the ground node, and a current source NMOS transistor Q17 and a drain of each of the two transistors Q13 and Q14 forming the differential pair. It consists of a depletion type NMOS transistor Q9, Q10 which is inserted as a load element and whose drain and gate are connected respectively.

The drain of the NMOS transistor Q14 for inputting the reference voltage is connected to the source follower circuit 23.
The source follower circuit 23
Are amplified by the common source circuit 24 and output.

In the source follower circuit 23, an enhancement type NMOS transistor Q12 for buffer amplification and an enhancement type NMOS transistor Q18 for current source are connected in series between the Vcc node and the ground node.

In the source grounding circuit 24, a depletion type NMOS transistor Q11 connected to a drain / gate for a load element and an enhancement type NMOS transistor Q15 for amplification are connected in series between a Vcc node and a ground node. It is connected.

The NMOS transistor Q16 of the current source circuit 21 and the current source N of the differential amplifier circuit 22 are used.
MOS transistor Q17 and source follower circuit 2
The gate is connected to the NMOS transistor Q18 for the current source of No. 3 to form a current mirror circuit.

Here, at least the gate-source voltage VGS of one of the two transistors Q13 and Q14 forming the differential pair must be equal to or higher than the gate threshold voltage Vth.

According to the MOS type semiconductor device having the above structure,
Since only the NMOS FET is used as the transistor of the voltage comparison circuit, the manufacturing process of the PMOS FET can be reduced when the output transistor is an N-channel type transistor.

That is, if only the NMOS FET is used as the transistor of the voltage comparison circuit and the voltage comparison operation is performed by using the analog operation of the NMOS FET, the accuracy is reduced, but the increase in the number of manufacturing steps is suppressed. Since the cost can be reduced, it is suitable for a case where priority is given to cost reduction even if accuracy of the voltage comparison circuit which is a part of the output transistor protection circuit is sacrificed.

The depletion type transistor has many manufacturing steps and requires a dedicated mask for implanting impurities into the channel region, so that the cost is increased. Recently, as semiconductor memory devices become more highly integrated, chip cost reduction has become an important issue, and it has been desired to configure circuits without using depletion type transistors. The voltage comparison circuit along the line will be described below.

FIG. 3 shows an NMO for the voltage comparison circuit shown in FIG.
An example is shown in which only enhancement type transistors are used as S transistors. In FIG. 3, Q19
Q22 to Q22 are enhancement type NMOS transistors, R1 to R5 are resistance elements, Vcc is a power supply voltage, Vi is an input voltage, Vref is a reference voltage, and Vout is an output voltage.

That is, the differential amplifier circuit 31 has a comparison voltage (voltage to be detected) in which the sources are commonly connected to form a differential pair.
Enhancement type NMOS transistor Q for input
20 and enhancement type NM for reference voltage input
An OS transistor Q21, resistance elements R1 and R2 respectively connected between a Vcc node and drains of the transistors Q20 and Q21 forming the differential pair, and a commonly connected node and a ground node of the transistors Q20 and Q21. And a resistance element R3 connected between them.

The drain of the NMOS transistor Q21 for inputting the reference voltage is connected to the source follower circuit 32.
The source follower circuit 32
Is amplified by the common source circuit 33 and output from the output node.

In the source follower circuit 32, an enhancement type NMOS transistor Q19 for buffer amplification and a resistance element R4 are connected in series between the Vcc node and the ground node.

The common source circuit 33 includes a load resistance element R5 and an amplification type enhancement type NMOS transistor Q22 between the Vcc node and the ground node.
Are connected in series.

Here, at least the gate-source voltage VGS of one of the two transistors Q20 and Q21 forming the differential pair must be equal to or higher than the gate threshold voltage Vth.

It should be noted that the present invention provides the power MOS
The invention can be applied not only to FETs but also to intelligent power IGBTs using, for example, N-channel IGBTs having a multi-emitter structure as output transistors.

[0045]

As described above, according to the MOS semiconductor device of the present invention, the voltage comparison circuit of the protection circuit for controlling the gate of the output transistor when the output transistor is abnormal is mounted on the same chip as the output transistor. In this case, cost reduction can be realized with priority.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of an example of a structure of a power MOS FET according to a first embodiment of a MOS type semiconductor device of the present invention.

FIG. 2 is a circuit diagram showing an example of a voltage comparison circuit using the NMOS transistors in FIG.

FIG. 3 is a circuit diagram showing another example of the voltage comparison circuit using the NMOS transistors in FIG. 1;

FIG. 4 is a circuit diagram showing an example of a conventional overcurrent limiting circuit of a power MOS FET.

FIG. 5 shows a conventional power MOS FET having a protection function.
Sectional drawing which shows a part of example of the structure of FIG.

FIG. 6 shows a conventional power MOS FET having a protection function.
Sectional drawing which shows some other examples of the structure of FIG.

7 is a circuit diagram showing an example of a voltage comparison circuit using the CMOS transistors in FIG.

[Explanation of symbols]

 Reference Signs List 10: NMOS output transistor, 11: N + drain region of output transistor, 12: N-type drain region of output transistor, 13: N + source region of output transistor, 14: Channel formation of output transistor Region 15: gate insulating film on the surface of the semiconductor substrate 16: source electrode of the output transistor 17: gate electrode of the output transistor 18: drain electrode of the output transistor 20: NMOS transistor 21: for forming NMOS transistor 22 ... N + drain region of NMOS transistor, 23 ... N + source region of NMOS transistor, 24 ... Gate electrode of NMOS transistor, 25 ... Drain electrode of NMOS transistor, 26 ... Source electrode of NMOS transistor.

Claims (4)

[Claims] An output transistor of a single channel type; and a protection circuit mounted on the same chip as the output transistor and controlling a gate of the output transistor when the output transistor is abnormal. An insulated gate semiconductor device, wherein the same single-channel MOS FET as the output transistor is used as a transistor of a voltage comparison circuit that is a part of a protection circuit. 2. The insulated gate semiconductor device according to claim 1, wherein said output transistor is an N-channel transistor, and said single-channel MOSFET is a depletion type NMOS transistor and an enhancement type NMOS transistor. An insulated gate semiconductor device comprising both. 3. The insulated gate semiconductor device according to claim 1, wherein said output transistor is an N-channel type transistor, and said single-channel type MOS FET is an enhancement type NMOS transistor. Gate type semiconductor device. 4. The insulated gate semiconductor device according to claim 1, further comprising a protection circuit that cuts off conduction of the output transistor when an overcurrent, overvoltage, or overheating of the output transistor occurs. Power MOS
An insulated gate semiconductor device, which is an FET or a power IGBT.