JPH10229331A - Input circuit - Google Patents

Abstract

(57) [Problem] To prevent power consumption from increasing even if switching is performed in a short cycle or a hysteresis voltage is increased. SOLUTION: MISTrM3 for generating hysteresis
Has its gate connected to the signal input terminal of the input unit 12. Further, when the MISTrM2 of the input unit 12 is in a conductive state, a unit (for example, switching) that holds an electric path between the first power supply VDD to which the MISTrM3 is connected and the output node ND1 of the input unit 12 in an interrupted state MISTrM4) was connected. Thereby, MIST
When rM2 is conducting, the operating current i _{3 of} MISTrM3 is
It does not flow into the MISTrM2 side as the through current IDC. In order to increase the hysteresis voltage without increasing the through current IDC, the MISTrM for generating the hysteresis is required.
5 and a switching MISTrM6 may be further provided on the second power supply VSS side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit using, for example, a CMOS inverter, and more particularly to a circuit for rising and falling output pulses so that waveform shaping can be performed while removing noise. The present invention relates to an input circuit with hysteresis in which a threshold voltage has hysteresis characteristics (hysteresis).

[0002]

2. Description of the Related Art As an example of a conventional CMOS input circuit with hysteresis, for example, an inverter input circuit has a circuit configuration shown in FIG. That is, the input circuit 2 connects the MOS transistor M3 for generating hysteresis to the power supply voltage supply line VDD or the reference voltage supply line with respect to the output V _{OUT of} the normal inverter input section 4 composed of the pMOS transistor M1 and the nMOS transistor M2. In addition to inserting the pMOS transistor M3 into one side of the line VSS (here, the pMOS transistor M3 is connected to the power supply line VDD), the control inverter 6 for controlling the hysteresis generating MOS transistor M3 is connected to the output V _{OUT of the} inverter input unit 4. It was configured to be connected to.

Next, the operation of the illustrated input circuit 2 will be described.
I will tell. First, the input V of the inverter input unit 4_INBut haile
When transitioning from the bell to low level, the pMOS transistor
When the transistor M1 changes from the cut-off state to the conductive state, the nMOS transistor
M2 shifts from the conductive state to the cutoff state,
Output V of barter input unit 4 _OUTBut from low level to high level
Then, the output pulse rises. At the same time,
Inverter 6 for trawl generates M for hysteresis
The gate of the OS transistor M3 becomes low level,
MOS transistor M3 is also conductive. This and
FIG. 3 shows the pMOS transistors M1 and M3.
Thus, the operating current i₁ , I_ThreeFlows. This dynamic
Operation current i₁ , I_ThreeIs to charge the load side
Flows for a time corresponding to the time constant.

Here, it is assumed that the hysteresis generating MOS transistor M3 and the control inverter 6 are not provided. At this time, the high level of the output pulse appearing at the output V _OUT is VH and the low level is VL. As is well known, the circuit threshold voltage V of this inverter
thc is a pMOS transistor M1 on the power supply voltage supply line VDD side and an nMOS transistor M1 on the reference voltage supply line VSS side.
The on-resistance ratio is determined by the ratio of Vthc0 = (VH-VL) / 2 = VDD / 2.

On the other hand, in the case of FIG. 3, since the hysteresis generating MOS transistor M3 which becomes conductive in conjunction with the pMOS transistor M1 is provided as described above, the pMOS transistor The ON resistance on the M1 side is smaller than that on the nMOS transistor M2 side. Therefore, the circuit threshold voltage Vthc
Is ΔVthc against Vthc0 in preparation for the next pulse fall.
(Hereinafter, referred to as a hysteresis voltage) (hereinafter, referred to as a circuit threshold voltage Vthc (off)).

On the other hand, when the input V _IN of the inverter input section 4 shifts from the low level to the high level, the pMOS transistor M1 changes from the conductive state to the cut-off state, while the nMOS transistor M1 changes from the n-state
Since the S transistor M2 transitions from the cut-off state to the conductive state, the output pulse falls at the output V _OUT of the inverter input unit 4. In conjunction with this, the pMOS transistor M3 for generating hysteresis is turned off, and the circuit threshold voltage Vthc returns to the original Vthc0 in preparation for the next rise of the pulse (hereinafter, the circuit threshold). Value voltage Vth
c (on)).

As described above, the output voltage of the inverter input circuit 2 with hysteresis is equal to the normal circuit threshold voltage Vthc0 when the input _VIN changes from the high level to the low level, as shown in FIG. Circuit threshold voltage Vth
With c (on), output pulse rises. When the input V _IN shifts from a low level to a high level, the output pulse falls at a circuit threshold voltage Vthc (off) that is larger than the normal circuit threshold voltage Vthc0 by the hysteresis voltage ΔVthc.

FIG. 5 is a diagram showing the operation of the inverter input circuit 2 with hysteresis in comparison with a normal inverter. In the description here, the normal operation of the inverter will be described with the inverter input unit 4. In the normal inverter input unit 4, when noise crossing the circuit threshold voltage Vthc is present on the input V _IN , as shown in FIG. There may be a phenomenon (chattering) in which pulses repeat in time. If there is chattering of this output pulse,
An internal circuit, such as a CPU, to which this is input causes a malfunction.

On the other hand, in the inverter input circuit 2 with hysteresis, as shown in FIG. 5B, the rising and falling of the output pulse causes the circuit threshold voltage Vth to rise.
The value of c is different, thereby preventing the occurrence of chattering of the output pulse. That is, the circuit threshold voltage Vthc
By setting the hysteresis voltage ΔVthc, which is the difference between the two, larger in advance than the repetition fluctuation width of the input due to noise, the influence of noise can be suppressed.

[0010]

However, in this conventional input circuit 2 with hysteresis, when the output pulse rises after the input _VIN changes from the high level to the low level, the input then goes high. Until the output pulse falls, the conduction state of the hysteresis generating MOS transistor M3 continues for a long time, so that there is a problem that power consumption increases.

In a normal inverter input section 4,
As shown in FIG. 3, when this output pulse rises,
Output V_OUTIn the early stage of the pulse rise,
The operating voltage of the pMOS transistor M1 forming the input unit 4
Flow i₁Only flowed. Also, the output pulse falls
Output V in a crooked state_OUTFrom the first pulse fall
The nMOS transistor constituting the inverter input unit 4
The operating current i _TwoIs supplied from the load side. Further
In addition, switching of output pulse, that is, before and after switching
A through current IDC passes through both transistors M1 and M2.
The amount of power consumption is determined by the flow and the total of these.

On the other hand, in the conventional input circuit 2 with hysteresis, as shown in FIG. 3, when the output pulse _rises , the current flowing to the output V _OUT side includes not only the operating current i ₁ but also the hysteresis generation current. operating current i ₃ of the MOS transistor M3 is added. Further, when the switching is performed continuously, increases without converging this operation current i _3, its increment i _31, is added to the through current IDC flowing back and forth during switching. Furthermore, if the hysteresis voltage ΔVthc is to be increased in order to suppress the influence of noise on the input side, the size (eg, gate width) of the MOS transistor M3 for generating hysteresis increases, and the current consumption increases accordingly.

Therefore, there is a strong demand for an input circuit with hysteresis that does not increase power consumption even if switching is performed in a short cycle or hysteresis voltage ΔVthc is increased. The present invention has been made in view of such circumstances, and has as its object to provide an input circuit with hysteresis in which power consumption does not increase even when switching is performed in a short cycle or a hysteresis voltage is increased.

[0014]

In order to solve the above-mentioned problems of the prior art and achieve the above object, an input circuit according to the present invention employs a metal insulating film semiconductor (M) for generating hysteresis.
IS: Metal Insulator Semiconductor) A transistor has an electric path which is a reverse conductive type MI which forms an input portion.
When the S transistor is turned on, it is disconnected from the output node of the input section.

Specifically, the input circuit according to the present invention includes a first MIS transistor having a first conductivity type connected between a first power supply and an output node, and a second MIS transistor having a second conductivity type and an output node. A second MIS having a second conductivity type connected therebetween
A first power supply and an output node of the input unit, each gate of which is connected to a signal input terminal, and a gate connected to the signal input terminal. A third MIS transistor having a first conductivity type, the signal having the same level as the input signal being input to the gate (by being connected to the terminal), and obtaining a signal having a hysteresis characteristic; When the second MIS transistor of the portion is in a conductive state,
Means for keeping an electric path between the first power supply connected to the third MIS transistor and the output node of the input unit in a cutoff state (for example, a switching element such as a fourth MIS transistor having a first conductivity type) ).

With such a circuit configuration, the means for holding the electric path in the cutoff state is cut off during the switching operation, so that the current flows from the third MIS transistor side into the through current at the time of switching of the input section. There is nothing. Therefore, power consumption can be reduced as compared with the conventional case.

Further, conventionally, in order to increase the hysteresis voltage, the size (eg, gate width) of the third MIS transistor has to be increased. Since the inputs of the transistors are connected in parallel, for example, the first MIS
The size of the hysteresis voltage is determined by the overall size of the transistor and the third MIS transistor. Therefore, the third MIS transistor does not need to be too large.

In order to increase the hysteresis voltage without increasing the operating current, a transistor for generating hysteresis and a fifth MI having the second conductivity type as a blocking means for the transistor are provided.
Contrary to the above, the S transistor and the second means (for example, the sixth MIS transistor having the second conductivity type) for holding the electric path in the cutoff state are connected between the output node and the second power supply side. It may be further provided between them.

With such a circuit configuration, the circuit threshold voltage can be changed not only on the positive side but also on the negative side without changing the size of each transistor, as compared with a normal inverter input circuit. It is easy to increase the hysteresis voltage, which is preferable in this sense.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An input circuit according to the present invention will be described below in detail with reference to the drawings. First Embodiment In the present embodiment, an inverter input circuit will be described with reference to FIG. 1 as an input circuit according to the present invention.

The inverter input circuit 10 generally includes a first power supply voltage supply line VDD as a first power supply and a reference voltage supply line VSS as a second power supply. An inverter input unit 12, a hysteresis generation unit 14, and a control inverter 16 composed of a first MIS transistor having a conductivity type and a second MIS transistor having a second conductivity type are inserted in parallel. I have.

The input unit 12 includes, for example, a pMOS transistor M1 having a first conductivity type and an nMOS transistor M2 having a second conductivity type connected in series between a power supply voltage supply line VDD and a reference voltage supply line VSS. , And the respective gates are connected to each other and connected to the input V _IN .

The hysteresis generation section 14 also has two hysteresis generation MOS transistors having the same configuration, that is, a third MIS transistor (pMOS transistor M3).
And a fifth MIS transistor (nMOS transistor M)
5). These gates are also connected to each other and connected to V _IN . In the middle of the connection between the drains of the pMOS transistor M3 and the nMOS transistor M5, a fourth MIS transistor (pMOS for switching) is connected to the pMOS transistor M3.
A sixth MIS transistor (switching nMOS transistor M6) is connected to the transistor M4) and the nMOS transistor M5, respectively. The midpoint between the two is connected to the output node ND1 of the inverter input unit 12. The switching MOS transistors M4 and M6 are connected to the power supply voltage supply line VDD, respectively.
Side or the reference voltage supply line VSS side.

The control inverter 16 also has two MOS transistors having the same configuration, that is, a pMOS transistor M7 and an nMOS transistor M8. Their gates are connected to the output node ND1, and the output V
_OUT is taken out. The output of the control inverter 16 is connected to the switching MOS
It is connected to the gates of transistors M4 and M6.

Next, the circuit operation will be described. First, when the input V _IN of the inverter input unit 12 shifts from a high level to a low level, the pMOS transistor M1 shifts from a cut-off state to a conductive state, and the nMOS transistor M2 shifts from a conductive state to a cut-off state. This operation is the same in the hysteresis generation section 14, and pMO
The S transistor M3 transitions to the conductive state, and the nMOS transistor M5 transitions to the cutoff state.

[0026] At this time, the output V _{OU T} taken out from the output node ND1 of the inverter input unit 12, it rises the output pulse. Therefore, the control inverter 1
6 pMOS for switching by inverter operation of 6.
The transistor M4 is turned on, but the other switching nMOS transistor M6 remains off. Therefore, as shown, the pMOS transistor M
1 and M3, the respective operating currents i ₁ and i ₃ are output V
_It flows toward _OUT until the capacitance on the load side is charged.

Here, assuming that the hysteresis generator 14 and the control inverter 16 are not provided, the high level of the output pulse appearing at the output V _OUT at this time is represented by VH.
, And the low level is VL. As is well known, the circuit threshold voltage Vthc of this inverter is determined by the ratio of the on-resistance of the pMOS transistor M1 on the power supply voltage supply line VDD side to the nMOS transistor M2 on the reference voltage supply line VSS side. Are theoretically the same, Vth
c0 = (VH-VL) / 2 = VDD / 2.

On the other hand, in the case of FIG. 1, as described above, the MOS transistor M3 and the MOS transistor M3 for generating hysteresis which become conductive in conjunction with the pMOS transistor M1 are turned on.
With the provision of the transistor M4, apparently,
The ON resistance on the pMOS transistor M1 side is
It is smaller than the nMOS transistor M2 side. For this reason, the circuit threshold voltage Vthc increases by ΔVth (hysteresis voltage) with respect to Vthc0 in preparation for the next pulse falling, and the second circuit threshold voltage increases from the first circuit threshold voltage Vthc (on). The voltage shifts to the value voltage Vthc (off).

Next, the input V _IN of the inverter input unit 12
At the time of switching from low level to high level, the circuit threshold voltage Vthc (off) at that time is input to the input V _IN
Before and after crossing, the pMOS transistor M1 and nMO
Both of the S transistors M2 have a transient state in which the channel is slightly opened. Therefore, the power supply voltage supply line V
A through current IDC that flows through both MOS transistors M1 and M2 flows from DD toward the reference voltage supply line VSS.

When the switching is completed, the pMOS transistors M1 and M3 are changed from the conductive state to the cutoff state,
The transistors M2 and M5 transition from the cutoff state to the conduction state, respectively. Accordingly, the output pulse appearing at the output V _OUT shifts from the high level VH to the low level VL and falls. For this reason, the inverter operation of the control inverter 16 causes the switching pM
The OS transistor M4 is turned off, and the other switching nMOS transistor M6 is turned on. Therefore, as shown in the figure, from the output V _OUT side, the nMOS transistor M
2, the operating current i _2, i ₅ of M5 is supplied, which flows to the load side of the capacitor is discharged. Also, nMO
Since the nMOS transistor M5 for generating the hysteresis which transitions to the cutoff state in conjunction with the S transistor M2 is provided, the on-resistance of the nMOS transistor M2 is apparently smaller than that of the pMOS transistor M1 by that much. . For this reason, the second circuit threshold voltage Vthc (off) at the time of the falling of the pulse is reduced by the hysteresis voltage ΔVthc from Vthc0, and shifts to the first circuit threshold voltage Vthc (on).

As described above, in the inverter input circuit 10 with hysteresis, the operating currents i ₃ , i ₅ of the hysteresis generating MOS transistors M ₃ , M 5 are reduced by the presence of the switching MOS transistors M 4, M 6 inverting each other. Since the current does not flow into the through current IDC, the current consumption can be reduced accordingly.

In the input circuit 10, when the input V _IN shifts from the high level to the low level, the first circuit threshold voltage takes a value smaller than the normal circuit threshold voltage Vthc0 by the hysteresis voltage ΔVthc. The output pulse rises at Vthc (on). On the other hand, when the input changes from the low level to the high level, the normal circuit threshold voltage V
The output pulse falls at the second circuit threshold voltage Vthc (off) having a value larger than the thc0 by the hysteresis voltage ΔVthc. These first circuit threshold voltages ΔVthc (o
n) and the second circuit threshold voltage ΔVthc (off) are the MOS transistors M3 and M5 for generating hysteresis, respectively.
Is adjusted by changing the size (eg, gate width). As described above, in the case where two MOS transistors for generating the hysteresis that invert each other are provided, the magnitude of the hysteresis voltage ΔVthc can be increased to, for example, about twice as compared with the case where only one MOS transistor is provided.

Further, conventionally, the hysteresis voltage ΔV
To increase thc, the size of the hysteresis generating MOS transistors M3 and M5 must be increased. On the other hand, in the input circuit 10 of the present invention, since the inputs of the MOS transistors (M1 and M3, M2 and M5) that operate in tandem are connected in parallel, for example, the pMOS transistor M1 and the MOS transistor M3 for generating hysteresis are connected. Hysteresis voltage ΔVth with overall size
The size of c is determined. Therefore, the hysteresis generation M
There is an advantage that the size of the OS transistors M3 and M5 does not need to be too large.

In the input circuit 10, the hysteresis voltage ΔVthc can be increased at the rise and fall of the output pulse without increasing the current consumption, thereby preventing the occurrence of chattering of the output pulse. That is, by setting the hysteresis voltage ΔVthc to be larger than the half width of the repetition fluctuation of the input due to noise in advance, it is possible to minimize the influence of noise. As a result, even when noise is present at the input, the occurrence of chattering in which the output pulse of the input circuit 10 repeats within a short time is thereby suppressed, thereby effectively preventing malfunction in an internal circuit such as a CPU at the next stage. It is possible to do.

Second Embodiment This embodiment is a case where the hysteresis generation section 14 has a one-sided configuration. Here, FIG. 2 shows a buffer input circuit in which the output is taken out from the output side 6a of the hysteresis generating inverter in the case of FIG. 3, and the buffer input circuit will be described below. Note that the same circuit components and operations as those in the first embodiment described above are denoted by the same reference numerals as in FIG. 1, and description thereof will be omitted.

In the buffer input circuit 20, the hysteresis generation section 14 includes a pMOS transistor M 3 for generating hysteresis and the output node N of the buffer input section 12.
D1 and a switching pMOS transistor M4. The gate of the pMOS transistor M3 for generating hysteresis is connected to the MOS transistors M1 and M2 forming the buffer input unit 12.
And are connected in parallel to the input V _IN . In the input circuit 20 of the present embodiment, the output V _OUT is obtained from the output of the control inverter 16.

When the input V _IN shifts from the high level to the low level, both the pMOS transistors M1 and M3 change to the conducting state, the potential of the output node ND1 changes to the high level, and the switching operation is performed by the inverter operation of the control inverter 16. , The input level of the pMOS transistor M4 drops, and this transitions to the conductive state. With this series of operations, an output pulse rises at the output V _OUT . Thereby, the pMOS transistors M1 and M3
Operating currents i ₁ and i ₃ flow until the load-side capacity is charged.

Before and after switching, a through current IDC similar to that of the first embodiment flows in the illustrated direction. Subsequently, when the input V _IN shifts from the low level to the high level, both the pMOS transistors M1 and M3 are cut off, and n
MOS transistor M2 conducts. Further, the potential of the output node ND1 becomes low level, and the inverting operation of the control inverter 16 shuts off the pMOS transistor M4. With this series of operations, the output V
_The output pulse that appears at _OUT falls. Accordingly, the output V _OUT side, the operating current i ₂ of the nMOS transistor M2 is supplied.

[0039] In this embodiment also, at the same time as the interruption of the hysteresis generation pMOS transistors M3, and cut off the pMOS transistor M4, hereinafter, this operating current i ₃ never flow into the through current IDC side. Therefore,
Current consumption can be reduced as compared with the conventional case. However, compared with the first embodiment, the effect of reducing the current consumption is small.

Further, a pMOS transistor M4 is added to the conventional circuit, and the size of the pMOS transistor M3 for generating hysteresis can be reduced as in the case of the first embodiment. There is not much increase.

Of course, as in the first embodiment, the hysteresis circuit section 14 may be provided on the reference voltage supply line VSS side.

[0042]

As described above, according to the input circuit of the present invention, the electric path of the third and sixth MIS transistors for generating the hysteresis is changed by the means for interrupting the electric path (for example, the MIS transistor). And the like, the switching element is turned off when the MOS transistor for generating hysteresis is turned on, so that the through current of the input section does not increase even when switching is repeated in a short cycle.

The hysteresis voltage can be increased without increasing the size (eg, gate width) of the hysteresis MIS transistor. Thus, the present invention is expected to greatly contribute to lower power consumption and enhanced noise immunity as an input circuit of a semiconductor device or the like.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an inverter input circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a buffer input circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram used to explain a problem to be solved in a conventional input circuit with hysteresis.

FIG. 4 is an input / output voltage transfer characteristic diagram of a conventional input circuit with hysteresis.

FIG. 5 is an explanatory diagram showing the operation of a conventional input circuit with hysteresis in comparison with a normal input circuit without hysteresis.

[Explanation of symbols]

2 ... Conventional input circuit with hysteresis, 4 ... Inverter input section, 6 ... Control inverter, 10 ... Inverter input circuit (input circuit), 12 ... Inverter input section,
Buffer input section (input section), 14 hysteresis generation section, 16 control inverter, 20 buffer input circuit (input circuit), M1 pMOS transistor (first MIS transistor having first conductivity type), M
2 ... nMOS transistor (second MIS transistor having the second conductivity type), M3 ... p for generating hysteresis
MOS transistor (third MIS having first conductivity type)
Transistor), M4 ... pMOS transistor for switching (third MIS transistor having first conductivity type), M5 ... nMOS transistor for generating hysteresis (fifth MIS transistor having second conductivity type),
M6: switching nMOS transistor (sixth MIS transistor having the second conductivity type); M7: pMOS transistor forming a control inverter; M8 ... nMO forming a control inverter
S transistor, V _IN … input (signal input terminal), V _OUT
... output, ND1 ... output node of the input unit, i ₁ , i ₂ , i
_3, i ₅ ... operating current, IDC ... through current, Vtho ... conventional circuit threshold voltage, Vthc (on) ... circuit threshold voltage upon pulse startup, Vthc (off) ... pulse elevational lowered when circuit Threshold voltage, ΔVthc: hysteresis voltage.

Claims (6)

[Claims] A first metal-insulating-film semiconductor transistor having a first conductivity type connected between a first power supply and an output node; and a first metal-insulating-film semiconductor transistor having a first conductivity type connected between a second power supply and an output node. An input unit configured to include a second metal insulating film semiconductor transistor having two conductivity types, each of which has a gate connected to a signal input terminal; a first power supply; and an output node of the input unit And a third metal insulating film semiconductor transistor having a first conductivity type having a gate to which a signal having the same level as the input signal is input, and obtaining a signal having hysteresis characteristics. When the second metal-insulating-film semiconductor transistor of the input unit is in a conductive state, the first power supply to which the third metal-insulating-film semiconductor transistor is connected and an output node of the input unit; An input circuit having a means for keeping an electric path between them in a disconnected state. 2. The gate of the third metal-insulating-film semiconductor transistor is connected to the signal input terminal, and the means for maintaining the cut-off state includes the third metal-insulating-film semiconductor transistor and an output of the input unit. The input circuit according to claim 1, further comprising a switching element connected between the output node and the output node, the switching element switching between a conductive state and a non-conductive state according to the level of the output node. 3. The input circuit according to claim 2, wherein said switching element comprises a fourth metal insulating film semiconductor transistor having a first conductivity type and a gate connected to said output node. 4. A fifth metal insulating film semiconductor having a second conductivity type, which is connected between the second power supply and an output node of the input unit, and has a gate to which a signal having the same level as an input signal is input. A transistor; a second power supply connected to the fifth metal insulating film semiconductor transistor when the first metal insulating film semiconductor transistor of the input unit is in a conductive state; and an output node of the input unit. 4. An input circuit according to claim 1, further comprising: a second means for keeping an electric path between the first and second circuits in an interrupted state. 5. The fifth metal-insulating-film semiconductor transistor has a gate connected to the signal input terminal, and the second means includes a fifth metal-insulating-film semiconductor transistor and an output node of the input unit. 5. The input circuit according to claim 4, further comprising a second switching element connected between the second switching element and a switching state between a conductive state and a non-conductive state according to the level of the output node. 6. 6. The second switching element according to claim 6, wherein a gate of the second switching element is connected to the output node and has a second conductivity type.
6. The input circuit according to claim 5, wherein said input circuit comprises a metal insulating film semiconductor transistor.