JPH10229160A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH10229160A JPH10229160A JP9030091A JP3009197A JPH10229160A JP H10229160 A JPH10229160 A JP H10229160A JP 9030091 A JP9030091 A JP 9030091A JP 3009197 A JP3009197 A JP 3009197A JP H10229160 A JPH10229160 A JP H10229160A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor chip
- electromagnet
- semiconductor device
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【課題】 ＬＯＣリード自体を変更することなく安定し
たワイヤーボンディングを行う。微細化に対するリード
の幅を縮小する。歩留を向上する。
【解決手段】 半導体チップ１の素子形成面上に絶縁性
接着テープ２を介在させてリード３を接着固定し、前記
半導体チップ１の外部端子と磁性体からなるリード３の
内部端子とをワイヤーで電気的に接続し、封止体で封止
する半導体装置の製造方法において、前記半導体チップ
１の素子形成面に絶縁性接着テープ２を介在させて前記
リード３の内部端子部を磁力で接着するものである。ま
た、電磁石７を準備し、前記半導体チップ１の素子形成
面上とリード３の内部端子部とを接着する時、電磁石７
に電磁力を発生させ、半導体チップ１とリード３の両者
を接着固定した後、電磁石７の電磁力を消減させて取り
去るものである。
[PROBLEMS] To perform stable wire bonding without changing a LOC lead itself. Reduce the width of leads for miniaturization. Improve yield. SOLUTION: A lead 3 is adhesively fixed on an element forming surface of a semiconductor chip 1 with an insulating adhesive tape 2 interposed therebetween, and an external terminal of the semiconductor chip 1 and an internal terminal of a lead 3 made of a magnetic material are connected by a wire. In a method of manufacturing a semiconductor device which is electrically connected and sealed with a sealing body, an internal terminal portion of the lead 3 is magnetically bonded to an element forming surface of the semiconductor chip 1 with an insulating adhesive tape 2 interposed therebetween. Things. Also, when the electromagnet 7 is prepared and the element terminal of the semiconductor chip 1 is bonded to the internal terminal of the lead 3, the electromagnet 7
After the electromagnetic force is generated and both the semiconductor chip 1 and the lead 3 are bonded and fixed, the electromagnetic force of the electromagnet 7 is reduced and removed.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特に、半導体チップの素子形成面（主面）上
に絶縁性接着テープを介在させてリードを接着固定し、
前記半導体チップの外部端子とリードの内部端子とをワ
イヤーで電気的に接続し、封止体で封止する半導体装置
の製造方法に適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for bonding and fixing leads on an element forming surface (main surface) of a semiconductor chip with an insulating adhesive tape interposed therebetween.
The present invention relates to a technique effective when applied to a method of manufacturing a semiconductor device in which external terminals of the semiconductor chip and internal terminals of leads are electrically connected by wires and sealed by a sealing body.
【０００２】[0002]
【従来の技術】高密度化は従来から主要な技術課題の中
でも最重要な課題であった。そして、高密度化の実施例
としてＬＯＣ（Ｌead Ｏn Ｃhip）構造化が行われてき
た。このＬＯＣ型半導体装置は、例えば、特開昭６１−
２８７２３号公報に記載されるように、半導体チップの
素子形成面上に絶縁性接着テープを介在させてリードを
接着固定し、前記半導体チップの外部端子とリードの内
部端子とをワイヤーで電気的に接続し、封止体で封止す
る構造となっている。2. Description of the Related Art High density has conventionally been the most important of the major technical issues. LOC (Lead On Chip) structuring has been performed as an example of high density. This LOC type semiconductor device is disclosed in, for example,
As described in Japanese Patent No. 28723, a lead is bonded and fixed on an element forming surface of a semiconductor chip with an insulating adhesive tape interposed therebetween, and an external terminal of the semiconductor chip and an internal terminal of the lead are electrically connected by a wire. They are connected and sealed with a sealing body.
【０００３】このＬＯＣ構造では、半導体チップの素子
形成面上に絶縁性接着テープを介在させてリードを接着
固定し、前記半導体チップの外部端子（パッド）とリー
ドの内部端子（インナーリード）とをワイヤーで電気的
に接続したものを、モールド型の上型と下型との間に挟
んで型締めした後、型内に投入されたレジンタブレット
を加圧加熱して溶融させ、溶けたレジンにより封止する
ようになっている。In this LOC structure, leads are bonded and fixed on an element forming surface of a semiconductor chip with an insulating adhesive tape interposed therebetween, and external terminals (pads) of the semiconductor chip and internal terminals (inner leads) of the leads are connected. After electrically connecting by wire, sandwich the mold between the upper mold and the lower mold and clamp the mold, press and heat the resin tablet put in the mold, melt it, and use the melted resin It is designed to be sealed.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、前述の
従来の半導体装置の製造方法では、チップシュリング化
に伴い、半導体チップの外部端子（パッド）のピッチの
縮小がなされ、その結果、ＬＯＣリードの先端は、リー
ド幅及びピッチとも小さくなってきている。そのため、
インナーリードの先端部にねじれが発生して、ワイヤー
ボンディング時の圧着不良が生じるという問題があっ
た。However, in the above-described conventional method for manufacturing a semiconductor device, the pitch of the external terminals (pads) of the semiconductor chip is reduced in accordance with the shrinking of the chip. At the tip, both the lead width and the pitch are becoming smaller. for that reason,
There has been a problem that the tip of the inner lead is twisted, resulting in poor crimping during wire bonding.
【０００５】本発明の目的は、ＬＯＣリード自体を変更
することなく安定したワイヤーボンディングを行うこと
が可能な技術を提供することにある。An object of the present invention is to provide a technique capable of performing stable wire bonding without changing the LOC lead itself.
【０００６】本発明の他の目的は、微細化に対するリー
ドの幅を縮小することが可能な技術を提供することにあ
る。Another object of the present invention is to provide a technique capable of reducing the width of a lead for miniaturization.
【０００７】本発明の他の目的は、歩留を向上すること
が可能な技術を提供することにある。Another object of the present invention is to provide a technique capable of improving the yield.
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.
【００１０】（１）半導体チップの素子形成面上に絶縁
性接着テープを介在させて磁性体からなるリードを接着
固定し、前記半導体チップの外部端子と前記リードの内
部端子とをワイヤーで電気的に接続し、封止体で封止す
る半導体装置の製造方法であって、前記半導体チップの
素子形成面に絶縁性接着テープを介在させて前記リード
の内部端子部を電磁力を用いて接着固定するものであ
る。(1) A lead made of a magnetic material is bonded and fixed on an element forming surface of a semiconductor chip with an insulating adhesive tape interposed therebetween, and an external terminal of the semiconductor chip and an internal terminal of the lead are electrically connected by wires. A method of manufacturing a semiconductor device, wherein the semiconductor device is connected to the semiconductor chip and sealed with a sealing body, wherein an insulating adhesive tape is interposed on an element forming surface of the semiconductor chip, and an internal terminal portion of the lead is bonded and fixed using electromagnetic force. Is what you do.
【００１１】（２）半導体チップの素子形成面上に絶縁
性接着テープを介在させて磁性体からなるリードを接着
固定し、前記半導体チップの外部端子と前記リードの内
部端子とをワイヤーで電気的に接続し、封止体で封止す
る半導体装置の製造方法であって、電磁石を準備し、前
記半導体チップの素子形成面上とリードの内部端子部と
を接着固定する時、前記電磁石をリードの内部端子部の
上に載置して電磁力を発生させ、半導体チップとリード
の両者を固定させ、前記電磁石を上から押圧して接着固
定した後、前記電磁石の電磁力を消滅させて取り去るも
のである。(2) A lead made of a magnetic material is bonded and fixed on an element forming surface of the semiconductor chip with an insulating adhesive tape interposed therebetween, and an external terminal of the semiconductor chip and an internal terminal of the lead are electrically connected by wires. And a method of manufacturing a semiconductor device to be sealed with a sealing body, wherein an electromagnet is prepared, and when the element forming surface of the semiconductor chip and the internal terminal portion of the lead are adhered and fixed, the electromagnet is connected to the lead. Is placed on the internal terminal portion to generate an electromagnetic force to fix both the semiconductor chip and the lead, press and fix the electromagnet from above, and then remove and remove the electromagnetic force of the electromagnet. Things.
【００１２】前述した（１）及び（２）の手段によれ
ば、電磁力により半導体チップとリードの両者を吸着す
ることにより、リード先端部のねじれを電磁力による圧
力で矯正して前記両者を接着固定するので、ＬＯＣリー
ド自体を変更することなく安定したワイヤーボンディン
グを行うことができる。これにより、微細化に対するリ
ードの幅を縮小することができる。また、精度不良のリ
ードも使用できるため歩留を向上することができる。According to the above-mentioned means (1) and (2), both the semiconductor chip and the lead are attracted by the electromagnetic force, so that the torsion at the tip of the lead is corrected by the pressure due to the electromagnetic force, and the both are corrected. Since bonding and fixing are performed, stable wire bonding can be performed without changing the LOC lead itself. Thereby, the width of the lead for miniaturization can be reduced. Further, since a lead with poor accuracy can be used, the yield can be improved.
【００１３】以下、本発明について、図面を参照して実
施形態とともに詳細に説明する。Hereinafter, the present invention will be described in detail along with embodiments with reference to the drawings.
【００１４】[0014]
【発明の実施の形態】図１は本発明の実施形態に係る半
導体装置の全体構成の概略を示す断面図であり、図２は
半導体装置の封止体の上部を除去した半導体チップ、リ
ード、ボンディングワイヤーの構成を示す平面図であ
る。図１及び図２において、１は半導体チップ、２は絶
縁性接着テープ、３は磁性体からなるリード、４はワイ
ヤー、５は封止体（モールド樹脂）である。前記絶縁性
接着テープ３は、図３に示すように、ポリイミド等から
なる絶縁性テープ２Ａの両面にポリイミド系接着剤２Ｂ
を塗布したものである。前記磁性体からなるリード３の
材料としては、例えば、４２アロイ合金を用いる。FIG. 1 is a cross-sectional view schematically showing the overall structure of a semiconductor device according to an embodiment of the present invention. FIG. FIG. 3 is a plan view illustrating a configuration of a bonding wire. 1 and 2, 1 is a semiconductor chip, 2 is an insulating adhesive tape, 3 is a lead made of a magnetic material, 4 is a wire, and 5 is a sealing body (mold resin). As shown in FIG. 3, the insulating adhesive tape 3 has a polyimide adhesive 2B on both sides of an insulating tape 2A made of polyimide or the like.
Is applied. As a material of the lead 3 made of the magnetic material, for example, a 42 alloy alloy is used.
【００１５】本実施形態に係る半導体装置は、図１及び
図２に示すように、半導体チップ１の素子形成面（主
面）上に絶縁性接着テープ２を介在させてリード３を接
着固定し、前記半導体チップ１の外部端子（パッド）と
リード３の内部端子部（インナーリード）とをワイヤー
５で電気的に接続し、封止体（モールド樹脂）５で封止
したものである。In the semiconductor device according to the present embodiment, as shown in FIGS. 1 and 2, leads 3 are bonded and fixed on an element forming surface (main surface) of a semiconductor chip 1 with an insulating adhesive tape 2 interposed therebetween. The external terminals (pads) of the semiconductor chip 1 and the internal terminals (inner leads) of the leads 3 are electrically connected by wires 5 and sealed by a sealing body (mold resin) 5.
【００１６】図４及び図５は、本実施形態の半導体装置
の製造方法を詳細に説明するための横方向の断面図及び
縦方向の断面図であり、６は磁性体からなるリード３を
固定して加熱するための治具、７は電磁石である。FIGS. 4 and 5 are a horizontal sectional view and a vertical sectional view, respectively, for describing the method of manufacturing the semiconductor device according to the present embodiment in detail. Reference numeral 6 denotes a fixed lead 3 made of a magnetic material. A heating jig 7 is an electromagnet.
【００１７】本実施形態の半導体装置の製造方法は、図
４及び図５に示すように、治具６の上に半導体チップ１
を載置し、半導体チップ１の素子形成面上に絶縁性接着
テープ２を介在させてリード３の内部端子部（インナー
リード）を載置し、その上に電磁石７を載置し、該電磁
石７に電磁力を発生させ、この電磁力により、リード３
の内部端子部（インナーリード）を電磁石７に吸着して
固定し、該電磁石７を上から押圧して半導体チップ１の
素子形成面（主面）上に絶縁性接着テープ２を介在させ
てリード３を接着固定する。その後、前記電磁石７の電
磁力を消減させ、電磁石７を取り去る。次に、前記半導
体チップ１の外部端子（パッド）とリード３の内部端子
部（インナーリード）とをワイヤーボンディングを行っ
てワイヤー５で電気的に接続し、封止体（モールド樹
脂）５で封止する。As shown in FIGS. 4 and 5, the method of manufacturing a semiconductor device according to the present embodiment includes the steps of:
Is mounted, and the internal terminals (inner leads) of the leads 3 are mounted on the element forming surface of the semiconductor chip 1 with the insulating adhesive tape 2 interposed therebetween, and the electromagnet 7 is mounted thereon. 7 generates an electromagnetic force, and the electromagnetic force
The internal terminals (inner leads) of the semiconductor chip 1 are attracted and fixed to the electromagnet 7, and the electromagnet 7 is pressed from above to lead the semiconductor chip 1 on the element forming surface (main surface) with the insulating adhesive tape 2 interposed therebetween. 3 is adhesively fixed. Thereafter, the electromagnetic force of the electromagnet 7 is reduced, and the electromagnet 7 is removed. Next, the external terminals (pads) of the semiconductor chip 1 and the internal terminals (inner leads) of the leads 3 are electrically connected by wires 5 by wire bonding, and sealed by a sealing body (mold resin) 5. Stop.
【００１８】前記電磁石７の上からの押圧は、例えば、
公知のピストン機構、空気圧制御機構、カム，リンク等
を用いた移動機構を使用して行う。The electromagnet 7 is pressed from above, for example,
This is performed using a known piston mechanism, a pneumatic control mechanism, a moving mechanism using a cam, a link, and the like.
【００１９】以上の説明からわかるように、本実施形態
の半導体装置の製造方法によれば、前記半導体チップ１
の素子形成面上にリード３を固定して加熱するための治
具６に電磁石７を設け、前記半導体チップ１の素子形成
面上とリード３の内部端子部（インナーリード）とを接
着させる時、電磁石７に電磁力を発生させ、この電磁力
により、リード３の内部端子部（インナーリード）を電
磁石７に吸着して、該電磁石７を上から押圧して半導体
チップ１の素子形成面（主面）上に絶縁性接着テープ２
を介在させてリード３を接着固定する。その後、前記電
磁石７の電磁力を消減させ、電磁石７を取り去ることに
より、インナーリードの先端部のねじれを電磁力による
圧力で矯正して前記半導体チップ１とリード３の両者を
接着固定するので、ＬＯＣリード自体を変更することな
く安定したワイヤーボンディングを行うことができる。As can be seen from the above description, according to the method of manufacturing a semiconductor device of the present embodiment, the semiconductor chip 1
An electromagnet 7 is provided on a jig 6 for fixing and heating the leads 3 on the element forming surface of the semiconductor chip 1 and bonding the internal terminals (inner leads) of the leads 3 to the element forming surface of the semiconductor chip 1. Then, an electromagnetic force is generated in the electromagnet 7, and the internal force (inner lead) of the lead 3 is attracted to the electromagnet 7 by the electromagnetic force, and the electromagnet 7 is pressed from above to press the element formation surface of the semiconductor chip 1 ( Insulating adhesive tape 2 on the main surface)
The lead 3 is bonded and fixed with the interposition of. Thereafter, the electromagnetic force of the electromagnet 7 is reduced and the electromagnet 7 is removed, so that the torsion at the tip of the inner lead is corrected by the pressure of the electromagnetic force and both the semiconductor chip 1 and the lead 3 are bonded and fixed. Stable wire bonding can be performed without changing the LOC lead itself.
【００２０】また、インナーリードの先端部のねじれを
電磁力による圧力で矯正して前記半導体チップ１とリー
ド３の両者を接着固定するので、微細化に対するリード
３の幅を縮小することができる。Further, since the semiconductor chip 1 and the lead 3 are both bonded and fixed by correcting the torsion at the tip of the inner lead by electromagnetic force, the width of the lead 3 for miniaturization can be reduced.
【００２１】また、インナーリードの先端部のねじれを
電磁力による圧力で矯正して前記半導体チップ１とリー
ド３の両者を接着固定するので、精度不良のリード３も
使用でき、歩留を向上することができる。Further, since the torsion at the tip of the inner lead is corrected by the pressure of the electromagnetic force and both the semiconductor chip 1 and the lead 3 are bonded and fixed, the lead 3 with poor accuracy can be used, and the yield is improved. be able to.
【００２２】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.
【００２３】[0023]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、以
下の通りである。The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【００２４】（１）インナーリードの先端部のねじれを
電磁力による圧力で矯正するので、ＬＯＣリード自体を
変更することなく安定してワイヤーボンディングするこ
とができる。(1) Since the torsion at the tip of the inner lead is corrected by the pressure of the electromagnetic force, the wire bonding can be performed stably without changing the LOC lead itself.
【００２５】（２）インナーリードの先端部のねじれを
電磁力による圧力で矯正するので、微細化に対するリー
ドの幅を縮小することができる。(2) Since the torsion at the tip of the inner lead is corrected by the pressure of the electromagnetic force, the width of the lead for miniaturization can be reduced.
【００２６】（３）インナーリードの先端部のねじれを
磁力による圧力で矯正するので、精度不良のリードも使
用でき、歩留を向上することができる。(3) Since the torsion at the tip of the inner lead is corrected by a magnetic force, a lead with poor accuracy can be used, and the yield can be improved.
【図１】本発明の実施形態に係る半導体装置の全体構成
の概略を示す断面図である。FIG. 1 is a cross-sectional view schematically illustrating an overall configuration of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の実施形態に係る半導体装置の封止体の
上部を除去した半導体チップ、リード、ボンディングワ
イヤーの構成を示す平面図である。FIG. 2 is a plan view showing a configuration of a semiconductor chip, a lead, and a bonding wire from which an upper portion of a sealing body of the semiconductor device according to the embodiment of the present invention has been removed.
【図３】本発明の実施形態に係る半導体装置に用いる絶
縁性接着テープの構成を示す断面図である。FIG. 3 is a cross-sectional view illustrating a configuration of an insulating adhesive tape used in the semiconductor device according to the embodiment of the present invention.
【図４】本実施形態の半導体装置の製造方法を詳細に説
明するための横方向の断面図である。FIG. 4 is a lateral sectional view for describing in detail the method for manufacturing the semiconductor device of the present embodiment.
【図５】本実施形態の半導体装置の製造方法を詳細に説
明するための縦方向の断面図である。FIG. 5 is a vertical cross-sectional view for describing in detail the method for manufacturing a semiconductor device of the present embodiment.
１…半導体チップ、２…絶縁性接着テープ、３…磁性体
からなるリード、４…ワイヤー、５…封止体（モールド
樹脂）、６…治具、７…電磁石。DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Insulating adhesive tape, 3 ... Lead made of a magnetic material, 4 ... Wire, 5 ... Sealing body (mold resin), 6 ... Jig, 7 ... Electromagnet.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 有馬 英夫 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 三木野 博 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 塚田 和子 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Arima 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Hiroshi Mikino Josuihoncho, Kodaira-shi, Tokyo 5-2-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Kazuko Tsukada 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Semiconductor Division, Hitachi, Ltd.
Claims (2)
着テープを介在させて磁性体からなるリードを接着固定
し、前記半導体チップの外部端子と前記リードの内部端
子とをワイヤーで電気的に接続し、封止体で封止する半
導体装置の製造方法であって、前記半導体チップの素子
形成面に絶縁性接着テープを介在させて前記リードの内
部端子部を電磁力を用いて接着固定することを特徴とす
る半導体装置の製造方法。1. A lead made of a magnetic material is bonded and fixed on an element forming surface of a semiconductor chip with an insulating adhesive tape interposed therebetween, and an external terminal of the semiconductor chip and an internal terminal of the lead are electrically connected by wires. A method of manufacturing a semiconductor device which is connected and sealed with a sealing body, wherein an internal bonding portion of the lead is bonded and fixed by using an electromagnetic force on an element forming surface of the semiconductor chip with an insulating adhesive tape interposed therebetween. A method for manufacturing a semiconductor device, comprising:
着テープを介在させて磁性体からなるリードを接着固定
し、前記半導体チップの外部端子と前記リードの内部端
子とをワイヤーで電気的に接続し、封止体で封止する半
導体装置の製造方法であって、電磁石を準備し、前記半
導体チップの素子形成面上とリードの内部端子部とを接
着固定する時、前記電磁石をリードの内部端子部の上に
載置して電磁力を発生させ、前記半導体チップとリード
の両者を固定させ、前記電磁石を上から押圧して接着固
定した後、前記電磁石の電磁力を消滅させて取り去るこ
とを特徴とする半導体装置の製造方法。2. A lead made of a magnetic material is bonded and fixed on an element forming surface of a semiconductor chip with an insulating adhesive tape interposed therebetween, and an external terminal of the semiconductor chip and an internal terminal of the lead are electrically connected by wires. A method of manufacturing a semiconductor device in which an electromagnet is prepared and connected to an element forming surface of the semiconductor chip and an internal terminal portion of a lead by bonding the electromagnet to the lead. It is placed on the internal terminal to generate an electromagnetic force to fix both the semiconductor chip and the lead, press and fix the electromagnet from above, and then remove and remove the electromagnetic force of the electromagnet. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9030091A JPH10229160A (en) | 1997-02-14 | 1997-02-14 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9030091A JPH10229160A (en) | 1997-02-14 | 1997-02-14 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10229160A true JPH10229160A (en) | 1998-08-25 |
Family
ID=12294127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9030091A Pending JPH10229160A (en) | 1997-02-14 | 1997-02-14 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10229160A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006317321A (en) * | 2005-05-13 | 2006-11-24 | Denso Corp | Physical quantity sensor device |
| JP2007127673A (en) * | 2007-02-22 | 2007-05-24 | Matsushita Electric Ind Co Ltd | Rotational speed sensor |
-
1997
- 1997-02-14 JP JP9030091A patent/JPH10229160A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006317321A (en) * | 2005-05-13 | 2006-11-24 | Denso Corp | Physical quantity sensor device |
| JP2007127673A (en) * | 2007-02-22 | 2007-05-24 | Matsushita Electric Ind Co Ltd | Rotational speed sensor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH11260856A (en) | Semiconductor device and its manufacture and mounting structure of the device | |
| JP2001274316A (en) | Semiconductor device and manufacturing method thereof | |
| JP2000003988A (en) | Lead frame and semiconductor device | |
| JPH10229160A (en) | Method for manufacturing semiconductor device | |
| JP3259377B2 (en) | Semiconductor device | |
| JPS59181025A (en) | Semiconductor device | |
| JP3847432B2 (en) | Resin-encapsulated semiconductor device and manufacturing method thereof | |
| JP2589520B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JPS6313337A (en) | Process of mounting semiconductor element | |
| JPH0296342A (en) | Wire-bonding device | |
| JPH10229099A (en) | Method for manufacturing semiconductor device | |
| JP2582534B2 (en) | Method for manufacturing semiconductor device | |
| JPS6138193Y2 (en) | ||
| JPH0366152A (en) | Semiconductor integrated circuit module | |
| JP2595908B2 (en) | Semiconductor device | |
| JP2000031367A (en) | Semiconductor device and manufacturing method thereof | |
| JP3007806B2 (en) | Semiconductor device, method of manufacturing the same, and lead frame used therefor | |
| JPH0366150A (en) | Semiconductor integrated circuit device | |
| JPH01209733A (en) | Semiconductor device | |
| JPH05218271A (en) | Ic package | |
| JPS6060743A (en) | Lead frame | |
| JPH0595023A (en) | Lead frame for semiconductor-integratedcircuit sealing device use | |
| JPH06120287A (en) | Semiconductor device using lead frame and manufacturing method thereof | |
| JPH11162998A (en) | Semiconductor device and its manufacture | |
| JP2000332163A (en) | Semiconductor device and manufacturing method thereof |