JPH1022345A - Mounting method for work - Google Patents
Mounting method for workInfo
- Publication number
- JPH1022345A JPH1022345A JP17761896A JP17761896A JPH1022345A JP H1022345 A JPH1022345 A JP H1022345A JP 17761896 A JP17761896 A JP 17761896A JP 17761896 A JP17761896 A JP 17761896A JP H1022345 A JPH1022345 A JP H1022345A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- substrate
- height
- work
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000003825 pressing Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000005259 measurement Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 12
- 230000002950 deficient Effects 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 230000003028 elevating effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L2224/749—Tools for reworking, e.g. for shaping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75743—Suction holding means
- H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/758—Means for moving parts
- H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
- H01L2224/75822—Rotational mechanism
- H01L2224/75823—Pivoting mechanism
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
- Length Measuring Devices By Optical Means (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、バンプを介して基
板にワークを実装するワークの実装方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a work mounting method for mounting a work on a substrate via bumps.
【0002】[0002]
【従来の技術】図11は、従来の基板にチップを実装中
の側面図である。基板1の上面には電極2が形成されて
いる。またワークとしてのチップ3の下面にはバンプ4
が形成されている。チップ3を加圧ヘッド5のフローテ
ィング機構部6に真空吸着して保持し、バンプ4を電極
2に押し付けてチップ3を基板1に実装するようになっ
ている。2. Description of the Related Art FIG. 11 is a side view showing a state where a chip is mounted on a conventional substrate. The electrode 2 is formed on the upper surface of the substrate 1. A bump 4 is provided on the lower surface of the chip 3 as a work.
Are formed. The chip 3 is mounted on the floating mechanism 6 of the pressure head 5 by vacuum suction and held, and the bump 4 is pressed against the electrode 2 to mount the chip 3 on the substrate 1.
【0003】[0003]
【発明が解決しようとする課題】基板1はガラエポ樹脂
やセラミックなどによりプレート状に形成されている
が、基板1の上面にはうねりによる高低差hが生じやす
い。したがって従来方法においては、高低差hが小さい
場合は、フローティング機構部6が首ふりしてチップ3
を基板1の上面にならわせることにより吸収し、すべて
のバンプ4を電極2に着地させることができる。しかし
ながら高低差hが大きくなるとフローティング機構部6
では高低差hを完全に吸収できず、その結果、すべての
バンプ4は電極2に着地できずに(図11において、左
側から2番目と3番目のバンプ4を参照)導通不良の不
良品となってしまう問題点があった。The substrate 1 is formed in a plate shape from glass epoxy resin, ceramics, or the like, but the top surface of the substrate 1 tends to have a height difference h due to undulation. Therefore, according to the conventional method, when the height difference h is small, the floating mechanism 6 swings and the tip 3
Is absorbed by making the upper surface of the substrate 1 flat, and all the bumps 4 can land on the electrode 2. However, when the height difference h increases, the floating mechanism 6
In this case, the height difference h cannot be completely absorbed, and as a result, all the bumps 4 cannot land on the electrode 2 (see the second and third bumps 4 from the left side in FIG. 11). There was a problem that became.
【0004】したがって本発明は、基板の上面の大きな
うねりによる高低差に対応してワークの実装を行えるワ
ークの実装方法を提供することを目的とする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a work mounting method capable of mounting a work in response to a height difference due to a large undulation of the upper surface of a substrate.
【0005】[0005]
【課題を解決するための手段】本発明は、基板の上面の
高低差を計測手段により計測する工程と、計測された高
低差とバンプの高さを制御部で比較する工程と、基板の
複数個の電極上にバンプを形成する工程と、これらのバ
ンプに平坦化ツールを押し付けてこれらのバンプの上面
の高さを同一レベルにする工程と、ワークの下面に形成
された電極を前記バンプに着地させてワークを前記基板
に搭載する工程とからワークの実装方法を構成した。SUMMARY OF THE INVENTION The present invention comprises a step of measuring a height difference of an upper surface of a substrate by a measuring means, a step of comparing the measured height difference with a height of a bump by a control unit, A step of forming bumps on the individual electrodes, a step of pressing a flattening tool against these bumps to make the heights of the upper surfaces of these bumps the same level, and a step of attaching electrodes formed on the lower surface of the work to the bumps. The step of landing and mounting the work on the substrate constituted the method of mounting the work.
【0006】[0006]
【発明の実施の形態】本発明によれば、計測手段により
計測された基板の上面の高低差がバンプの高さよりも小
さい場合には、バンプに平坦化ツールを押し付けてすべ
てのバンプの上面の高さを同一レベルにし、これらのバ
ンプにワークのすべての電極を着地させて搭載する。ま
た高低差がバンプの高さよりも大きい場合には、ワーク
を基板に搭載してもワークの電極はバンプに着地できな
いので不良品として処理する。According to the present invention, when the height difference of the upper surface of the substrate measured by the measuring means is smaller than the height of the bumps, a flattening tool is pressed against the bumps and the upper surface of all the bumps is pressed. The height is set to the same level, and all the electrodes of the work are landed on these bumps and mounted. If the height difference is larger than the height of the bumps, the electrodes of the work cannot land on the bumps even if the work is mounted on the substrate.
【0007】以下、本発明の一実施の形態を図面を参照
しながら説明する。図1は本発明の実施の形態1のワー
クの実装装置の正面図である。また、図2、図3、図
4、図5、図6、図7は同ワークの実装工程図であっ
て、ワークの実装方法を工程順に示すものである。また
図8は、同基板が不良品の場合の説明図である。Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a front view of a work mounting apparatus according to a first embodiment of the present invention. 2, 3, 4, 5, 6, and 7 are mounting process diagrams of the work, and show a method of mounting the work in the order of processes. FIG. 8 is an explanatory diagram when the substrate is defective.
【0008】まず図1を参照して、ワークの実装装置の
全体構成を説明する。基板11は搬送路12に沿って右
方へピッチ送りされる。搬送路12の上方には、PSD
などの高さの計測手段13を備えた可動テーブル14、
ホーン15やキャピラリツール16などを備えたワイヤ
ボンダ17、平坦化ツール18を備えた平坦化手段1
9、ボンド塗布手段としてのディスペンサ20、チップ
21を真空吸着するダイコレット22を備えたダイボン
ダ23などが順に並設されている。25はコンピュータ
であり、上記各手段に接続されている。図2に示すよう
に、基板11の上面には電極24が多数形成されてい
る。基板11の上面にはうねりにより高低差hが生じて
いる。First, an overall configuration of a work mounting apparatus will be described with reference to FIG. The substrate 11 is pitch-fed to the right along the transport path 12. PSD above the transport path 12
A movable table 14 having a height measuring means 13 such as
A wire bonder 17 including a horn 15 and a capillary tool 16 and a flattening unit 1 including a flattening tool 18
9, a dispenser 20 as a bond applying means, a die bonder 23 having a die collet 22 for vacuum-sucking the chip 21, and the like are arranged in order. Reference numeral 25 denotes a computer, which is connected to each of the above units. As shown in FIG. 2, a large number of electrodes 24 are formed on the upper surface of the substrate 11. The height difference h is generated on the upper surface of the substrate 11 by undulation.
【0009】次に、図2〜図8を参照して、チップの実
装方法を説明する。まず図2に示すように、搬送路12
を搬送されてきた基板11を計測手段13の直下で停止
させる。そこで計測手段13を水平移動させながら、基
板11の上面にレーザ光Rを照射し、その反射光を受光
することにより、基板11の上面の高さを計測する。計
測値はコンピュータ25に入力される。そしてコンピュ
ータ25は基板11の上面の最大の高低差hを計算し、
かつ次の工程で形成されるバンプの高さHとこの高低差
hを比較する。そして、高低差hがバンプの高さHより
も小さいときは、以下の作業が続行されるが、バンプの
高さHよりも大きいときは以下の作業は中止され、この
基板11は不良品としてラインから除外される。Next, a method of mounting a chip will be described with reference to FIGS. First, as shown in FIG.
Is stopped immediately below the measuring means 13. Therefore, while horizontally moving the measuring means 13, the upper surface of the substrate 11 is irradiated with the laser beam R and the reflected light is received to measure the height of the upper surface of the substrate 11. The measured value is input to the computer 25. Then, the computer 25 calculates the maximum height difference h of the upper surface of the substrate 11,
The height H of the bump formed in the next step is compared with this height difference h. When the height difference h is smaller than the height H of the bumps, the following operation is continued. However, when the height difference h is larger than the height H of the bumps, the following operation is stopped. Excluded from the line.
【0010】さて、図2の工程において高低差hはバン
プの高さH(図3)よりも小さく、基板11は良品と判
定されると、基板11は次のワイヤボンダ17の下方へ
送られ、ワイヤボンディング手段により基板11の電極
24上にバンプ28が次々に形成される。In the process shown in FIG. 2, the height difference h is smaller than the height H of the bump (FIG. 3). If the board 11 is determined to be non-defective, the board 11 is sent below the next wire bonder 17, The bumps 28 are sequentially formed on the electrodes 24 of the substrate 11 by wire bonding means.
【0011】図3はその様子を示すものであって、キャ
ピラリツール16の下端部から導出されたワイヤ27の
下端部にトーチ26を接近させ、トーチ26に高電圧を
印加してワイヤ27の下端部との間に電気的スパークを
発生させて、ワイヤ27の下端部にボール28’を形成
する。そしてキャピラリツール16に下降・上昇動作を
行わせてボール28’を電極24にボンディングし、バ
ンプ28を形成する。なおバンプ28の高さHはほぼ一
定であり、既知値としてコンピュータ25のメモリに予
め入力されているので、上述した高低差hとの比較をコ
ンピュータ25で行えるものである。次に基板11は平
坦化手段19の直下へ送られる。そしてそこで平坦化ツ
ール18が下降してそのフラットな下面がすべてのバン
プ28に押し付けられ(図4において、鎖線で示す平坦
化ツール18を参照)、すべてのバンプ28の高さは同
一レベルLにされる(図5)。FIG. 3 shows this state. The torch 26 is made to approach the lower end of the wire 27 led out from the lower end of the capillary tool 16, and a high voltage is applied to the torch 26 to lower the lower end of the wire 27. A ball 28 'is formed at the lower end of the wire 27 by generating an electrical spark between the wire 27 and the wire. Then, the ball 28 ′ is bonded to the electrode 24 by causing the capillary tool 16 to perform a descending / elevating operation to form a bump 28. Since the height H of the bump 28 is substantially constant and is previously input as a known value into the memory of the computer 25, the computer 25 can compare the height H with the above-described height difference h. Next, the substrate 11 is sent directly below the flattening means 19. Then, the flattening tool 18 is lowered and its flat lower surface is pressed against all the bumps 28 (see the flattening tool 18 shown by a dashed line in FIG. 4), and the height of all the bumps 28 becomes the same level L. (FIG. 5).
【0012】図8は、上記高低差hがバンプ28の高さ
Hよりも大きい場合を示している。この場合、平坦化ツ
ール18はすべてのバンプ28に着地できないので、す
べてのバンプ28の高さを同一レベルLにすることはで
きず、後述するチップの搭載作業において、チップの電
極をすべてのバンプ28に着地させることはできないこ
ととなる。よってこのような基板11は、不良品として
上述したようにラインから除去する。なお図8では、平
坦化ツール18は左側から2番目のバンプ28に着地で
きず、このバンプ28を平坦化できない。FIG. 8 shows a case where the height difference h is larger than the height H of the bump 28. In this case, since the planarization tool 18 cannot land on all the bumps 28, the heights of all the bumps 28 cannot be set to the same level L. It will not be possible to land on 28. Therefore, such a substrate 11 is removed from the line as described above as a defective product. In FIG. 8, the flattening tool 18 cannot land on the second bump 28 from the left and cannot flatten the bump 28.
【0013】さて、バンプ28の上面を平坦化された基
板11は、ディスペンサ20の直下へ送られる。そこで
ディスペンサ20からボンド29が吐出される(図
6)。ボンド29はすべてのバンプ28を覆うように基
板11の上面に塗布される。次に基板11はダイボンダ
23の直下へ送られ、ダイコレット22に真空吸着して
保持されたチップ21が搭載される(図7)。チップ2
1の下面にはバンプ30が突設されており、バンプ30
を基板11側のバンプ28に着地させて搭載される。次
いでこの基板11は加熱炉(図外)へ送られ、ボンド2
9を加熱して硬化させることにより全工程は終了する。
なおボンド29を硬化させる方法としては、ダイコレッ
ト22もしくは基板下受けブロック(図示せず)に加熱
用のヒータを取り付け、ダイボンダ23で搭載と硬化を
一度に行ってもよい。The substrate 11 having the upper surface of the bump 28 flattened is sent directly below the dispenser 20. Then, the bond 29 is discharged from the dispenser 20 (FIG. 6). The bond 29 is applied to the upper surface of the substrate 11 so as to cover all the bumps 28. Next, the substrate 11 is sent to a position directly below the die bonder 23, and the chip 21 held by vacuum suction on the die collet 22 is mounted (FIG. 7). Chip 2
1 has a bump 30 protruding from the lower surface thereof.
Are landed on the bumps 28 on the substrate 11 and mounted. Next, the substrate 11 is sent to a heating furnace (not shown),
The entire process is completed by heating and curing 9.
As a method of curing the bond 29, a heater for heating may be attached to the die collet 22 or the substrate support block (not shown), and mounting and curing may be performed at once by the die bonder 23.
【0014】図9および図10は、本発明の実施の形態
2のワークの実装工程図である。図9および図10は、
実施の形態1の図7の工程に対応している。この実施の
形態2では、実施の形態1の図6の工程において、ディ
スペンサ20によりボンド29を塗布したのに代えて、
異方性導電テープ(以下、ACFという)32を平坦化
されたバンプ28上に貼着している。そして図9に示す
ように、チップ21の電極33を基板11のバンプ28
に位置合わせして、図示しない加熱手段により熱を加え
つつ、ダイコレット22でACF32を押し潰しながら
チップ21を基板11に搭載し、チップ21の電極33
を基板11のバンプ28に押し付ける(図10)。する
と熱によってACF32は流動化した後、硬化し、チッ
プ21は基板11にボンディングされる。なおこのチッ
プ21の電極33にはバンプは形成されていない。FIGS. 9 and 10 are process diagrams for mounting a workpiece according to the second embodiment of the present invention. FIG. 9 and FIG.
This corresponds to the step of FIG. 7 of the first embodiment. In the second embodiment, instead of applying the bond 29 by the dispenser 20 in the process of FIG. 6 of the first embodiment,
An anisotropic conductive tape (hereinafter, referred to as ACF) 32 is stuck on the flattened bumps 28. Then, as shown in FIG. 9, the electrodes 33 of the chip 21 are connected to the bumps 28 of the substrate 11.
The chip 21 is mounted on the substrate 11 while crushing the ACF 32 with the die collet 22 while applying heat by a heating means (not shown).
Is pressed against the bumps 28 on the substrate 11 (FIG. 10). Then, the ACF 32 is fluidized by heat and then hardened, and the chip 21 is bonded to the substrate 11. No bumps are formed on the electrodes 33 of the chip 21.
【0015】本発明は上記実施の形態に限定されないの
であって、例えば計測手段をワイヤボンダに組み込み、
バンプを形成す直前に基板の上面の高低差を計測しても
よく、あるいはバンプはクリーム半田を用いるスクリー
ン印刷法や導電性ボールを用いる工法、さらにメッキ法
等により形成してもよいものである。The present invention is not limited to the above embodiment. For example, the measuring means is incorporated in a wire bonder,
The height difference of the upper surface of the substrate may be measured immediately before the formation of the bump, or the bump may be formed by a screen printing method using cream solder, a construction method using conductive balls, or a plating method. .
【0016】[0016]
【発明の効果】本発明は、チップなどのワークを基板に
搭載するのに先立って、計測手段により基板の上面の高
低差を計測し、高低差がバンプの高さよりも小さい場合
には、バンプに平坦化ツールを押し付けてすべてのバン
プの上面の高さを同一レベルにしたうえでワークを基板
に実装し、また高低差がバンプの高さよりも大きい場合
には、ワークを基板に搭載してもワークの電極はバンプ
に着地できないので不良品として処理するようにしてい
るので、良品のみの生産が可能となり、不良品を無駄に
生産するのを解消できる。According to the present invention, prior to mounting a work such as a chip on a substrate, the height difference of the upper surface of the substrate is measured by a measuring means. If the height difference is smaller than the height of the bump, the bump is measured. Press the flattening tool to make the top surface of all the bumps the same level, then mount the work on the board.If the height difference is larger than the height of the bump, mount the work on the board. Also, since the electrodes of the work cannot land on the bumps, they are treated as defectives, so that only non-defective products can be produced, and wasteful production of defective products can be eliminated.
【図1】本発明の実施の形態1のワークの実装装置の正
面図FIG. 1 is a front view of a work mounting apparatus according to a first embodiment of the present invention.
【図2】本発明の実施の形態1のワークの実装工程図FIG. 2 is a mounting process diagram of a work according to the first embodiment of the present invention;
【図3】本発明の実施の形態1のワークの実装工程図FIG. 3 is a mounting process diagram of the work according to the first embodiment of the present invention;
【図4】本発明の実施の形態1のワークの実装工程図FIG. 4 is a process diagram for mounting a workpiece according to the first embodiment of the present invention;
【図5】本発明の実施の形態1のワークの実装工程図FIG. 5 is a process diagram of mounting a workpiece according to the first embodiment of the present invention;
【図6】本発明の実施の形態1のワークの実装工程図FIG. 6 is a mounting process diagram of the workpiece according to the first embodiment of the present invention.
【図7】本発明の実施の形態1のワークの実装工程図FIG. 7 is a process diagram of mounting a workpiece according to the first embodiment of the present invention;
【図8】本発明の実施の形態1の基板が不良品の場合の
説明図FIG. 8 is an explanatory diagram when the substrate according to the first embodiment of the present invention is a defective product;
【図9】本発明の実施の形態2のワークの実装工程図FIG. 9 is a process diagram of mounting a work according to the second embodiment of the present invention.
【図10】本発明の実施の形態2のワークの実装工程図FIG. 10 is a mounting process diagram of a work according to the second embodiment of the present invention.
【図11】従来の基板にチップを実装中の側面図FIG. 11 is a side view showing a state where a chip is mounted on a conventional substrate.
11 基板 13 計測手段 17 ワイヤボンダ 18 平坦化ツール 19 平坦化手段 20 ディスペンサ 21 ワーク 23 ダイボンダ 24 電極 28 バンプ 29 ボンド 30 バンプ 32 ACF 33 電極 DESCRIPTION OF SYMBOLS 11 Substrate 13 Measuring means 17 Wire bonder 18 Flattening tool 19 Flattening means 20 Dispenser 21 Work 23 Die bonder 24 Electrode 28 Bump 29 Bond 30 Bump 32 ACF 33 Electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/92 604T ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical indication location H01L 21/92 604T
Claims (1)
する工程と、計測された高低差とバンプの高さを制御部
で比較する工程と、基板の複数個の電極上にバンプを形
成する工程と、これらのバンプに平坦化ツールを押し付
けてこれらのバンプの上面の高さを同一レベルにする工
程と、ワークの下面に形成された電極を前記バンプに着
地させてワークを前記基板に搭載する工程と、を含むこ
とを特徴とするワークの実装方法。A step of measuring a height difference of an upper surface of a substrate by a measuring unit; a step of comparing the measured height difference with a height of a bump by a control unit; and forming a bump on a plurality of electrodes of the substrate. And pressing a flattening tool on these bumps to make the heights of the upper surfaces of these bumps the same level, and landing the electrodes formed on the lower surface of the work on the bumps to transfer the work to the substrate. A mounting method of a work, comprising: mounting.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17761896A JP3244001B2 (en) | 1996-07-08 | 1996-07-08 | Work mounting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17761896A JP3244001B2 (en) | 1996-07-08 | 1996-07-08 | Work mounting method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH1022345A true JPH1022345A (en) | 1998-01-23 |
JP3244001B2 JP3244001B2 (en) | 2002-01-07 |
Family
ID=16034161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17761896A Expired - Fee Related JP3244001B2 (en) | 1996-07-08 | 1996-07-08 | Work mounting method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3244001B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1047956C (en) * | 1994-01-26 | 2000-01-05 | 北京大学 | Method for prepn. of wheat alcohol-dissolved protein molecular microcapsule |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105308732B (en) * | 2013-06-24 | 2018-11-27 | 亮锐控股有限公司 | Method and corresponding electronic structure including the manufacture electronic structure by planarization reduction welded gasket topological variation |
-
1996
- 1996-07-08 JP JP17761896A patent/JP3244001B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1047956C (en) * | 1994-01-26 | 2000-01-05 | 北京大学 | Method for prepn. of wheat alcohol-dissolved protein molecular microcapsule |
Also Published As
Publication number | Publication date |
---|---|
JP3244001B2 (en) | 2002-01-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5813115A (en) | Method of mounting a semiconductor chip on a wiring substrate | |
US4970365A (en) | Method and apparatus for bonding components leads to pads located on a non-rigid substrate | |
US7726546B2 (en) | Bonding apparatus and bonding method | |
US6172422B1 (en) | Semiconductor device and a manufacturing method thereof | |
US3724068A (en) | Semiconductor chip packaging apparatus and method | |
CN1051641C (en) | Semiconductor and its producing method | |
US3531852A (en) | Method of forming face-bonding projections | |
JPH04348540A (en) | Flip chip bonder | |
KR102363436B1 (en) | Device and method of laser compression bonding for semiconductor chip | |
JPH06349892A (en) | Manufacture of semiconductor device | |
JP4489524B2 (en) | Semiconductor device manufacturing method and paste coating apparatus | |
JP3244001B2 (en) | Work mounting method | |
WO1998047175A1 (en) | Process for manufacturing semiconductor device and semiconductor component | |
US11145617B2 (en) | Semiconductor structure | |
JP2793766B2 (en) | Conductive paste transfer method | |
JP3388152B2 (en) | Adhesive coating method and adhesive coating device | |
US5899375A (en) | Bump bonder with a discard bonding area | |
JP3368811B2 (en) | Mounting method of work with bump | |
JPH05291260A (en) | Forming method for bump | |
JPH07249897A (en) | Electronic component mounting apparatus | |
CN110739228A (en) | method for quickly mounting BGA chip | |
JP3253761B2 (en) | Outer bonding apparatus and method | |
JPH06124952A (en) | Bump forming method for semiconductor chip | |
JPH10223687A (en) | Method and device of manufacture of flip-chip mounting module | |
JP2504466B2 (en) | Thermocompression head |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |