JPH10222442A - Asynchronous data transmitter-receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of a memory and to reduce a chip area by multiplexing and decoding an address count signal on the reading/writing of a transmission/reception selection part and outputting it to a selection FIFO memory part. SOLUTION: One of first and second FIFO memory parts 40 and 41 and the selection FIFO memory part 42 is selected by the logic of first and second FIFO controller selection parts 48 and 49 and the transmission/reception operation of data is executed. When the selection FIFO memory part 42 is selected, first and second transmission/reception selection parts 46 and 47 select a transmission or reception mode by a transmission enable signal and a reception enable signal and data is written and read. Since a system operates at a half- duplex mode (namely, at an infrared communication mode), the transmission enable signal and the reception enable signal are prevented from simultaneously being enabled. Thus, one memory can be used at the time of transmission and reception.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission / reception device, and more particularly to an asynchronous data transmission / reception device capable of reducing a memory capacity and a chip area.

[0002]

2. Description of the Related Art Generally, most modules in a system employ a CPU to process many operations individually. When exchanging data between each module, it has a relationship with other modules. that time,
There are a synchronous method for synchronizing the data processing clock and an asynchronous method for processing data asynchronously without synchronizing. The synchronization method has a drawback in that it is necessary to synchronize between the two modules, which requires a lot of additional circuits, thereby reducing the processing speed of the system. On the other hand, the asynchronous method is advantageous in terms of speed and cost because the read module and the write module use different input / output buffers.

Hereinafter, a conventional asynchronous transmitting / receiving apparatus (UART) will be described with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a conventional asynchronous transmission / reception device using a FIFO memory, which does not perform infrared communication, and FIG. 2 is a conventional transmission / reception device using a FIFO memory, capable of performing 4 Mbps infrared communication. FIG. Infrared communication is used, for example, when exchanging data between PCs arranged in a short distance, and is used in a half-duplex mode because transmission and reception cannot be performed simultaneously. A UART that does not use infrared communication supports a full-duplex mode that allows simultaneous reception and transmission.

FIG. 1 is a block diagram of a UART that does not perform infrared communication, and each of a receiving end and a transmitting end has a 16-byte FI.
The FO memories 9 and 10 are connected. The read (READ) counters 1 and 3 and the write (WRITE) counters 2 and 4 of the transmitting end or the receiving end are respectively Tx-RD,
When the signals of Rx-RD, Tx-WR, and Rx-WR are input, each counter performs a counting operation. The read decoders 5, 7 and the write decoder 6, which are respectively connected to the read counter and the write counter,
Numeral 8 decodes the value of the counter, accesses the Tx-FIFO memory 9 or the Rx-FIFO memory 10, reads out the data, and writes the data therein. A Tx-MUX 11 for multiplexing the signals of the read decoder 5 and the write decoder 6 is connected to the transmitting end. Also, the receiving end has a read decoder 7.
And Rx-MUX for multiplexing the signals of the write decoder 8
12 are connected.

On the other hand, in the case of a UART capable of performing 4 Mbps infrared communication, as shown in FIG. 2, a 32-byte FIFO memory is required at each of the receiving end and the transmitting end. At the transmitting end, when the Tx-RD signal is input, the read counter 13 performs a counting operation. The read decoder 14 outputs the address of the Tx-FIFO memory 21 to be read based on the count signal of the read counter 13, and outputs the 32-byte Tx-FIFO memory 21.
Is read. When the Tx-WR signal is input, the write counter 15 performs a counting operation,
The write decoder 16 outputs an address to be written based on the count signal of the write counter 15 and outputs
Write to the byte Tx-FIFO memory 21. A Tx-MUX 23 that multiplexes and outputs signals from the read decoder 14 and the write decoder 16 is connected to the transmission end. At the receiving end, when the Rx-RD signal is input, the read counter 17 performs a counting operation, and the read decoder 18 outputs the address of the Rx-FIFO memory 22 to be read based on the count signal of the read counter 17, and outputs a 32-byte data. The data in the Rx-FIFO memory 22 is read. Then, when the Rx-WR signal is input,
The write counter 19 performs a count operation, and the write decoder 20 outputs a write address based on the count signal of the write counter 19 and writes the address to the 32-byte Rx-FIFO memory 22. An Rx-MUX 24 that multiplexes and outputs signals from the read decoder 18 and the write decoder 20 is connected to the receiving end.

[0006] The UART supports a full-duplex mode when infrared communication is not used, and supports a half-duplex mode when infrared communication is used.

[0007]

The UART of the prior art
In order to support the 4 Mbps infrared communication, the receiving end and the transmitting end each have a large F of 32 bytes.
I use IFO memory. Therefore, the size of a chip constituting the circuit is large. SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the above-mentioned conventional asynchronous data transmitting and receiving apparatus, and has as its object to reduce the memory area and the chip area to reduce the chip area. Is to provide.

[0008]

SUMMARY OF THE INVENTION An asynchronous data transmission / reception device of the present invention, which has a reduced memory capacity while supporting infrared communication, has first and second FIFO memory units used for input / output of data to be transmitted / received. , The first and second FIFs
A selected FIFO memory unit selected and used when the O memory unit is full, and first and second FIFOs for counting and outputting addresses related to data transmission or reception.
A controller selection unit, and the first data reception mode in a data reception mode.
A first multiplexing / decoding unit that multiplexes and decodes an address count signal of a FIFO controller selecting unit and outputs the multiplexed and decoded address count signal to a first FIFO memory; and multiplexes an address count signal of the second FIFO controller selecting unit in a data transmission mode. And decoding the second F
A second multiplexing / decoding unit for outputting to the IFO memory, and judging whether the mode is the transmission mode or the reception mode when using the selected FIFO selection unit, and outputting the respective write / read address count signals. A first and second transmission / reception selecting unit, and a third multiplexing / decoding that multiplexes and decodes an address count signal related to reading / writing of the first and second transmission / reception selecting units and outputs the multiplexed and decoded address count signal to a selected FIFO memory unit. And a unit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an asynchronous data transmitting / receiving apparatus according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 3 shows a UAR using the FIFO memory of the present embodiment.
It is a block diagram of T. This embodiment for reducing the capacity of the FIFO memory of the UART supporting the 4 Mbps infrared communication includes a first FIFO memory 40 having a capacity of 16 bytes used for input / output of reception data, and a 16-byte capacity used for input / output of transmission data. A second FIFO memory 41 having a capacity and a selection FIFO memory 42 used in common with the first FIFO memory 40 or the second FIFO memory 41 when data is selectively output in the infrared communication mode are provided. The selected FIFO memory 42 is a memory that is used instead of the first FIFO memory 41 and the second FIFO memory 42 when they are full in the infrared communication mode. Further, in the present embodiment, the first multiplexing / decoding unit 4
3, the second multiplexing / decoding unit 44, the third multiplexing /
Decoding section 45, first transmission / reception selection section 46, second transmission / reception selection section 47, first FIFO controller selection section 4
8, a second FIFO controller selection unit 49 is provided. The first FIFO controller selecting unit 48 outputs a read (RD) signal based on data transmission / reception and a write (W) signal.
R) signal, the address of the first FIFO memory 40 is counted and an address count signal (WR_fi) is generated.
fo, RD_fifo) and the address count signal (WR_Sel_fi) of the selected FIFO memory 42.
fo, RD_Sel_fifo). The second FIFO controller selection unit 49 also outputs a read (RD) signal due to data transmission / reception and a write (W
R) signal, the address of the second FIFO memory 40 is counted and an address count signal (WR_fi) is generated.
fo, RD_fifo) and the address count signal (WR_Sel_fi) of the selected FIFO memory 42.
fo, RD_Sel_fifo). Address count signal of selected FIFO memory 42 (WR_Sel_fifo, RD_Sel_fifo)
Is output in the infrared communication mode.

The first multiplexing / decoding unit 43 includes a control signal (control_control) related to a data reception mode.
Rx), the read / write address count signal (WR_fi) of the first FIFO controller selecting unit 48.
fo, RD_fifo) and outputs a 16-bit address to the first FIFO memory 40. The second multiplexing / decoding unit 44 receives an address count signal (WR-fifo, WR-fifo, WR) for reading / writing of the second FIFO controller selecting unit 49 according to a control signal (control-Tx) for a data transmission mode.
RD-fifo) is multiplexed and decoded to obtain 1
The 6-bit address is output to the second FIFO memory unit 41.

The first transmission / reception selecting section 46 has a write address count signal (WR_Sel) for transmitting / receiving data during infrared communication of the first FIFO controller selecting section 48.
_Fifo) and a write address count signal (WR_Sel_fifo) related to data transmission and reception during infrared communication of the second FIFO controller selecting unit 49, and a transmission / reception enable signal (Tx_en, Rx_e).
It is determined whether the mode is the transmission mode or the reception mode according to n), and one of the write address count signals is output to the selected FIFO memory unit 42. The second transmission / reception selection unit 47 includes a read address count signal (RD_Sel_fifo) related to data transmission / reception of the first FIFO controller 48 during infrared communication, and a read address count signal (RD_Sel_fif) related to data transmission / reception of the second FIFO controller selection unit 49 during infrared communication.
o) is input and the transmission / reception enable signal (Tx_e)
(n, Rx_en) to determine whether the mode is the transmission mode or the reception mode, and outputs one of the address count signals to the selected FIFO memory unit 42. The third multiplexing / decoding unit 45 includes a data transmission / reception selection signal (control_
Sel), multiplexes and decodes the address count signals related to reading / writing of the first and second transmission / reception selecting units 46 and 47, and outputs a 16-bit address to the selected FIFO memory unit 42.

Next, the first FIFO controller selecting section 4
8. The detailed configuration of the second FIFO controller selection unit 49 will be described. FIG. 4 is a detailed configuration diagram of the FIFO controller selection units 48 and 49 of the present embodiment. When infrared communication is used, the half-duplex signal shown is enabled, and when infrared communication is not performed, the half-duplex signal is not enabled.
That is, the FIFO controller selection unit is used in the full-duplex mode unless the half-duplex signal is enabled. In the case of the full-duplex mode, only an address count signal (WR_fifo, RD_fifo) relating to reading / writing in a state not supporting infrared communication is output,
Only the first and second FIFO memory units 40 and 41 are used. On the other hand, when the half-duplex signal is enabled, the address count signals (WR_Sel_fifo, RD_Sel) related to reading / writing in the infrared communication mode state.
_Fifo) so that the selected FIFO memory unit 42 is also used. The details will be described below.

As shown, the first and second FIFO controller selection sections 48 and 49 have a first FIFO controller 50 and a second FIFO controller 51, respectively. These receive a read / write enable signal (WR_en, RD_en) and a read / write signal (WR / RD) and read / write address count signals (WR_fifo, RD_fi).
fo) and a full-duplex or half-duplex comparison signal (f
output the output signals (ull 1, 2) (Empty 1, 2).
52 is a half-duplex mode controller, which is a first FIFO
The read address count signal (R
D_fifo) and the half-duplex mode comparison signal (Empty 2) of the second FIFO controller 51, when the half-duplex signal is enabled, the AND gates 62, 6
3 to the second FIFO controller 51, and a write enable signal can be given to operate the second FIFO controller 51. Full-duplex or half-duplex comparison signal (F
ull 1,2) (Empty 1,2) are the first and second
The signals are multiplexed by the MUXs 53 and 54 and output, respectively, and sent to the other party such as an external controller.

Hereinafter, the detailed configuration of the FIFO controller will be described with reference to FIG. The FIFO controller is
A read counter 56 that outputs an address count signal (RD_fifo) related to reading by a read enable signal (RD_en) and a write counter 55 that outputs an address count signal (RW_fifo) related to writing by a write enable signal (WR_en) are provided. These counters are conventionally the same as the counters described in the circuits of FIGS. 1 and 2, for example. Further, a first comparing unit 57 that compares the MSB of the write counter 55 with the MSB of the read counter 56 and outputs the comparison value, an address count signal related to writing of the write counter 55, and a count signal related to reading of the read counter 56 And a second comparing unit 58 that compares the values of the two and outputs the comparison value. That is, the first comparing unit 57 compares the MSBs of both counters, and outputs an output, for example, “high” when they are equal. The second comparing section 58 compares the count values of both counters and outputs the same if they are equal. The outputs of the first and second comparators 57 and 58 are input to a first AND gate, and the inverted signal of the output of the first comparator 57 and the output of the second comparator 58 are input to a second AND gate. You. An output of the first AND gate outputs a half-duplex comparison signal (empty), and a second AND gate outputs a full-duplex comparison signal (full). That is, if the MSBs of both counters are equal to the count value, a half-duplex signal enmty is output, and if the count values are equal and the MSBs are different, a full-duplex signal full is output.

Further, a detailed configuration of the half-duplex mode controller 52 of the FIFO controller selection unit shown in FIG. 4 will be described. The counter 59 operates using a signal obtained by inverting the half-duplex comparison signal (empty 2) of the second FIFO controller 51 as an enable signal, and the RD_count described above.
And outputs a high signal when the value and the address count value are 15. That is, when the final address is output, a high signal is output (in the embodiment, a 4-bit counter). The first latch unit 60 is enabled by a half-duplex comparison signal (empty 2), and
The full-duplex comparison signal (full) of the FIFO controller 50
l 1) is latched and output. The high signal from the counter 59 enables the second latch unit 61 to latch and output the output value of the first latch unit 60. The output of the first latch unit and the half-duplex signal output from the system controller (not shown) are logically operated by the second AND gate 63 and output to the RD of the second FIFO controller 51. That is, when infrared communication is selected, when the last address is counted, RD_enable of the second FIFO controller 51 is enabled. Also,
The half-duplex signal output from the system controller (not shown) is logically operated by the first AND gate 62 with the full-duplex signal (full 1) of the first FIFO controller 50, and WR_enab of the second FIFO controller 51
Output to le. The third AND gate 64 is connected to the first and second FIs.
A signal (f) related to full duplex of the FO controllers 50 and 51
logical 1 and 2 are output. First,
The signals (empty 1 and 2) related to half duplex of the second FIFO controllers 50 and 51 are logically operated by the OR gate 65 and output to the first MUX.

The asynchronous data transmission / reception device configured as described above includes the first and second FIFO controllers 50,
51 outputs an address count signal relating to reading and writing, and outputs the MSB of the count value to the first comparator 5.
7 and compare the count value with the second comparator 5
8 to output a signal for the full-duplex or half-duplex mode. With this logic, the 32-byte receive FI
The data transmission / reception operation supported by using the FO memory and the 32-byte transmission FIFO memory is performed by using a 16-byte FIFO.
It is designed to be supported by three O memories. That is, in the data transmission / reception operation, when infrared communication is not performed, only the first FIFO controller 50 is used because the half-duplex signal is low, and therefore, only the first and second memory units 40 and 41 are used. However, when the half-duplex signal is high, not only the first FIFO controller 50 but also the second FIFO controller 51 operates, so that the selected FIFO memory 42 is used. In that case, the first and second FIFO memory units 40, 4
1 is not completely full, the data transmission / reception operation is performed using only the first and second FIFO memory units 40 and 41, and when the first and second FIFO memory units 40 and 41 are completely full, the selected FIFO memory unit 42 is further used to perform data transmission / reception operations. The first and second FIF
O memory units 40 and 41, and selected FIFO memory unit 4
The logic for selecting 2 is generated by the first and second FIFO controller selecting sections 48 and 49. The first and second above
FIG. 6 shows operation waveforms of the FIFO controller selection sections 48 and 49.

Next, the operation of the asynchronous data transmitting / receiving apparatus of the present invention will be described in detail. If the asynchronous data transceiver is in full-duplex mode (not in infrared communication mode), half-duplex mode is disabled,
16-byte first FIFO memory 40 and second FIFO
The data transmission / reception operation is performed using only the memory unit 41. When the half-duplex signal is enabled to perform the infrared communication, (fu) of the first FIFO controller 50
11) The signal is enabled, and the second FIFO controller 51 also generates a write address count signal according to the latch signals of the first and second latch units 60 and 61. According to the logic of the first and second FIFO controller selecting sections 48 and 49 as described above, the first and second FIFO controllers are selected.
One of the FIFO memory units 40 and 41 and the selected FIFO memory unit 42 is selected to perform the data transmission / reception operation. Then, the selected FIFO memory unit 42
Is selected, the first and second transmission / reception selecting units 46,
At 47, the transmission or reception mode is selected by the transmission enable signal (Tx-en) and the reception enable signal (Rx-en) to write or read data. In this case, since the present embodiment operates in the half-duplex mode (that is, in the case of the infrared communication mode), the transmission enable signal and the reception enable signal are not enabled at the same time. And can be used for receiving respectively.

[0018]

As described above, the UART of the present invention is divided into a full-duplex mode and a half-duplex mode (infrared communication is supported). That is, the FIF at the transmitting / receiving end
O Selected and used when memory becomes full 16
Data can be transmitted and received using a byte selection FIFO memory. Therefore,
It does not require two conventional 32-byte memories,
Operation is possible with three 6-byte memories. That is, even if the memory capacity is small, data can be read and written at a high data transmission rate of 4 Mbps, which has the effect of reducing the size of the chip of the data transmitting and receiving device.

[Brief description of the drawings]

FIG. 1 UAR that does not support the infrared communication of the conventional technology
FIG. 3 is a configuration diagram of a T FIFO memory.

FIG. 2 is a configuration diagram of a UART FIFO memory that supports 4 Mbps infrared communication according to the related art.

FIG. 3 is a configuration diagram of a main block of a UART FIFO memory according to the present invention.

FIG. 4 is a detailed configuration diagram of a FIFO controller selection unit of the present invention.

FIG. 5 is a detailed configuration diagram of a FIFO controller of the present invention.

FIG. 6 is an operation waveform diagram of a FIFO controller selection unit.

[Explanation of symbols]

 Reference Signs List 40 First FIFO memory unit 41 Second FIFO memory unit 42 Selection FIFO memory unit 43 First multiplexing / decoding unit 44 Second multiplexing / decoding unit 45 Third multiplexing / decoding unit 46 First transmission / reception selecting unit 47 No. 2 transmission / reception selecting section 48 first FIFO controller selecting section 49 second FIFO controller selecting section 50 first FIFO controller 51 second FIFO controller 52 half-duplex mode controller

Claims (9)

[Claims] 1. A first and second FIFO memory unit used when inputting / outputting data to be transmitted / received, and a selected FIFO memory unit selected and used when the first and second FIFO memory units become full. A first and a second FIFO controller selecting unit for counting and outputting an address relating to data transmission or reception; and a first FIFO memory for multiplexing and decoding an address count signal of the first FIFO controller selecting unit in a data receiving mode. And a second multiplexing / decoding unit for multiplexing and decoding the address count signal of the second FIFO controller selecting unit in a data transmission mode and outputting the multiplexed and decoded address count signal to a second FIFO memory. The transmission mode when using the selected FIFO memory unit Multiplexing the first and second transmission / reception selecting units for judging whether the current mode is the communication mode and outputting respective write / read address count signals, and the read / write of the first and second transmission / reception selecting units. And a third multiplexing / decoding unit for multiplexing and decoding and outputting the multiplexed and decoded data to the selected FIFO memory unit. 2. The asynchronous data transmission / reception device according to claim 1, wherein each of the first and second FIFO memory units and the selected FIFO memory unit has a capacity of 16 bytes. 3. The asynchronous data transmission / reception apparatus according to claim 1, wherein the first, second, and third multiplexing / decoding units each output a 16-bit address. 4. The asynchronous data transmission / reception device according to claim 1, wherein the first and second transmission / reception selecting units do not simultaneously enable the transmission mode and the reception mode. 5. The apparatus of claim 1, wherein the first and second FIFO controller selectors support a full-duplex mode when a half-duplex signal is not enabled. 6. The first and second FIFO controller selecting sections each include an address count signal (WR-fi) related to reading / writing that is not in the infrared communication mode in the full-duplex mode.
fo, RD-fifo) and outputs the first and second F
Data transmission / reception is performed using the IFO memory unit, and when the half-duplex signal is enabled, the address count signals (WR-Sel-fifo, RD-Sel-
6. The asynchronous data transmission / reception apparatus according to claim 5, wherein the data transmission / reception is performed so that data transmission / reception is performed using the selected FIFO memory unit. 7. A read / write enable signal (WR) for each of the first and second FIFO controller selectors.
-En, RD-en) and the read / write signal (W
R / RD), read and write address count signals (WR-fifo, RD-fifo) are output, the read address count signal is compared with the write address count signal, and full-duplex or half-duplex is performed. Double comparison signal (full 1, 2) (Empty 1, 2)
A first FIFO controller, a second FIFO controller, and a read address count signal (RD-f) of the first FIFO controller when the half-duplex signal is enabled.
ifo) and a half-duplex mode comparison signal (Empty 2) of the second FIFO controller, and latches the second comparison signal.
A half-duplex mode controller that outputs to a FIFO controller, and the full-duplex or half-duplex comparison signal (Full 1, 2)
2. The asynchronous data transmission / reception device according to claim 1, further comprising first and second MUXs for multiplexing and outputting (Empty 1, 2). 8. The first and second FIFO controllers each use a write enable signal (WR-en) to generate an address count signal (WR-fif) for writing.
o), a read counter that outputs an address count signal (RD-fifo) related to reading by a read enable signal (RD-en), an MSB of the write counter and M of the read counter.
A first comparison unit that compares the SB and outputs a comparison value thereof, a first AND gate that performs a logical operation on the comparison value of the first and second comparison units and outputs a half-duplex signal (empty), A second AND gate that compares the inverted comparison value of the first comparison unit with the comparison value of the second comparison unit and outputs a full-duplex signal (full). Item 2. An asynchronous data transmission / reception device according to item 1. 9. The half-duplex mode controller includes a second FI
The signal (e) for the inverted half-duplex of the FO controller
mpty 2) and the read address count signal (RD-fifo) of the second FIFO controller, and if the signal relating to half duplex is in a disabled state, a high signal is output when the read address count value is 15. If the half-duplex signal is enabled, a comparison unit that outputs a read address count value; and the half-duplex signal (empty 2) that is enabled by the first FIFO controller full-duplex signal (empty 2). 1st that latches and outputs full 1)
A latch unit, the first unit being enabled by an output signal of the comparing unit,
A second latch unit that latches and outputs an output value of the latch unit, a first AND gate that performs a logical operation on a signal related to half duplex and a signal (full 1) related to full duplex of the first FIFO controller, and outputs the result. 2 The latch value output from the latch unit and the first F
Full duplex signal of IFO controller (full)
A second AND gate that logically calculates and outputs a signal (full 1, 2) related to full duplex of the first and second FIFO controllers
An ND gate, and a logic operation for outputting a signal (empty 1, 2) related to half duplex of the first and second FIFO controllers, and outputting the signal.
The asynchronous data transmission / reception device according to claim 6, comprising: an R gate;