JPH10215354A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of signal lines, to facilitate control and to improve extendibility by connecting image processing means in common through selective decision means, respectively selecting the image processing means for inputting and outputting image data and turning only the selective decision means corresponding to them to a conductive state. SOLUTION: The plural selective decision means provided corresponding to the plural image processing means composed of an image read part 3, an image recording part 4, a communication part 5 for transmitting and receiving data and a host interface part 6 selectively decide whether to turn the image data to the conductive state or an interrupted state to the respective image processing means 2-6. Then, the image processing means 2-6 are connected by a signal transmission line 7 in common through the selective decision means and a control part 2 selects one each of optional image processing means 4-6 for inputting the image data from the image processing means 2-6 and the optional image processing means 3, 5 and 6 for outputting the image data and performs the control so as to make only the selective decision means corresponding to them be conductive.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus having a predetermined number of image input units and image output units, and transmitting image data to and from an arbitrary image input unit and image output unit.

[0002]

2. Description of the Related Art Conventionally, there is a digital copying machine 501 as shown in FIG. The digital copying machine 501 is roughly composed of a laser printer 502 and a scanner 503. An interface 511 provided on the laser printer 502 side
And an interface 51 provided on the scanner 503 side
2 by signal lines 521 and 522,
The image data read by the scanner 503 is transferred to the laser printer 502, and a desired image is printed out.

Further, on the laser printer 502 side, expansion interfaces 513 and 515 are provided in advance, and these interfaces 513 and 515 are provided.
By connecting a facsimile unit 504 and an optical filing unit 505, which are optional expansion units, a function as a facsimile apparatus or an optical filing apparatus can be added to the digital copying machine 501.

Specifically, by connecting the interface 513 and the interface 514 provided on the facsimile unit 504 side by signal lines 523 and 524, the facsimile image received by the facsimile unit 504 is printed out by the laser printer 502. The image data read by the scanner 503 is transmitted from the facsimile unit 504 via the laser printer 502.

[0005] By connecting the interface 515 and the interface 516 provided on the optical filing unit 505 side by signal lines 525 and 526, image data in the optical filing unit 504 is printed out by the laser printer 502, The image data read by the scanner 503 is transferred to the laser printer 50.
2 and stored in the optical filing unit 505.

Further, as an image apparatus which can be combined with a facsimile apparatus, an optical filing apparatus and the like, an image processing apparatus as disclosed in Japanese Patent Application Laid-Open No. Hei 4-248679 has been proposed. The image processing apparatus includes an image input unit and an image output unit, and an output buffer circuit for outputting image data input by the image input unit, and for inputting image data to be output to the image output unit. And an input signal line for transmitting image data and an output signal line are wired independently of each other.

[0007] In order to newly connect a device capable of performing both input and output of image data, such as an extended function device such as a facsimile device or an optical filing device, both image data and a synchronization signal are used. There is provided a through path for transmission in the direction. The transmission direction of this through path is determined by an externally applied control signal. As described above, in the present image processing apparatus, a large number of extended function devices can be added with a simple configuration, and image data can be freely exchanged between the image input unit, the image output unit, and the newly added extended function device. Can be exchanged.

[0008]

However, in the former digital copying machine 501, it is necessary to prepare an interface corresponding to a device to be expanded in advance, so connection is planned at the time of system design. Only an interface for expansion devices is provided. For this reason, equipment that is not planned to be expanded cannot be newly expanded,
There was a problem of poor expandability.

On the other hand, in the latter image processing apparatus, since the input signal line and the output signal line are separate, compared with the case where the input signal line and the output signal line are commonly used,
It simply requires twice as many signal lines. In addition, since a plurality of buffer circuits are required for the through path, there is a problem that the circuit becomes complicated and its control becomes complicated.

Further, in both the former and latter image processing apparatuses, the number of connection signal lines connecting between the new expansion apparatus and the main apparatus increases with the addition of the expansion apparatus.
The configuration and control processing of the control circuit for controlling the signal flow become complicated, which causes a problem that the cost is increased.

More specifically, as shown in FIG. 18, when an image processing apparatus composed of four modules of an image reading unit 601, an image recording unit 602, a communication unit 603, and a host interface unit 604 is considered, In order to connect the modules, six signal lines 611 to 616 are required. Here, if one new module is added and the total number of modules is set to 5, four more signal lines are required, and each time a module is added, the number of signal lines reduced by one from the current module number is not added. must not.

Further, one signal line described here includes a signal line for image data for transmitting image data and a signal line and a line for page synchronization signal for synchronizing between image processing means. Since a total of four signal lines including a signal line for a synchronization signal and a signal line for a dot synchronization signal are included, the number of signal lines for connecting the above-described four modules is actually 24. As described above, the increase in the number of signal lines accompanying the addition of the module becomes considerable.

It is an object of the present invention to provide an image processing apparatus in which the number of signal lines is reduced, control is facilitated, and expandability is improved, in order to solve the above problems.

[0014]

According to the first aspect of the present invention, a plurality of image processing means for inputting or outputting image data to be processed and a plurality of image processing means are provided in correspondence with these image processing means. Selection determining means for selectively determining whether the image data is in a conductive state or in a cutoff state with respect to the means, and a signal transmission line for commonly connecting the image processing means via these selection determining means And an image processing means for inputting image data and an image processing means for outputting image data are selected one by one from the image processing means, and a selection determining means corresponding to the selected image processing means is selected. And control means for controlling only one of them to be in a conductive state.

That is, according to the first aspect of the present invention, the number of signal lines can be significantly reduced by commonly connecting all image processing means for inputting or outputting image data by a signal transmission path. In addition, by setting only the pair of image processing units that exchange image data to be in a conductive state, it is possible to prevent erroneous input / output of image data to / from the signal transmission path by other commonly connected image processing units.

According to a second aspect of the present invention, there are provided a plurality of image processing means for inputting or outputting image data to be processed,
A plurality of selection determining means are provided correspondingly to these image processing means, and selectively determine whether to set the image data to a conduction state or a blocking state for each image processing means, A signal transmission path for commonly connecting the image processing means via the determining means, and a level constant for making the potential level in the signal transmission path constant when the image data for all the image processing means is cut off by the selection determining means Means, and any one of image processing means for inputting image data and any image processing means for outputting image data is selected from among the image processing means, and a selection corresponding to the selected image processing means is determined. And control means for controlling only the means to be in a conductive state.

That is, according to the second aspect of the present invention, in addition to the first aspect of the present invention, when no signal flows in the signal transmission line, the potential level of the signal transmission line is set to, for example, a low level. By fixing the potential level of the potential power supply line, an erroneous potential such as an intermediate potential level is prevented from being applied to a circuit connected to the signal transmission line.

According to the third aspect of the present invention, the signal transmission path comprises:
A signal line for image data for transmitting image data, and a signal line for synchronization signal for synchronizing between the image processing means, and the image processing means for inputting image data selected by the control means. An image processing unit that outputs image data outputs a synchronization signal to the image processing unit that outputs the image data from the image processing unit that outputs the image data, which is selected by the control unit. On the other hand, an image data signal is output via an image data signal line.

That is, according to the third aspect of the present invention, in addition to the first or second aspect of the present invention, image data can be correctly exchanged only between the selected image processing means.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one illustrated embodiment.

First Embodiment

FIG. 1 shows an example of a main configuration of an image processing apparatus according to a first embodiment of the present invention. As shown in FIG. 1, the image processing apparatus 1 according to the present embodiment includes a control unit (control unit) 2 that performs overall control of processing in the image processing apparatus 1, and output from the control unit 2 via a signal line 101. An image reading unit (image processing means) 3 for reading desired image data based on a control signal from the control unit 2;
Communication between an image recording unit (image processing unit) 4 that records image data based on a control signal output through the control unit 2 and an external device based on a control signal output from the control unit 2 via a signal line 103 Communication unit (image processing means) 5 for transmitting and receiving data by a host, and a host serving as an input / output interface with a host device such as a personal computer (not shown) based on a control signal output from the control unit 2 via a signal line 104. An interface unit (image processing means) 6.

The image reading unit 3, the image recording unit 4, the communication unit 5,
The host interface unit 6 constitutes an independent module (hereinafter, the image reading unit 3, the image recording unit 4, the communication unit 5, and the host interface unit 6 are respectively referred to as sub-modules). (Signal transmission path) 7 are commonly connected to each other.

In FIG. 1, the signal line 7 is shown as one signal line. However, actually, the signal line 7 is for transmitting image data, and the signal line 7 is for transmitting a synchronizing signal. A signal line for a page synchronization signal to be a signal line for a synchronization signal of
It includes a total of four signal lines: a signal line for line synchronization signals and a signal line for dot synchronization signals. One end of the signal line 7 is connected to a low-potential power supply line via a pull-down resistor (level stabilizing means) 8.

The control unit 2 controls the system bus 100
CPU (Central Processes) connected via signal line 105
sing unit) 11 and R connected via a signal line 106.
An OM (Read Only Memory) 12, a RAM (Random Access Memory) 13 connected via a signal line 107, an operation panel 14 connected via a signal line 108, and a serial input / output connected via a signal line 109 Unit (hereinafter, a serial input / output unit is abbreviated as an SIO unit) 15 and an SIO unit 1 connected via a signal line 110.
6, an SIO unit 17 connected via a signal line 111,
And an SIO unit 18 connected via a signal line 112.

Here, the CPU 11 is a central processor of the control unit 2 and executes various control processes based on a program processing procedure stored in the ROM 12.
The ROM 12 is a semiconductor memory that stores various control programs and data used by the CPU 11,
The RAM 13 is a semiconductor memory for storing program data and the like used during execution of program processing in the CPU 11, temporarily storing data and the like related to processing, and using it as a work area. Note that a queue register described later is realized by using a predetermined area in the RAM 13. The operation panel 14 is an interface for inputting various instruction items to the control unit 2.

The SIO section 15 is for transmitting a control signal output from the CPU 11 to the image reading section 3 connected via the signal line 101.
The IO unit 16 is connected to the image recording unit 4 connected via the signal line 102, the SIO unit 17 is connected to the communication unit 5 connected via the signal line 103, and the SIO unit 18 is connected to the signal line This is for transmitting a control signal output from the CPU 11 to the host interface unit 6 connected via 104.

FIG. 2 shows in detail the configuration of the main part of the image reading section in FIG. The image reading unit 3 includes a bus 2
CPU 21 connected via signal line 201 to CPU 21
A ROM 22 connected via a signal line 202; a RAM 23 connected via a signal line 203;
, An image signal interface unit 25 connected via a signal line 205, an A / D converter 26 connected via a signal line 206, and a signal line 2
09 and a sensor 29 connected via a signal line 210.

Further, a CCD (Charge Coupled Device) connected to the A / D converter 26 via a signal line 208 is provided.
e) 27, a buffer circuit 30 that outputs the image data signal VD input from the image signal interface unit 25 via the signal line 211 via the signal line 212, and a dot synchronization input via the signal line 213. Signal VCLK
And a line synchronization signal LSYNC input through a signal line 215 to the image signal interface unit 25 via a signal line 214.
A buffer circuit 32 that outputs the page synchronization signal PSYNC input via the signal line 217 to the image signal interface unit 25 via the signal line 218; It has.

[0030] These buffer circuits 30 to 33 has a function as a selection determination means together with the image signal interface unit 25, the respective signals by the enable signal E ₁ outputted from the image signal interface unit 25 via the signal line 219 Control I / O state. Specifically, when the enable signal E _{1 is set} to a high level (hereinafter, “H”), the idle state is set, and when the enable signal E ₁ is set to a low level (hereinafter, “L”), the operation state is set. Also, the A / D conversion unit 26
Image signal interface unit 25 via signal line 207
To output a timing signal. As a result, the image reading unit 3 receives the control signal from the control unit 2 based on the control signal.
The desired image data is read by the CCD 27, and the read image data is output to the signal line 212 (that is, the signal line 7).

FIG. 3 shows in detail the configuration of the main part of the image recording unit in FIG. The image recording unit 4 includes the bus 2
CPU 41 connected to signal line 20 via signal line 221
A ROM 42 connected via a signal line 222, a RAM 43 connected via a signal line 223, and a signal line 224.
, An image signal interface unit 45 connected via a signal line 226, a motor 47 connected via a signal line 229, and a sensor 48 connected via a signal line 230. ing.

Further, an exposure section 46 connected from the image signal interface section 45 via a signal line 227.
And the image data signal V input through the signal line 231
D via a signal line 232 to a buffer circuit 49 for outputting the signal D to the image signal interface unit 45, and a dot synchronization signal VCLK input from the image signal interface unit 45 via the signal line 233 via a signal line 234. A buffer circuit 50 that outputs a line synchronization signal LSYNC input from the image signal interface unit 45 via a signal line 235 via a signal line 236, and a signal line 237 from the image signal interface unit 45. Page synchronization signal PSYN input through
C that outputs C through a signal line 238
And

[0033] These buffer circuits 49 to 52 has a function as a selection determination means together with the image signal interface unit 45, the respective signals by the enable signal E ₂ output from the image signal interface unit 45 via the signal line 239 Control I / O state. Thus, the image recording unit 4 forms desired image data in the exposure unit 46 based on the control signal input from the control unit 2, and prints out the formed image data on a predetermined image recording sheet.

FIG. 4 shows the configuration of the main part of the communication unit in FIG. 1 in detail. The communication unit 5 includes a CPU 61 connected to the bus 240 via a signal line 241, a ROM 62 connected via a signal line 242, and a signal line 243.
, An SIO unit 64 connected via a signal line 244, an image signal interface unit 65 connected via a signal line 246, and a compression / decompression unit 66 connected via a signal line 248. , A modem 67 connected via a signal line 249, and a line interface 68 connected via a signal line 251.

Further, a buffer circuit 69 for outputting the image data signal VD input via the signal line 253 to the image signal interface section 65 via the signal line 255.
And a signal line 254 from the image signal interface 65.
The image data signal VD input through the
3 and a signal line 256
And a dot synchronization signal VCLK input from the image signal interface unit 65 via the signal line 257 to the buffer circuit 71 for outputting the dot synchronization signal VCLK input via the image signal interface unit 65 via the signal line 258. A buffer circuit 72 that outputs a line synchronization signal LSYNC input via a signal line 259 to the image signal interface unit 65 via a signal line 261.
The line synchronization signal LSYNC input from the image signal interface unit 65 via the signal line 260 is
A buffer circuit 74 for outputting the signal via the signal line 59;
2, a buffer circuit 75 that outputs the page synchronization signal PSYNC input via the signal line 264 to the image signal interface unit 65, and a page synchronization signal input from the image signal interface unit 65 via the signal line 263. A buffer circuit 76 for outputting PSYNC via a signal line 262.

The buffer circuits 69, 71, 73, 75
An enable signal E ₃ output from the image signal interface unit 65 via the signal line 265 has a function as selection determining means together with the image signal interface unit 65.
Control the input / output state of each signal. The buffer circuit 70, 72, 74, 76, controls the output state of each signal by the enable signal E ₄ output from the image signal interface unit 65 via a signal line 266. That is, in order to input and output the image signal and the synchronization signal, the communication unit 5 needs to control the input and output with two types of enable signals.

The compression / expansion unit 66 exchanges an image signal with the image signal interface unit 65 via the signal line 247 to compress or expand the image signal.
The modem 67 is connected to the line interface 68 via the signal line 250, and modulates a signal to be output to the line interface 68 and demodulates a signal input from the line interface 68. . The line interface 68 is connected to an external line such as an analog general public line via a signal line 252, and inputs and outputs image signals through the external line. Thereby, the communication unit 5 inputs and outputs image data to and from an external line based on the control signal input from the control unit 2.

FIG. 5 shows in detail the configuration of the main part of the host interface unit in FIG. The host interface unit 6 connects the signal line 27 to the bus 270.
1, a ROM 82 connected through a signal line 272, a RAM 83 connected through a signal line 273, and an SIO connected through a signal line 274.
An image signal interface unit 85 connected via a signal line 276, a page memory 86 connected via a signal line 278, and a bidirectional parallel interface 87 connected via a signal line 279. .

Further, a buffer circuit 89 for outputting the image data signal VD input via the signal line 281 to the image signal interface unit 85 via the signal line 283.
And a signal line 282 from the image signal interface unit 85.
The image data signal VD input through the
1 and a signal line 285
And a dot synchronization signal VCLK input from the image signal interface unit 85 via the signal line 286 to the buffer circuit 91 which outputs a dot synchronization signal VCLK input via the signal line 287 to the image signal interface unit 85 via the signal line 287. A buffer circuit 92 that outputs a signal via a signal line 285, a buffer circuit 93 that outputs a line synchronization signal LSYNC input via a signal line 288 to the image signal interface unit 85 via a signal line 290,
The line synchronization signal LSYNC input from the image signal interface unit 85 via the signal line 289 is transmitted to the signal line 2
A buffer circuit 94 for outputting the signal via a signal line 88;
1 and a buffer circuit 95 for outputting the page synchronization signal PSYNC input to the image signal interface unit 85 via the signal line 293, and a page synchronization signal input from the image signal interface unit 85 via the signal line 292. A buffer circuit 96 for outputting PSYNC via a signal line 291 is provided.

The buffer circuits 89, 91, 93, 95
An enable signal E ₅ output from the image signal interface unit 85 via the signal line 294 has a function as selection determining means together with the image signal interface unit 85.
Control the input / output state of each signal. The buffer circuit 90, 92 controls the output state of each signal by the enable signal E ₆ output from the image signal interface unit 85 via a signal line 295. That is, similarly to the communication unit 5, the host interface unit 6 needs to control input and output by two types of enable signals in order to input and output an image signal and a synchronization signal.

The page memory 86 exchanges image signals with the image signal interface unit 85 via the signal line 277, and stores one page of image data.
The bidirectional parallel interface 87 is an interface for connecting to a personal computer (hereinafter, referred to as a personal computer) 88 serving as a host device via a signal line 280. Is used to input and output image signals. Thereby, the host interface unit 6 inputs and outputs image data to and from the personal computer 88 based on the control signal input from the control unit 2.

In the above configuration, the image signal interface units 25, 45, 65, 85 in each sub-module
Are connected to a signal line for a page synchronization signal, a signal line for a line synchronization signal, a signal line for a dot synchronization signal, and a signal line for an image data, respectively. Line 7 is formed.

FIG. 6 shows the waveforms of the page synchronization signal, the line synchronization signal, the dot synchronization signal, and the image data signal at the time of idling. FIG. 7 shows the page synchronization signal, the line synchronization signal, and the dot synchronization signal during operation. 3 shows a waveform of an image data signal. 6 and 7
(A) is a page synchronization signal PSYNC, (b) is a line synchronization signal LSYNC, and (c) is a dot synchronization signal VCL.
K and (d) show the image data signal VD.

At the time of idling, as shown in FIG. 6, the potentials of the signal lines for the page synchronizing signal, the line synchronizing signal, and the dot synchronizing signal are fixed at "L" in an inactive state. . Therefore, the pull-down resistor 8 has
Using a resistor having a resistance value of several hundred Ω to several kΩ, the potential level of the synchronization signal line in the inactive state is kept constant. The image data signal line is set to high impedance (hereinafter, “Z”).

On the other hand, in operation, a predetermined sub-module (in this case, any one of the image reading unit 2, the communication unit 4, and the host interface unit 5) for outputting an image by the control unit 2 and a predetermined sub-module for inputting an image. The module (in this case, any of the image recording unit 3, the communication unit 4, and the host interface unit 5) is activated, and the image data signal V
The image data signal V
The page synchronization signal PSYNC and the line synchronization signal LSY as shown in FIG.
NC outputs the dot synchronization signal VCLK to the signal line 7.
Then, the submodule that outputs the image data signal VD outputs the image data signal VD to the signal line 7 in synchronization with the input page synchronization signal PSYNC, line synchronization signal LSYNC, and dot synchronization signal VCLK.

At this time, since the sub-modules to which the image data signal VD is to be output and the sub-modules to which the image data signal VD is to be input are in the idle state, the signal line 7 is electrically connected. Is not connected to That is, the selected 2
Only the two sub-modules are in a state equivalent to that connected by a page synchronization signal line, a line synchronization signal line, a dot synchronization signal line, and an image data signal line. Each signal has a different time period depending on the size of the document or the recording paper, and the reading or recording resolution.

FIG. 8 shows operable combinations of sub-modules for inputting and outputting image data.
The sub-module on the image output side is any of the image reading unit 2, the communication unit 4, and the host interface unit 5, while the sub-module on the image input side is the image recording unit 3, the communication unit 4, the host interface Part 5. Then, as shown in FIG. 8, “copy” (01
H), "Transmission accumulation" (02H), "Local scan"
(03H), "Receive Print" (04H), "PC Fax Receive" (05H), "PC Print" (06
H), and seven operation modes of “PC fax transmission” (07H). And in each operation mode,
Numbers “01H” to “07H” are assigned.

The image processing apparatus 1 of the present embodiment has only one sub module on the image output side and one sub module on the image input side that are active during operation, and cannot perform two operations at a time. Therefore, when there is an operation request from the idle sub-module, the request is queued in the queue register in the RAM 13. The queue register, as described above,
And is managed by the CPU 11. Further, in the present embodiment, since there is a possibility that an operation request is generated from the remaining two sub-modules while the two sub-modules are operating, a three-stage queue register is prepared as shown in FIG. .

FIG. 9 is for explaining the change of the internal value of the queue register according to the operation request. Immediately after the power is turned on, the queue registers for both the first to third stages are "00".
(See A in FIG. 9.) Here, when there is an operation request of “transmission accumulation” from the image reading unit 2, “02H” is written in the first stage of the queue register, and “transmission” is written. An "accumulation" operation is performed (see B in FIG. 9).

If the host interface unit 5 requests a “PC print” operation during the “transmission and accumulation” operation, the “transmission and accumulation” operation is currently being executed.
“06H” is written in the second stage of the queue register (FIG. 9
Medium, see C). When the “transmission accumulation” operation is completed, the contents of the second stage of the queue register are copied to the first stage, the contents of the third stage are copied to the second stage, and “0” is copied to the third stage.
Thus, “06H” stored in the second row is written in the first row, and the “PC print” operation is executed (see D in FIG. 9).

Next, an example of the operation of the image processing apparatus 1 in the above embodiment will be described with reference to FIGS.

FIG. 10 shows a processing procedure after the power of the image processing apparatus is turned on. When the power of the image processing apparatus 1 is turned on, the CPU 11 writes “00H” into the queue register in the RAM 13 and initializes the queue register (step S101). The image signal interface units 25, 45,
The enable signals E _{1 to} E ₆ output from 65 and 85 are set to “H”, respectively. As a result, the potential of each of the signal lines for the page synchronization signal, the line synchronization signal, and the dot synchronization signal is fixed to the inactive state “L”, and the idle state is set (step S102). Next, other initialization processing is executed (step S103).

FIGS. 11 to 13 show the processing procedure when facsimile transmission is performed by the image processing apparatus of the present embodiment. When the operator inputs an instruction of “transmission accumulation” from the operation panel 14 (step S201), C
The PU 11 reads the contents of the first stage of the queue register, and confirms that the contents are “00H” and the current operation state is the idle state (Step S20)
2). Then, the CPU 11 writes “02H” in the first stage of the queue register and selects “transmission accumulation” as the operation mode (step S203). Then, CPU
11 instructs the image reading unit 3 to read the original from the SIO unit 15 via the signal line 101 (step S2).
04), it is determined whether or not the image reading unit 3 is in a ready state (step S205).

In the determination processing of step S205, if there is no response from the image reading section 3 to the ready status signal, it is determined that the image reading section 3 is not in the ready state yet (step S205; N), and the ready status signal is output. Wait until you receive. On the other hand, in the determination processing of step S205, when there is a reply of the ready status signal from the image reading unit 3, it is determined that the image reading unit 3 is in the ready state (step S205; Y). Image reading portion 3 became ready state, the enable signal E ₁ outputted from the image signal interface section 25 as "L", page synchronizing signal signal line, the line synchronizing signal signal line, a signal line dot synchronizing signal In addition to the operation state, the document size is detected by the sensor 29, and information on the detected document size is notified from the SIO unit 44 to the CPU 11 (step S206).

Next, the CPU 11 instructs the SIO unit 17 to transmit to the communication unit 5 via the signal line 103, and also transmits necessary information such as a document size, a transmission mode, and a destination telephone number ( Step S207). CPU1
The communication unit 5 which has received the transmission instruction from 1, the enable signal E ₃ and outputs the image signal interface unit 65 as "L", page synchronizing signal signal line, the line synchronizing signal signal line, dot synchronizing signal signal The operating state of the wire,
Page synchronization signal PSYNC, line synchronization signal LSYNC
C, a state in which each synchronization signal of the dot synchronization signal VCLK can be transmitted (step S208).

Next, the communication section 5 provides a predetermined page synchronization signal PSYNC and a line synchronization signal LS corresponding to the document size.
The synchronization signals of the YNC and the dot synchronization signal VCLK are output to the signal line 7, and the image reading unit 3 inputs these synchronization signals via the signal line 7 (step S209). As a result, the image reading unit 3 outputs the image data signal VD to the signal line 7.
And the communication unit 5 receives the image data signal VD via the signal line 7. Further, the communication section 5 compresses the image data signal VD by the compression / decompression section 66 and stores the compressed image data in the RAM 63 (step S21).
0).

When the “transmission accumulation” for one page is completed, the communication unit 5 sends information of the page end to the SIO unit 64.
To notify the CPU 11 (step S211). Then, the CPU 11 checks whether or not there is a document remaining from the SIO unit 15 via the signal line 101 to the image reading unit 3 (step S212), and determines whether or not the document is still present in the image reading unit 3. Is determined (step S213). In the determination processing of step S213, if there is still a document in the image reading unit 3 (step S213; Y), the CPU 11
The SIO unit 17 instructs the communication unit 5 to input the next original via the signal line 103 (step S214), and executes the processing from step S209.

On the other hand, in the judgment processing of step S213, when there is no more original in image reading section 3 (step S2).
13; N), the CPU 11 sends the signal line 1 from the SIO unit 15
The end of the “transmission and accumulation” operation is notified to the image reading unit 3 via “01” (step S215). The image reading unit 3 that has received the end notification of the “transmission accumulation” operation sets the enable signal E ₁ output from the image signal interface unit 25 to “H”, and sets the signal line for the page synchronization signal, the signal line for the line synchronization signal, and the dot. The synchronization signal line is set to the idle state (step S216). Subsequently, the CPU 11 executes S
The IO unit 17 notifies the communication unit 5 via the signal line 103 of the end of the "transmission accumulation" operation (step S21).
7).

The communication unit 5 that has received the notification of the end of the “transmission accumulation” operation sets the enable signal E ₃ output from the image signal interface unit 65 to “H”, and sets the signal line for the page synchronization signal and the signal line for the line synchronization signal. Then, the signal line for the dot synchronization signal is set to the idle state (step S218). Next, the CPU 61 modulates the compressed image data stored in the RAM 63 by the modem 67, and transmits the modulated image data to the communication partner via the line interface 68 (step S21).
9). Then, the CPU 11 writes “00H” in the first row of the queue register and sets the end of “transmission accumulation” (step S220).

FIGS. 14 to 16 show a processing procedure when another operation request is made during facsimile transmission in the image processing apparatus of this embodiment. In addition,
In this example, a case has been described in which a “PC print” operation request is issued from the personal computer 88 connected to the host interface unit 6 as another operation request, but an operation other than the “PC print” operation request is performed. For a request, the same processing procedure is performed only by changing the relevant part.

The personal computer 88 connected to the host interface unit 6 sends a bidirectional parallel interface 87
(Step S30)
1) The host interface unit 6 stores the print data sent from the personal computer 88 in the page memory 86 (step S302). Then, the page memory 86
When one page of print data is stored in the SIO section 84, the host interface section 6
The CPU 11 notifies the CPU 11 that there is a print request (step S303). At this time, information such as the recording paper size is also notified.

Upon receiving the notification from the host interface unit 6, the CPU 11 reads the contents of the first stage of the queue register and checks the contents (step S30).
4). In this case, since the contents of the first stage of the queue register are “02H” indicating “transmission accumulation” as shown in B in FIG. 9, the current operation state is the “transmission accumulation” state. Check. Subsequently, the CPU 11 reads the contents of the second stage of the queue register, and reads the contents of “00”.
If it is confirmed that the operation mode is "H", "06H" is written here, and the fact that there is an operation request of "PC print" as the next operation mode is recorded (step S305). And
Since the CPU 11 is currently performing the “transmission accumulation” operation,
The IO unit 18 instructs the host interface unit 6 via the signal line 104 to temporarily wait (Step S
306). Thereafter, the CPU 11 checks the contents of the queue register at regular intervals (step S307).

That is, the first stage of the queue register is "0"
It is determined at regular intervals (step S308) whether or not "0H" has been reached (step S30).
8; Y), the CPU 11
The contents of the second row (in this case, "06H") are copied, and the contents of the second row are written to "00H" to update the contents of the queue register (step S309). Subsequently, the CPU 11 instructs the host interface unit 6 to start printing from the SIO unit 18 via the signal line 104 (step S310).

The host interface unit 6 to which the print start instruction is given is sent to the image signal interface unit 8
Then, the enable signal E ₆ output from the terminal 5 is set to “L”, and the image signal can be output (step S311). Then, the CPU 11 instructs the image recording unit 4 to perform printing from the SIO unit 16 via the signal line 102 (Step S).
312), it is determined whether or not the image recording unit 4 is in a ready state (step S313). If there is no response from the image recording unit 4 in the determination process in step S313, the image recording unit 4 determines that the image recording unit 4 is not in the ready state (step S313; N), and receives the ready status signal. Wait until.

On the other hand, in the determination processing of step S313, if there is a reply of the ready status signal from the image recording unit 4, it is determined that the image recording unit 4 is in the ready state (step S313; Y). In the ready state, the image recording unit 4 sets the enable signal E ₂ output from the image signal interface unit 45 to “L”, and sets the page synchronization signal line, the line synchronization signal line, and the dot synchronization signal line to “L”. Activate the page synchronization signal PSY
NC, line synchronization signal LSYNC, dot synchronization signal VC
Each of the LK synchronization signals can be transmitted (step S
314).

Next, the image recording unit 4 outputs predetermined synchronizing signals of a page synchronizing signal PSYNC, a line synchronizing signal LSYNC, and a dot synchronizing signal VCLK to the signal line 7 in accordance with the size of the original, via the signal line 7. The host interface unit 6 inputs these synchronization signals (step S
315). Thereby, the host interface unit 6
Outputs the image data signal VD to the signal line 7 and
The image recording unit 4 receives the image data signal VD via the.

Then, the host interface unit 6
While outputting the image data signal VD to the image recording unit 4, the next print data sent from the personal computer 88 is stored in the page memory 86 (step S316). When the storage of the print data is completed, the page end information is notified from the SIO unit 84 to the CPU 11 (step S317). Then, the CPU 11 checks whether or not the print data remains from the SIO unit 18 to the host interface unit 6 via the signal line 104 (step S318), and determines whether the print data still exists in the page memory 86. It is determined whether or not it is (step S319).

If it is determined in step S319 that print data still exists in the page memory 86 (step S319; Y), the processing from step S315 is executed again. On the other hand, in the determination process of step S319, when there is no more print data in the page memory 86 (step S319; N), the CPU 11
8 notifies the host interface unit 6 via the signal line 104 of the end of the "PC print" operation (step S320).

The host interface unit 6 having received the notification of the end of the “PC print” operation sets the enable signal E ₆ output from the image signal interface unit 85 to “H”, sets the signal line for the page synchronization signal and the signal for the line synchronization signal. The line and the dot synchronization signal line are set to the idle state (step S321). Subsequently, the CPU 11 executes the SIO unit 1
6 to the image recording unit 4 via the signal line 102 with “P
The end of the "C print" operation is notified (step S32).
2).

The image recording unit 4 which has received the notification of the end of the “PC print” operation sets the enable signal E ₂ output from the image signal interface unit 45 to “H”, and sets a signal line for a page synchronization signal and a signal for a line synchronization signal. The line and the dot synchronization signal line are set to the idle state (step S32).
3). Then, the CPU 11 writes “00H” in the first row of the queue register and sets the end of “PC print” (step S324).

As described above, in this embodiment, the four signals of the image data signal line, the page synchronization signal signal line, the line synchronization signal signal line, and the dot synchronization signal signal line are provided between the sub-modules. Since the line is used as a common signal line, by adding new sub-modules,
The number of signal lines does not increase. Further, by sharing the signal line, it is easy to add a sub-module later, and the system is excellent in expandability.

First Modification of First Embodiment

The facsimile transmission in the above-described embodiment is
The image data to be transmitted is stored after being stored in the RAM 63 in the communication unit 5. However, instead of storing all the image data and then transmitting the image data, the image data input to the communication unit 5 is input. You may make it transmit sequentially at the time when it was performed.

In the above-described embodiment, the image reading unit 3, the image recording unit 4, the communication unit 5, and the host interface unit 6 are exemplified as sub-modules. Any device having a function of performing input or output may be connected as a submodule.

[0075]

As described above, according to the first aspect of the present invention, all the image processing means for inputting or outputting image data are connected in common by a signal transmission line, thereby greatly reducing the number of signal lines. This can reduce the number of signal lines due to the addition of the image processing means. In addition, by setting only a pair of image processing means for exchanging image data to be in a conductive state, even if another commonly connected image processing means tries to input / output image data to / from the signal transmission path, this is not necessary. Can be prevented, and inconvenience due to common connection can be avoided.

According to a second aspect of the present invention, in addition to the first aspect of the present invention, the potential level of the signal transmission line is fixed at a constant level when no signal flows in the signal transmission line. Accordingly, the application of an erroneous potential such as an intermediate potential level to other image processing means connected to the signal transmission path can be prevented, and safety can be improved.

According to a third aspect of the present invention, in addition to the first or second aspect of the present invention, only the selected image processing means is provided without supplying a synchronization signal from outside for transmitting image data. , Image data can be exchanged correctly.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a main configuration of an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating in detail a configuration of a main part of an image reading unit in FIG. 1;

FIG. 3 is a diagram illustrating in detail a configuration of a main part of an image recording unit in FIG. 1;

FIG. 4 is a diagram showing in detail a main configuration of a communication unit in FIG. 1;

FIG. 5 is a diagram showing in detail a main configuration of a host interface unit in FIG. 1;

FIG. 6 is a diagram illustrating waveforms of a page synchronization signal, a line synchronization signal, a dot synchronization signal, and an image data signal during an idle time.

FIG. 7 is a diagram illustrating waveforms of a page synchronization signal, a line synchronization signal, a dot synchronization signal, and an image data signal during operation.

FIG. 8 is a diagram showing operable combinations of sub-modules for inputting and outputting image data.

FIG. 9 is a diagram for explaining a change in a queue register internal value according to an operation request;

FIG. 10 is a diagram showing a processing procedure after power-on of the image processing apparatus.

FIG. 11 is a diagram illustrating a processing procedure when facsimile transmission is performed by the image processing apparatus according to the present embodiment.

FIG. 12 is a diagram illustrating a processing procedure subsequent to FIG. 11 when facsimile transmission is performed by the image processing apparatus according to the present embodiment;

FIG. 13 is a diagram illustrating a processing procedure subsequent to FIG. 12 when facsimile transmission is performed by the image processing apparatus according to the present embodiment;

FIG. 14 is a diagram illustrating a processing procedure when another operation request is made during a certain operation in the image processing apparatus according to the present embodiment;

FIG. 15 is a diagram, following FIG. 14, illustrating a processing procedure when another operation request is made during one operation of the image processing apparatus of the present embodiment.

FIG. 16 is a diagram illustrating a processing procedure subsequent to FIG. 15 when another operation request is made during one operation of the image processing apparatus according to the present embodiment;

FIG. 17 is a diagram illustrating a main configuration of an image processing apparatus according to a first conventional example.

FIG. 18 is a diagram illustrating a main configuration of an image processing apparatus according to a second conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus, 2 ... Control part (control means), 3 ... Image reading part (image processing means), 4 ... Image recording part (image processing means), 5 ... Communication part (image processing means), 6 ... Host Interface section (image processing means), 7: signal line (signal transmission path), 8: pull-down resistor (level stabilizing means), 11
... CPU, 12 ROM, 13 RAM, 14 operation panel, 15-18 SIO section, 100 system bus,
101 to 112 ... signal lines

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 1/32 H04N 1/04 102

Claims (3)

[Claims] 1. A plurality of image processing means for inputting or outputting image data to be processed, and a plurality of image processing means provided corresponding to these image processing means, for determining whether the image data is in a conductive state with respect to each image processing means. Alternatively, selection determining means for selectively determining whether to be in the cutoff state, a signal transmission line commonly connecting the image processing means via these selection determining means, and an image from among the image processing means. An arbitrary image processing unit for inputting data and an arbitrary image processing unit for outputting image data are selected one by one, and only the selection determining unit corresponding to the selected image processing unit is controlled to be in a conductive state. An image processing apparatus comprising: a control unit. 2. A plurality of image processing means for inputting or outputting image data to be processed, and a plurality of image processing means provided correspondingly to these image processing means, for determining whether the image data is in a conductive state with respect to each image processing means. Or selection decision means for selectively deciding whether or not to be in a cutoff state; a signal transmission line commonly connecting the image processing means via these selection decision means; and all image processing by the selection decision means When the image data for the means is in a cutoff state, a level stabilizing means for stabilizing a potential level in the signal transmission path; and, from the image processing means, any image processing means for inputting image data and image data. An arbitrary image processing unit to be output is selected one by one, and only the selection determining unit corresponding to the selected image processing unit is controlled to be in a conductive state. The image processing apparatus characterized by comprising a control means. 3. The signal transmission path has an image data signal line for transmitting image data and a synchronization signal signal line for synchronizing image processing means, and is selected by the control means. A synchronization signal is output from the image processing means for inputting the image data to the image processing means for outputting the image data through the signal line for the synchronization signal, and the image data selected by the control means is output. 3. The image processing apparatus according to claim 1, wherein an image data signal is output via the image data signal line to an image processing unit that inputs image data from the image processing unit.