JPH10214948A - Method for manufacturing capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure sufficient capacity and prevent a reduction in an etch rate of an insulation film without heightening stepped parts by a method wherein, after a core of a porous insulation film is formed and one electrode is formed on a surface of the core and the core is removed, a counter electrode is formed via a dielectric film on a surface of one electrode. SOLUTION: After a core 22a of a porous insulation film is formed and one electrode (lower electrode) 9 is formed on a surface of the core 22a and the core 22a is removed, a counter electrode (upper electrode) 11 is formed via dielectric film on a surface of one electrode 9 to manufacture a capacitor. By forming the core 22a of the porous insulation film, it is possible to form an irregularities in the lower electrode 9 formed on a surface of the core 22a and to increase a surface area of the lower electrode 9. Therefore, it is possible to increase capacity of a capacitor 12. Further, the insulation film constituting the core 22a is formed as porous quality, whereby as an etch rate in etching the insulation film is faster, a time for a step of etching-off can be lessened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor which is suitably applied to a highly miniaturized and integrated semiconductor device, for example, a miniaturized and integrated memory device.

[0002]

2. Description of the Related Art With the miniaturization and integration of semiconductor elements, the size of a memory cell in a large-scale DRAM is reduced, whereas the capacity of a capacitor is required to maintain data retention characteristics. , Almost the same value needs to be maintained. For this purpose, for example, a lower electrode of a capacitor, that is, a so-called node electrode is formed at a higher position with respect to a memory cell so as to secure a capacity even with a small cell area, or as shown in FIG. Means for increasing the surface area and securing the capacity by using the capacitor 42 of the (shape) have been proposed.

FIG. 5 is a sectional view of an example of a semiconductor device in which a cylindrical capacitor 42 is formed. This semiconductor device is an example applied to a DRAM which is a semiconductor memory, and includes a MOS transistor 30 formed in a region separated by an element isolation layer 32 of a semiconductor substrate 31 and a capacitor 42 connected to the MOS transistor 30 as a capacitive element. These form a memory cell. The MOS transistor 30 includes a diffusion layer 33 serving as a source and a drain, and a gate electrode formed with a gate insulating film interposed therebetween. The gate electrode serves as a word line 34 of the memory cell.

[0004] One diffusion layer 33 of the MOS transistor 30 is connected to an electrode on the interlayer insulating layer 35 via a plug contact layer 38 made of, for example, polycrystalline silicon formed in a contact hole of the interlayer insulating layer 37. The other diffusion layer 33 is connected to the bit line 36 of the memory cell made up of layers, and the other diffusion layer 33 is connected to the capacitor 42 via the plug contact layer 38 made of, for example, polycrystalline silicon in the contact hole formed in the interlayer insulating layers 35 and 37. Connected to lower electrode 39.

The capacitor 42 has a cylindrical lower electrode (so-called node electrode) 39 made of, for example, polycrystalline silicon and an upper electrode (so-called plate electrode) made of, for example, polycrystalline silicon via a dielectric film 40 covering the lower electrode 39. 41 are formed. The cylindrical capacitor 42 is covered with an interlayer insulating layer 43a,
An upper wiring 44 made of aluminum or the like is formed thereon. An interlayer insulating film 43b further covers the upper wiring 44.

[0006] A large number of memory cells are
For example, the memory area 51 is formed in a matrix. On the other hand, around the memory area 51, for example, M
A logic region (that is, a peripheral circuit) 52 including an OS transistor is formed, and controls a memory cell and the like. That is, in the logic region 52, a diffusion layer 45 serving as a source and a drain is formed in the semiconductor substrate 31, and a gate electrode 47 is formed via a gate insulating film to form a MOS transistor.
A transistor is formed, and diffusion layer 45 and upper wiring 44 are connected by plug contact layer 46.

The cylindrical capacitor 42 is manufactured, for example, by the following method. First, on a semiconductor substrate 31 made of, for example, silicon, a structure as shown in FIG. 5, that is, an element isolation layer 32, a diffusion layer 33 serving as a source and a drain constituting the MOS transistor 30 of the memory cell, and a gate insulating film And a gate electrode, a word line 34; an interlayer insulating layer 35 between the word line 34 and the bit line 36;
And an interlayer insulating layer 37 covering the bit line 36 is formed.

Then, a resist is formed on the interlayer insulating layer 37 on the bit line 36, and a photoresist is patterned to open a contact hole, and the other diffusion layer of the MOS transistor 30 is formed in the interlayer insulating films 35 and 37. A contact hole for connecting the capacitor 33 and the capacitor 42 is opened. Subsequently, although not shown, a polycrystalline silicon layer is deposited so as to cover the inside and the surface of the contact hole.

Next, as shown in FIG. 6A, the polysilicon layer is etched back to form a plug contact layer 38 made of polysilicon. Further, as shown in FIG. 6B, a polycrystalline silicon layer 61 is deposited so as to cover the surface.

Next, as shown in FIG. 6C, a core insulating film 62 made of, for example, a silicon oxide film to be a core of the cylindrical capacitor is formed.

Next, after patterning the photoresist 63 formed on the core insulating film 62, the core insulating film 62 is etched using the photoresist 63 as a mask to form a core 62a as shown in FIG. 7D. I do.

Next, as shown in FIG. 7E, after removing the photoresist 63, a second polycrystalline silicon layer 64 is deposited to cover the surface and side surfaces of the core 62a.

Next, as shown in FIG. 7F, the second polycrystalline silicon layer 64 is etched back until the upper surface of the core 62a and the underlying interlayer insulating layer 37 are exposed, and polycrystalline silicon is formed on the side wall of the core 62a. Is formed.

Next, as shown in FIG. 8G, the core 62a is etched off by wet etching to form a cylindrical lower portion composed of the sidewall 65 made of polycrystalline silicon and the first polycrystalline silicon layer 61. An electrode 39 is formed. Subsequently, as shown in FIG. 8H, a dielectric film 40 composed of, for example, a nitride film-oxide film (a so-called NO film) is formed so as to cover the lower electrode 39.

Next, as shown in FIG. 8I, the dielectric film 40
Then, a third polycrystalline silicon layer serving as an upper electrode of the capacitor is deposited, and then the upper electrode 41 is formed by patterning the third polycrystalline silicon layer.
Can be manufactured.

[0016]

However, even when such a cylindrical capacitor 42 is formed, the cylindrical capacitor 42 must be formed at a high position in order to secure a desired capacitance. If the step is large, a problem of disconnection of the upper wiring 44 made of aluminum or the like to be formed later in the upper layer occurs.

If the step is large, the contact hole between the upper wiring 44 and the diffusion layer 33 in the semiconductor substrate 31 becomes deep, and the aspect ratio of the contact hole becomes large.
As a result, when the contact hole is formed by etching, the so-called microloading effect, which lowers the etch rate, is likely to occur.

In order to solve the above-mentioned problem, in the present invention, a sufficient capacity can be ensured and the size of a semiconductor device forming a capacitor can be reduced without increasing the level difference. A method for manufacturing a capacitor is provided.

[0019]

According to a method of manufacturing a capacitor of the present invention, a core made of a porous insulating film is formed, one electrode is formed on the surface of the core, and after removing the core, the surface of one electrode is formed. A counter electrode is formed via a dielectric film.

According to the manufacturing method of the present invention described above, by forming the core with the porous insulating film, it is possible to form irregularities on one electrode formed on the surface of the core and to increase the surface area of this electrode. Thus, the capacitance of the capacitor can be increased. Further, since the insulating film constituting the core is made porous, the etching rate at the time of etching the insulating film constituting the core becomes faster than in the case where the core is formed of a non-porous insulating film. Can be shortened in the step of etching the substrate.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a core made of a porous insulating film is formed, one electrode is formed on the surface of the core, and after the core is removed, a surface of one electrode is interposed with a dielectric film. This is a method for manufacturing a capacitor for forming a counter electrode.

An embodiment of the method for manufacturing a capacitor according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a semiconductor device to which a method of manufacturing a capacitor according to the present invention is applied, in this example, a DRAM which is a semiconductor memory.

In this DRAM, as described above, a memory cell is formed by a MOS transistor 27 formed in a region separated by an element isolation layer 2 of a semiconductor substrate 1 and a capacitor 12 as a capacitive element connected thereto. Be composed. The MOS transistor 27 includes a diffusion layer 3 serving as a source and a drain, and a gate electrode formed via a gate insulating film. The gate electrode serves as a word line 4 of the memory cell.

Then, one diffusion layer 3 of MOS transistor 27 is connected to an electrode on interlayer insulating layer 5a via plug contact layer 8 made of, for example, polycrystalline silicon formed in a contact hole of interlayer insulating layer 5a. The other diffusion layer 3 is connected to a bit line 6 of a memory cell made of a layer, and a plug contact layer 8 made of, for example, polysilicon in a contact hole formed in an interlayer insulating layer 5 (5a, 5b). Connected to lower electrode 9 of capacitor 12.

In this embodiment, a cylindrical lower electrode (so-called node electrode) 9 made of, for example, polycrystalline silicon having irregularities and an upper part made of, for example, polycrystalline silicon, An electrode (a so-called plate electrode) 11 is formed to form a cylindrical capacitor 12. The cylindrical capacitor 12 is covered with an interlayer insulating layer 13a, on which an upper wiring 14 made of aluminum or the like is formed. 13b
Is an interlayer insulating film that further covers the upper wiring 14.

A large number of memory cells configured as described above,
For example, the memory area 18 is formed in a matrix.

On the other hand, a logic area (peripheral circuit) 19 composed of, for example, a MOS transistor is formed around the memory area 18 to control a memory cell. That is, in the logic region 19, a diffusion layer 15 serving as a source and a drain is formed in the semiconductor substrate 1, and a gate electrode 17 is formed via a gate insulating film to form a MOS transistor. The wiring 14 is connected by the plug contact layer 16.

In the present invention, as will be described later, the capacitor 12 is manufactured by forming a core insulating film with a porous insulating film instead of the normal insulating film used in FIG. 7D. As a method for forming the porous insulating film, for example, TEO
There is a method of forming a porous silicon oxide film by a thermal CVD method using S and high-concentration ozone as a source gas (refer to literature Semiconductor World, January 1992, pages 140 to 153).

In particular, a thin silicon oxide film is formed on the underlying layer made of polycrystalline silicon by plasma CVD using TEOS and oxygen as raw materials, or the surface of the underlying layer made of polycrystalline silicon is thermally oxidized to form silicon oxide. When the film is formed thin, it becomes easier to form a more porous silicon oxide film.

Next, a method of manufacturing the capacitor 12 shown in FIG. 1 according to the present invention will be described with reference to the drawings. First, on a semiconductor substrate 1 made of, for example, silicon, a structure as shown in FIG. 1, that is, an element isolation layer 2, a diffusion layer 3 serving as a source and a drain constituting a MOS transistor 27 of a memory cell, and a gate insulating film And a gate electrode, a word line 4, an interlayer insulating layer 5a between the word line 4 and the bit line 6, and a bit line 6 formed by an electrode layer.
And an interlayer insulating layer 5b covering the bit line 6 is formed.

Then, a resist is formed on the interlayer insulating layer 5b, a photoresist is patterned for opening a contact hole, and the MOS transistor 27 is formed on the interlayer insulating film 5 (5a, 5b) under the following etching conditions. A contact hole for connecting the other diffusion layer 3 and the capacitor 12 is opened.

Apparatus: Magnetron RIE apparatus of the sheet type Gas: C ₄ F ₈ = 8 sccm, CO = 60 sccm, A
r = 200 sccm Pressure: 5.3 Pa Susceptor temperature: 20 ° C.

Subsequently, although not shown, a polycrystalline silicon layer is deposited under the following conditions so as to cover the inside and the surface of the contact hole. Apparatus: Low pressure CVD apparatus Gas: SiH ₄ / He / N ₂ / PH ₃ = 100/400
/ 200 / 50sccm Pressure: 70Pa Temperature: 550 ° C

Next, as shown in FIG. 2A, the polysilicon layer is etched back under the following conditions to form a plug contact layer 8 made of polysilicon. Apparatus: ECR etcher Gas: C ₂ Cl ₃ F ₃ / SF ₆ = 60/10 sccm Pressure: 1.3 Pa Microwave: 850 W RF output: 100 W Susceptor temperature: 20 ° C.

Next, as shown in FIG. 2B, a polycrystalline silicon layer 21 is deposited so as to cover the surface. The film forming conditions at this time may be the same as the film forming conditions for the polycrystalline silicon layer forming the plug contact layer 8.

Next, as shown in FIG. 2C, a porous insulating film 22 made of a porous silicon oxide film serving as a core of a cylindrical capacitor is formed under the following conditions. Apparatus: Normal pressure CVD apparatus Gas: TEOS = 100 sccm, O ₃ / O ₂ = 100
0 sccm (ozone concentration in oxygen 8%) Temperature: 350 ° C

Preferably, although not shown, before forming the porous insulating film 22, a thin plasma TEOS oxide film is formed under the following conditions, or the surface of the polycrystalline silicon layer 21 is kept at 850 ° C. for 20 minutes. When the thin film is oxidized with oxygen under the conditions, a porous insulating film 22 made of a more porous silicon oxide film is easily formed. Apparatus: Parallel plate plasma CVD apparatus Gas: TEOS / O ₂ = 800/600 sccm Pressure: 1133.2 Pa RF output: 1133.2 PaW Temperature: 400 ° C.

Next, after patterning the photoresist 23 formed on the porous insulating film 22, the core insulating film 22 is etched using the photoresist 23 as a mask under the following conditions, as shown in FIG. 3D. The core 22a is formed on the substrate. Apparatus: Parallel plate etcher Gas: C ₄ F ₈ = 50 sccm Pressure: 2 Pa RF output: 1200 W Susceptor temperature: 0 ° C.

Next, as shown in FIG. 3E, after removing the photoresist 23, a second polysilicon layer 24 is deposited under the following conditions so as to cover the surface and side surfaces of the core 22a. Apparatus: Low pressure CVD apparatus Gas: SiH ₄ / He / N ₂ / PH ₃ = 100/400
/ 200/50 sccm Pressure: 70 Pa Temperature: 550 ° C. At this time, since the core 22 a is formed of the porous insulating film, the second polycrystalline silicon layer 24 is formed with irregularities on the surface.

Next, as shown in FIG. 3F, the second polycrystalline silicon layer 24 is etched back under the following conditions until the upper surface of the core 22a and the underlying interlayer insulating layer 5 are exposed.
A side wall 25 made of polycrystalline silicon and having an uneven surface is formed on the side wall of the core 22a. Apparatus: ECR etcher Gas: CCl ₂ / O ₂ = 75/2 sccm Pressure: 0.4 Pa Microwave: 850 W RF output: 70 W Susceptor temperature: 20 ° C.

Next, the porous insulating film of the core 22a is etched off with hydrofluoric acid. Thereby, as shown in FIG. 4G, a cylindrical lower electrode 9 composed of the sidewall 25 made of polycrystalline silicon and having irregularities on the surface and the first polycrystalline silicon layer 21 is formed. In this example, since the core 22a is made of a porous insulating film, the etch rate of the core 22a is large,
The etch-off step 2a is completed in a much shorter time than in the case of the conventional manufacturing method shown in FIG. 8G.

Subsequently, although not shown, 85 in an NH ₃ atmosphere.
The surface of the lower electrode 9 made of polycrystalline silicon is thinly nitrided by performing a heat treatment at 0 ° C., and then a thin silicon nitride film is formed under the following conditions. Apparatus: Low pressure CVD apparatus Gas: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 50/200 /
200 sccm Pressure: 70 Pa Temperature: 700 ° C

Next, as shown in FIG. 4H, the surface of the lower electrode 9 is composed of a nitride film and an oxide film (a so-called NO film) due to the fact that the silicon nitride film is thinly oxidized by heat treatment at 850 ° C. in an oxygen atmosphere. The dielectric film 10 to be formed is formed.

Next, as shown in FIG.
And a third polycrystalline silicon layer 26 serving as an upper electrode of the capacitor is deposited under the following conditions. Apparatus: Low pressure CVD apparatus Gas: SiH ₄ / He / N ₂ / PH ₃ = 100/400
/ 200 / 50sccm Pressure: 70Pa Temperature: 550 ° C

Thereafter, although not shown, the third polycrystalline silicon layer 26 is patterned to form the upper electrode 11, and the capacitor 12 having the structure shown in FIG. 1 can be manufactured.

According to the above-described method for manufacturing a capacitor, by forming the core 22a with the porous insulating film, it is possible to form irregularities on the lower electrode 9 formed on the surface of the core 22a. Can be increased, so that the capacitance of the capacitor 12 can be increased.
Further, by making the insulating film 22 forming the core 22a porous, the etch rate at the time of etching the insulating film 22 forming the core 22a becomes faster than when the core is formed of a non-porous insulating film. Therefore, the time of the step of etching off the core 22a can be reduced.

Here, the following method has been proposed as a method of manufacturing the cylindrical capacitor 12 in which the lower electrode 9 having the unevenness shown in FIG. 1 is formed. For example, as shown in FIG. 9A, FIG.
Similarly to the above, a patterned polycrystalline silicon layer 61 and a side wall 65 made of polycrystalline silicon are formed. Then, the polycrystalline silicon of the side wall 65 is made porous by a method such as anodization to form a porous side wall 66, and the lower electrode 9 having a large surface area is formed by this and the porous silicon layer 61. Things.

According to the above-described method of manufacturing a capacitor of the present embodiment, in comparison with such a conventional manufacturing method, in the step of forming the core and the step of forming one of the electrodes, ie, the lower electrode, the porous material of the lower electrode is formed. The sidewalls can be formed in one fewer process steps, and the manufacturing process can be simplified. Further, according to the above-described method for manufacturing a capacitor, the time required in the step of etching off the core is significantly reduced because the core is porous as compared with such a conventional manufacturing method.

The method of manufacturing the capacitor of the present invention is not limited to the above-described example, and may take various other configurations without departing from the gist of the present invention.

[0050]

According to the above-described method of manufacturing a capacitor according to the present invention, by forming a core with a porous insulating film, it is possible to form irregularities on one of the electrodes formed on the surface of the core. Since the surface area of the capacitor can be increased, the capacitance of the capacitor can be increased. Also, by making the insulating film constituting the core porous,
Rather than forming a core with a non-porous insulating film,
Since the etching rate at the time of etching the insulating film constituting the core is increased, the step of etching the core itself can be shortened.

According to the manufacturing method of the present invention, as compared with the conventional manufacturing method in which one electrode is formed once and the unevenness is formed on this electrode, the unevenness is formed on one electrode in a smaller number of steps to manufacture a capacitor. can do.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram (cross-sectional view) of an example of a semiconductor device to which a method for manufacturing a capacitor according to the present invention is applied.

2A to 2C are process diagrams of a process for forming a capacitor according to the method of the present invention.

3A to 3F are process diagrams of a capacitor forming process according to the method of the present invention.

FIG. 4 is a process diagram of a process of forming a capacitor according to the present invention.

FIG. 5 is a schematic configuration diagram (cross-sectional view) of a semiconductor device having a conventional capacitor.

6A to 6C are process diagrams of a capacitor forming process according to a conventional manufacturing method.

7A to 7F are process diagrams of a capacitor forming process according to a conventional manufacturing method.

8A to 8G are process diagrams of a capacitor forming process according to a conventional manufacturing method.

FIGS. 9A and 9B are process diagrams of a capacitor forming process according to another conventional manufacturing method.

[Description of Signs] 1 semiconductor substrate, 2 element isolation layer, 3,15 diffusion layer,
4 word lines, 5, 5a, 5b, 13a, 13b
Interlayer insulating layer, 6 bit line, 8, 16 plug contact layer, 9 lower electrode, 10 dielectric film, 11 upper electrode, 12 capacitor, 14 upper layer wiring, 17 gate electrode, 18 memory area, 19 logic area (peripheral circuit) , 21 polycrystalline silicon layer, 22 porous insulating film, 22a core, 23 photoresist, 24 second polycrystalline silicon layer, 25 side wall, 26 third
Polycrystalline silicon layer, 27, 30 MOS transistor, 31 semiconductor substrate, 32 element isolation layer, 33, 45
Diffusion layer, 34 word lines, 35, 37, 43a,
43b interlayer insulating layer, 36 bit lines, 38, 46
Plug contact layer, 39 lower electrode, 40 dielectric film, 41 upper electrode, 42 capacitor, 44 upper layer wiring, 47 gate electrode, 51 memory area, 52 logic area (peripheral circuit), 61 polycrystalline silicon layer, 62
Core insulating film, 62a core, 63 photoresist, 6
4 second polycrystalline silicon layer, 65 sidewalls,
66 Porous sidewall

Claims (1)

[Claims] 1. A core made of a porous insulating film is formed, one electrode is formed on the surface of the core, and after removing the core, a counter electrode is formed on the surface of the one electrode via a dielectric film. Forming a capacitor.