JPH10214917A - Semiconductor device, its manufacture, and wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be improved easily in electrical characteristic, a method for manufacturing the device, and a wiring board. SOLUTION: A semiconductor device which can prevent the production of reflection noise in wiring lines and, accordingly, can be easily improved in electrical characteristic by making the characteristic impedance of the first and second parts 30A and 30B of the wiring lines nearly equal to each other when a bare chip 22 is operated, a method by which the semiconductor device can be manufactured, and a wiring board can be realized by manufacturing the wiring board carrying the wiring lines comprising the first parts 30A having a first line width and second parts 30B having a second line width which is narrower than that of the first parts 30a, and then, the semiconductor device by mounting the bare chip 22 on one surface of the wiring board in such a state that the backside of the chip 22 is faced oppositely to the surface of the wiring board and second parts 3B of the wiring lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order.

BACKGROUND OF THE INVENTION Prior Art (FIGS. 12 and 13) Problems to be Solved by the Invention (FIGS. 14 to 16) Means for Solving the Problems (FIGS. 1 to 11) Embodiment (1) Example (1-1) Configuration of BGA Package (FIGS. 1 to 3) (1-2) Manufacturing Procedure of BGA Package (FIGS. 4A to 4C)
(FIG. 10B) (1-3) Operation of Embodiment (1-4) Effect of Embodiment (2) Other Embodiment (FIG. 11) Effect of the Invention

[0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the semiconductor device, and a wiring board, and more particularly to a ball grid array (hereinafter referred to as a BGA package) and a method of manufacturing the same. It is preferable.

[0004]

2. Description of the Related Art Conventionally, this type of BGA package is configured as shown in FIGS. 12 and 13, for example.

That is, as shown in FIGS. 12 and 13,
In the BGA package 1, a bare chip 3 is provided on one surface 2A of a multilayer wiring board 2 with a back surface 3B facing the circuit surface 3A on a die pad 4 made of a conductive metal foil formed at the center of the one surface 2A. And the like, and are arranged so as to be joined via a conductive adhesive 5 made of, for example, and sealed by the sealing resin 6 so as to cover the circuit surface 3A.

Here, first, the multilayer wiring board 2 is provided with a ground layer 7 made of a plurality of conductive metal foils and a power supply layer 8 made of a plurality of conductive metal foils insulated inside an insulating substrate. A plurality of lands 9 made of conductive metal foil and wiring lines 10 electrically connected to the corresponding lands 9 are formed in a predetermined pattern around the die pad 4 of 2A, and wiring corresponding to the other surface 2B is formed. Line 10, ground layer 7 and / or power supply layer 8 and via 1
A plurality of external connection lands (hereinafter, referred to as external connection lands) 12 conductively connected through the first electrode 1 are formed in a lattice shape. Incidentally, the multilayer wiring board 2 has the other surface 2B.
A solder resist 14 is formed between the external connection lands 12 so as to insulate the external connection lands 12 from each other.

On the other hand, a plurality of pads 15 are provided at predetermined pitches on the circuit surface 3A of the bare chip 3 along the outermost periphery, and each pad 15 is connected to a corresponding land 9 on one surface 2A of the multilayer wiring board 2 respectively. They are electrically connected by wires 16 made of a conductive metal such as gold.

In this case, in the BGA package 1, an electrode made of a conductive metal (hereinafter, referred to as a spherical electrode) 17 is formed in a spherical shape on each of the external connection lands 12 on the other surface 2B of the multilayer wiring board 2. In this manner, the BGA package 1 is mounted on the motherboard (not shown) by bonding each spherical electrode 17 to a corresponding electrode of the motherboard (not shown), and in this state, the bare chip 3 is connected to each spherical electrode. Signals can be input from the motherboard via the multi-layer wiring board 17 and the multilayer wiring board 2 or signals can be output to the motherboard.

[0009]

Generally, in the multilayer wiring board 2, when the bare chip 3 operates,
The characteristic impedance value of the wiring line 10 is determined by the distance between the wiring line 10 and the ground layer 7 or the power supply layer 8. Therefore, for example, when a predetermined portion of the wiring line 10 and the ground layer 7 or the power supply layer 8 are located relatively close to each other, the characteristic impedance value of the predetermined portion of the wiring line 10 becomes the characteristic impedance of another portion of the wiring line 10. Wiring line 10
Therefore, it is known that a signal propagated in a predetermined direction is propagated in the predetermined direction in the opposite direction, that is, so-called reflection noise occurs.

That is, as shown in FIGS. 14A and 14B, for example, a wiring line 10 formed in an insulating material 18 is formed.
Is a predetermined distance Y relatively closer to the ground layer 7 (or power supply layer 8) than when it is located a predetermined distance X relatively far from the ground layer 7 (or power supply layer 8).
14A, the characteristic impedance value drops sharply and reflected noise occurs (FIG. 14A), and a predetermined portion of the wiring line 10 is sandwiched between the ground layer 7 and the power supply layer 8. Position causes reflection noise (Fig. 1
4 (B)).

By the way, as shown in FIG.
In the A package 1, one surface 2A of the multilayer wiring board 2
A die pad 4 slightly larger than the size of the circuit surface 3A of the bare chip 3 is formed, and a wiring line 10 is formed around the die pad 4.

However, in recent years, in the BGA package 1, the integration rate of the circuit of the
As the number of the chips increases, the size of the bear chip 3 tends to increase. For this reason, in the multilayer wiring board 2, the number of lands 9 formed on one surface 2A increases as the size of the bear chip 3 increases, and each land 9 is formed in a narrow pitch.
The wiring line 10 electrically connected to the land 9 also tends to be formed in a narrow pitch. Therefore, as shown in FIG. 16, in such a BGA package 1, a die pad 4 which is relatively smaller than the size of the circuit surface 3A of the bare chip 3 is formed on one surface 2A of the multilayer wiring board 2, and the wiring line 10 is formed. The predetermined portion is formed so as to face the back surface 3B of the bear chip 3.

However, in the BGA package 1,
Usually, the ground layer 7 connected to the ground of the motherboard in the multilayer wiring board 2 is electrically connected to the die pad 4 via the corresponding via 11 and wiring line 10, whereby the back surface 3B of the bare chip 3 is electrically conductive. It is grounded to the die pad 4 via the conductive adhesive 5.
Accordingly, in the BGA package 1, the back surface 3 of the
B is a predetermined portion of the wiring line 10 facing the back surface 3B.
, The characteristic impedance value of the predetermined portion is greatly reduced (may be about half as compared with other portions of the wiring line 10),
Reflection noise may occur in the wiring line 10. In this case, the BGA package 1 has a problem in that the bare chip 3 malfunctions and the electrical characteristics of the BGA package 1 are greatly reduced.

The present invention has been made in consideration of the above points, and has as its object to propose a semiconductor device, a method of manufacturing the semiconductor device, and a wiring board which can easily improve electrical characteristics.

[0015]

According to a first aspect of the present invention, there is provided a semiconductor device having a predetermined first line width on one surface of a wiring substrate and located on a periphery of a chip in a semiconductor device. A wiring line including a first portion and a second portion having a second line width smaller than the first line width of the first portion and facing the back surface of the chip is provided. .

According to a second aspect of the present invention, in the method for manufacturing a semiconductor device, the first semiconductor device having the first predetermined line width has
And a first step of manufacturing a wiring board in which a wiring line composed of a part and a second part having a second line width smaller than the first line width of the first part is formed on one surface. And a second step of mounting the bare chip on one surface of the wiring board with the one surface and the second portion of the wiring line facing the back surface of the bare chip.

According to a third aspect of the present invention, in the wiring board, a first portion having a predetermined first line width on one surface and located around a chip mounted on the one surface, A wiring line having a second line width smaller than the first line width of the portion and having a second portion located opposite to the back surface of the chip is provided.

Therefore, in the first invention, a first portion having a predetermined first line width on one surface of the wiring board, the first portion being located around the chip, and the first line width of the first portion being provided. By providing a wiring line having a narrower second line width and comprising a second portion located opposite to the back surface of the bare chip, the first wiring line is provided when the bare chip operates. By making the characteristic impedance value of the portion and the characteristic impedance value of the second portion substantially equal, it is possible to prevent the occurrence of reflection noise in the wiring line.

In the second invention, a first portion having a predetermined first line width and a second portion having a second line width smaller than the first line width of the first portion are provided. Then, a wiring board is formed on one surface of which the wiring line is formed, and then the bare chip is mounted on one surface of the wiring substrate with the one surface and the second portion of the wiring line facing the back surface of the bare chip. As a result, when the bare chip operates, the characteristic impedance value of the first portion of the wiring line and the characteristic impedance value of the second portion of the wiring line become substantially equal, and the occurrence of reflection noise in the wiring line is prevented. A semiconductor device that can be manufactured can be easily manufactured by a manufacturing method that is almost the same as a conventional semiconductor device manufacturing method.

Further, in the third aspect of the present invention, the first portion having a predetermined first line width on one surface of the wiring board and located around the bare chip and the first line width of the first portion are provided. Has a narrow second line width and is provided with a wiring line composed of a second portion located opposite to the back surface of the chip mounted on the one surface, so that one surface of the wiring board is actually provided. When the chip mounted on the wiring line operates, the characteristic impedance value of the first part of the wiring line and the characteristic impedance value of the second part of the wiring line are made substantially equal to each other to prevent the occurrence of reflection noise in the wiring line. can do.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Embodiment (1-1) Configuration of BGA Package In FIG. 1, reference numeral 20 denotes a B to which the present invention is applied as a whole.
5A shows a GA package, and one surface 21A of a multilayer wiring board 21;
On the top, the back surface 2 where the chip 22 faces the circuit surface 22A
2B is bonded to a die pad 23 made of a conductive metal foil formed at the center of one surface 21A of the multilayer wiring board 21 via a conductive adhesive 24 made of silver paste or the like, and covers the circuit surface 22A. Is sealed by the sealing resin 25 as described above.

Here, the multilayer wiring board 21 has a four-layer structure in which a ground layer 27 made of a plurality of conductive metal foils and a power supply layer 28 made of a plurality of conductive metal foils are provided in an insulating substrate. A plurality of lands 29 made of conductive metal foil are formed in a predetermined pattern around a die pad 23 on one surface 21A, and wiring lines 30 electrically connected to the corresponding lands 29 and the die pad 23 are formed on the other surface. A plurality of external connection lands 32 electrically connected to the wiring lines 30, the ground layers 27 and / or the power supply layers 28 via the vias 31 respectively corresponding to 21B are formed in a lattice shape.

In this case, in the multilayer wiring board 21, one surface 21
The size of the die pad 23 formed on the chip A is
2 is smaller than the size of the circuit surface 22A, and a predetermined portion of the wiring line 30 formed around the die pad 23 is formed so as to face the back surface 22B of the bare chip 22. Incidentally, a solder resist 33 is formed on one surface 21A of the multilayer wiring board 21 so as to expose each land 29 and the die pad 23 and to cover the wiring line 30, so that the wiring line 30 can be protected from deterioration due to moisture. It has been made like that.

On the other hand, the bare chip 22 has a plurality of pads 34 provided on a predetermined pitch along the outermost periphery of the circuit surface 22A, each of which has a corresponding land 29 on the one surface 21A of the multilayer wiring board 21 and a wire made of a conductive metal such as gold. 35, thereby electrically connecting the first surface 2 of the multilayer wiring board 21
1A.

In this case, the BGA package 20 has a solder resist 36 coated between the external connection lands 32 on the other surface 21B of the multilayer wiring board 21 and a solder or the like on each of the external connection lands 32. The spherical electrodes 37 made of a conductive metal are provided, whereby each of the spherical electrodes 35 is joined to a corresponding electrode of a motherboard (not shown) and mounted on the motherboard.

In this state, the BGA package 20
When the ground layer 27 of the multilayer wiring board 21 is grounded to the ground of the motherboard, the back surface 22B of the bare chip 22 is grounded via the die pad 23 conductively connected to the ground layer 27, and the power supply layer 2
8 is connected to the power supply of the motherboard, so that the pad 34 of the bear 22 is electrically connected to the power supply layer 28.
Is supplied with electricity, and thus the bead 22 is connected to each spherical electrode 37.
And a multilayer wiring board 21 to input a signal from a motherboard or output a signal.

As shown in FIG. 2, a die pad 23 smaller than the circuit surface 22A of the bare chip 22 is formed on one surface 21A of the multilayer wiring board 21 in the BGA package 20, and is joined to the die pad 23. Each land 29 is formed around the periphery of the chip 22, and one end of each of the plurality of wiring lines 30 electrically connected to the corresponding land 29 is formed so as to face the back surface 22 </ b> B of the chip 22. You. Incidentally, the wiring line 30 has a portion (hereinafter referred to as a first portion) 30A located around the chip 22 and has a portion facing the back surface 22B of the chip 22 (refer to the first line width). Hereinafter, this is referred to as a second portion.)
The second line width of 30B is formed to be narrow. In a predetermined position of the wiring line 30, a via 35 electrically connected to the wiring line 30 is formed.

In this case, as shown in FIG.
0 indicates that the first portion 3
0A and the second portion 3 facing the back surface 22A functioning as the ground of the bare chip 22.
0B and the second line width a of the first portion so that the characteristic impedance value becomes substantially equal to the second line width a.
Is selected, for example, the second line width b of the second portion 30B is set to the first portion 30A.
Is selected so as to be about 25% with respect to the first line width a. Further, in the wiring line 30, the first line 30A and the second portion 30B extend over the same length as the first line width a of the first portion 30A. The tapered portion is formed so as to be narrowed in the width a direction, and the tapered portion is located near the peripheral side surface of the bearing 22. Thereby, the wiring line 30 becomes
The characteristic impedance value can be prevented from abruptly changing in the vicinity of facing the peripheral side surface of the chip 22.

(1-2) Manufacturing Procedure of BGA Package Here, the BGA package 20 can be actually manufactured by the following procedure shown in FIGS. 4 (A) to 10 (B).

That is, first, as shown in FIG. 4A, a predetermined insulating substrate 4 having a thickness of, for example, about 200 [μm].
A double-sided substrate 43 is prepared by laminating predetermined conductive metal foils 41 and 42 each having a thickness of, for example, about 35 [μm] on both sides of the substrate.

Thereafter, as shown in FIG. 4B, the conductive metal foil 41 on one surface 43A of the double-sided substrate 43 and the conductive metal foil 42 on the other surface 43B are patterned by a method such as an etching method. As a result, the ground layer 27 made of a plurality (or a single) conductive metal foil 41 is formed on one surface 43A of the double-sided substrate 43, and the plurality (or a single) conductive metal foil 42 is formed on the other surface 43B of the double-sided substrate 43. Is formed. The ground layer 27 and the power supply layer 28 are formed of a plurality of conductive metal foils 41 and 42, respectively.
Is formed at a predetermined interval so as to prevent a short circuit between the conductive metal foils 41 and 42.

Next, as shown in FIG. 4C, a first prepreg (bonding sheet) having a thickness of, for example, about 100 [μm] and having an insulating property and an adhesive property is formed on the ground layer 27 of the double-sided board 43. ) 45 and a predetermined conductive metal foil 46 having a thickness of, for example, about 12 [μm] are sequentially laminated and thermocompression-bonded, and a thickness of, for example, about 100 [μm] is also formed on the power supply layer 28. A second prepreg (bonding sheet) 47 having a thickness of, for example, and a predetermined conductive metal foil 48 having a thickness of, for example, about 12 [μm] are sequentially laminated and thermocompression-bonded. Thus, a four-layer board 49 serving as a basis of the multilayer wiring board 21 is formed.

Subsequently, as shown in FIG. 5 (A), via holes are drilled from one surface to the other surface at a plurality of predetermined positions on one surface of the four-layer plate 49 using a drill or the like. A portion other than the inner peripheral surface and the opening of the via hole is covered with a resist, and in this state, a conductive metal is formed on the inner peripheral surface and the opening of each via hole by a method such as a plating method to form a plurality of vias 31. Thereby, each via 31
Are electrically connected to the corresponding ground layer 27 or power supply layer 28, respectively. Incidentally, the resist applied to portions other than the inner peripheral surface and the opening of each via hole is peeled off by washing after finishing the plating.

Next, as shown in FIG.
9 by patterning the conductive metal foil 46 on the first prepreg 45 by a method such as an etching method, thereby forming the die pad 23 made of the conductive metal foil 46 at the center on the first prepreg 45. And a conductive metal foil 4 around the die pad 23 in a predetermined pattern.
6 and a plurality of lands 29 and wiring lines 30 electrically connected to the corresponding lands 29 and the corresponding vias 31 are formed. In addition to this, the four-layer plate 49
By patterning the conductive metal foil 48 on the second prepreg 47 by a method such as an etching method,
A plurality of external connection lands 32 made of the conductive metal foil 48 electrically connected to the corresponding vias 31 on the second prepreg 47 are formed in a grid pattern.

As shown in FIG. 6, each land 29 is positioned on the first prepreg 45 of the four-layer plate 49 at a position around the bear chip 22 when the bear chip 22 is arranged on the die pad 23. While being formed to
Among the wiring lines 30 electrically conductively connected to the corresponding lands 29, the wiring line 30 having the second portion 30B facing the back surface 22B of the bear chip 22 is the second one.
Is formed so that the second line width of the portion 30B is narrower than the first line width of the first portion 30A of the wiring line 30.

By the way, as shown in FIG.
A and the wiring line 30 having the second portion 30B
The first line width of the first portion 30A is, for example, 160
[Μm] and the second line width of the second portion 30B is about 25 [%] of the first line width of the first portion 30A, for example, about 40 [μm]. It is formed so that Also, in this wiring line 30,
The distance between the first portion 30A and the second portion 30B is substantially equal to the first line width of the first portion 30A.
It is formed in a tapered shape over a length of about [μm].

Subsequently, as shown in FIG. 5C, a solder resist 33 is applied on the first prepreg 45 so that the die pad 23 and each land 29 are exposed, for example, 50 μm.
m]. Thus, a multilayer wiring board 21 having a four-layer structure can be manufactured.

Thereafter, as shown in FIG. 8A, the die pad 23 located on one surface 21A (on the first prepreg 45) of the multilayer wiring board 21 is formed so as to be substantially the same height as the upper surface of the solder resist 33. A conductive adhesive 24 made of silver paste or the like is applied.

Subsequently, as shown in FIG. 8B, the upper surface of the die pad 23 and the back surface 22 B of the bear chip 22 are opposed to each other, and the bear chip 22 is mounted on the die pad 23 via a conductive adhesive 24. Then, the conductive adhesive 2
4 is heated and cured at a temperature of, for example, about 170 ° C. for about 90 minutes to bond the bare chip 22 onto the die pad 23 via the conductive adhesive 24.

Next, as shown in FIG. 8C, the circuit surface 22 of the bare chip 22 is formed by a wire bonding method.
Each pad 34 of A is connected to a corresponding land 29 on one surface 21A of the multilayer wiring board 21 via a wire 35 made of a conductive metal such as gold. As a result, the bare chip 22 is placed on the one surface 21 of the multilayer wiring board 21 and the back surface 22 thereof.
B can be mounted facing the one surface 21A.

Subsequently, as shown in FIG. 9A, the circuit surface 22A of the
Then, an insulating sealing resin 25 is applied so as to cover each wire 35, and then the sealing resin 25 is heated and cured at a predetermined temperature, so that one surface of the multilayer wiring board 21 is formed by the sealing resin 25. The chip 22 is sealed with 21A.

Next, as shown in FIG. 9B, a solder resist 36 is formed between the external connection lands 32 on the other surface 21 B of the multilayer wiring board 21 (on the second prepreg 47).

Subsequently, as shown in FIG. 10A, a solder paste 51 is applied to each of the external connection lands 32 on the other surface 21B of the multilayer wiring board 21.

Thereafter, as shown in FIG. 10B, the solder paste 51 applied on each of the external connection lands 32 is heated at, for example, about 200 ° C. so that each of the solder pastes 51 is melted. As a result, spherical electrodes 37 are formed on the external connection lands 32, respectively. Thus, the BGA package 20 can be manufactured by the above-described manufacturing procedure.

(1-3) Operation of Embodiment In the above configuration, in the BGA package 20, the ground layer 27 is formed on one surface 43A of the double-sided substrate 43, and the power supply layer 2 is formed on the other surface 43B of the double-sided substrate 43.
8 (FIGS. 4 (A) and 4 (B)). Thereafter, the first prepreg 45 and the conductive metal foil 46 are sequentially laminated on the ground layer 27 of the double-sided substrate 43, and the power supply layer 2 is formed.
8, a second prepreg 47 and a conductive metal foil 48 are sequentially laminated to form a four-layer plate 49 (FIG. 4).
(C)).

Next, the first prepreg 45 of the four-layer plate 49
A die pad 23 is formed in the upper central portion, and a plurality of lands 29 around the die pad 23 are formed, and the corresponding lands 29 and the wiring lines 30 electrically connected to the die pad 23 are formed. A plurality of external connection lands 32 are formed in a grid on the second prepreg 47.

In this case, the wiring line 30 is connected to the bare chip 2
2 operates, the second line width of the second portion 30B is selected such that the characteristic impedance values of the first portion 30A and the second portion 30B are substantially equal, respectively. The second line width of the second portion 30B is formed to be smaller than the first line width of the first portion 30A (FIG. 5A).

Subsequently, a plurality of vias 31 are formed in the four-layer board 49, and the corresponding wiring lines 3
0, the ground layer 27, the power supply layer 28, and / or the external connection land 32 are conductively connected (FIG. 5B), and then the solder is formed on the first prepreg 45 so that the die pad 23 and each land 29 are exposed. By forming a film of the resist 33, the multilayer wiring board 21 having a four-layer structure is manufactured (FIG. 5C).

Next, the conductive adhesive 2 is placed on the die pad 23.
Then, the bare chips 22 are joined via the wires 4 (FIGS. 8A and 8B). Thereafter, the pads 34 of the bare chips 22 and the corresponding lands 29 on the one surface 21A of the multilayer wiring board 21 are connected via the wires 35. Then, the bare chip 22 is mounted on one surface 21A of the multilayer wiring board 21 by conducting connection (FIG. 8C). Subsequently, the bare chip 22 is sealed on one surface 21A of the multilayer wiring board 21 with a sealing resin 25, and thereafter a solder resist 36 is formed on the other surface 21B of the multilayer wiring board 21 between the external connection lands 32 by coating. At the same time, a spherical electrode 37 is formed on each external connection land 32 (FIGS. 9A to 10B). Thus, the BGA package 20 can be manufactured.

Accordingly, in such a method of manufacturing the BGA package 20, when the wiring lines 30 are formed on the one surface 21A of the multilayer wiring board 21, a method such as an etching method generally used conventionally is used. A first portion 30A having a first line width of approximately 160 [μm] and a second portion of approximately 40 [μm] which is approximately 25 [%] of the first line width of the first portion 30A. By forming the wiring line 30 including the second portion 30B having the line width of 1 mm, when the bare chip 22 of the manufactured BGA package 20 operates, the first line of the wiring line 30 is formed.
BGA package 2 in which the characteristic impedance values of the portion 30A and the second portion 30B are substantially equal to each other and can prevent occurrence of reflection noise in the wiring line 30
0 can be easily manufactured by almost the same manufacturing procedure as that of manufacturing a conventional BGA package.

In the BGA package 20 manufactured according to such a manufacturing procedure, the second portion 30B of the wiring line 30 formed on the one surface 21A of the multilayer wiring board 21 opposes the back surface 22B of the bare chip 22. Has a first line width of about 160 [μm], and the second part 30B has a first line width of about 160 μm.
40, which is approximately 25% of the first line width of the portion 30A of FIG.
By having the second line width of about [μm], the characteristic impedance value of the first portion 30A of the wiring line 30 becomes, for example, about 45 [Ω] when the bare chip 22 operates. , The second portion 30B
Characteristic impedance value of the first portion 30A
For example, about 45 [Ω], which is substantially the same as above, thus preventing a sharp decrease in the characteristic impedance value at the second portion 30B of the wiring line 30 and preventing the generation of reflection noise at the second portion 30B of the wiring line 30. Can be prevented.

(1-4) Effects of Embodiment According to the above configuration, one surface 21A of the multilayer wiring board 21
A first portion 30A having a predetermined first line width and located around the chip 22 and a predetermined second line width smaller than the first line width and having a predetermined second line width. 2nd part 30 located opposite back 22B of
B is provided so that when the bare chip 22 operates, the wiring line 3
0, the characteristic impedance value of the first portion 30A is substantially equal to the characteristic impedance value of the second portion 30B, so that the occurrence of reflection noise in the wiring line 30 can be prevented. Can be realized easily.

Further, it has a first line width,
2 and a second portion 30 having a second line width smaller than the first line width and facing the back surface 22B of the chip 22.
B to form a multilayer wiring board 21 having a wiring line 30 formed on one surface 21A.
The first portion 30A of the wiring line 30 is formed when the bare chip 22 is operated by mounting the bare chip 22 on the first surface 21A of the multilayer wiring board 21 with its back surface 22B facing the one surface 21A of the multilayer wiring board 21. And the second portion 30B have substantially the same characteristic impedance value, and the BGA package 20 capable of preventing the generation of reflection noise in the wiring line 30 is manufactured in substantially the same manufacturing procedure as that for manufacturing a conventional BGA package. A method of manufacturing a semiconductor device that can be easily manufactured and thus can easily manufacture a semiconductor device whose electrical characteristics can be easily improved can be realized.

Further, on one surface 21 A of the multilayer wiring board 21,
A first portion 30A having a predetermined first line width and located around the bear chip 22; and a second portion 30 having a predetermined second line width smaller than the first line width.
2 is provided with a second portion 30B opposed to the back surface 22B of the second chip 2 so that when the bare chip 22 operates, the wiring line 30
Characteristic impedance value of the first portion 30A of
By making the characteristic impedance value of the second portion 30B substantially equal, the occurrence of reflection noise in the wiring line 30 can be prevented, and thus a wiring board that can easily improve the electrical characteristics can be realized. .

(2) Other Embodiments In the above-described embodiment, the case where the present invention is applied to the BGA package 20 provided with the four-layered multilayer wiring board 21 has been described. The present invention is not limited to this, and may be applied to a BGA package provided with a multilayer wiring board having a multilayer structure of two or more layers.
In this case, the same effect as in the above embodiment can be obtained.

In the above embodiment, the wiring line 30 is formed such that the second line width of the second portion 30B is approximately 25% of the first line width of the first portion 30A. However, the present invention is not limited to this, and the first portion 30A of the wiring line 30 is
If the characteristic impedance value of the second part 30B can be made substantially equal, the wiring line 30
The second line width of the second part 30B is changed to the first part 30.
25% or more or 25% of the first line width of A
You may make it form so that it may become the following ratios.

Further, in the above-described embodiment, the wiring line 3 composed of the first portion 30A and the second portion 30B
0, the first portion 30A and the second portion 30B are formed in a tapered shape so as to be narrowed in the first line width direction. However, the present invention is not limited to this. For example, as shown in FIGS. 11A to 11C, a first portion 60A and a second portion 60 like a wiring line 60 are provided.
B is formed in a tapered shape so as to be narrowed only from one side along the first line width (FIG. 11A), or a first portion 61A such as a wiring line 61 and a second portion 61A are formed. Between the first portion 62A and the first portion 62A as shown in FIG. 11 (B). As shown in FIG. 11 (C) or the like, the gap between the second portion 62B and the second portion 62B is formed on both sides along the first line width.
A portion between the first portion and the second portion of the wiring line may be formed in various other shapes.

Further, in the above-described embodiment, in the manufacturing procedure of the BGA package 20, the first prepreg 4
5, the solder resist 33 is formed to have a thickness of, for example, about 50 [μm] so as to expose the die pad 23 and each land 29 (FIG. 5C). The present invention is not limited to this, and the solder resist 33 may be formed so as to have a thickness of about 50 μm or more or about 50 μm or less.

Further, in the above embodiment, in the manufacturing procedure of the BGA package 20, the first prepreg 45 having a thickness of about 100 μm is formed on the ground layer 27 of the double-sided board 43, On layer 28
Second prepreg 47 having a thickness of about 100 [μm]
(FIG. 4 (C)), but the present invention is not limited to this, and 100 [μm] is respectively provided on the ground layer 27 and the power supply layer 28 of the double-sided board 43.
A prepreg having a thickness of about 100 μm or more or about 100 μm or less may be laminated.

Further, in the above embodiment, the case where the present invention is applied to the BGA package 20 and its manufacturing method has been described. However, the present invention is not limited to this.
For example, on a surface of a single-layer or multi-layer wiring board such as a chip size package or a pin grid array, a bare chip has its back surface opposed to the one surface, and the back surface is grounded. The present invention may be applied to other various semiconductor devices to be mounted and a manufacturing method thereof. Alternatively, the present invention may be applied to a single-layer or multi-layer wiring board in which a back surface is mounted on one surface with the back surface facing the one surface and the back surface is connected to ground.

[0062]

As described above, according to the present invention, on one surface of a wiring board, a first portion having a predetermined first line width and located around the chip and a first portion of the first portion. A line having a second line width smaller than the line width of the first chip and having a second portion positioned opposite to the back surface of the bare chip is provided. The characteristic impedance value of the first portion of the line and the characteristic impedance value of the second portion can be made substantially equal to prevent the occurrence of reflection noise in the wiring line 30. Thus, the electrical characteristics can be easily improved. A semiconductor device that can be improved can be realized.

A wiring line including a first portion having a predetermined first line width and a second portion having a second line width smaller than the first line width of the first portion is formed. By producing the wiring board formed on one surface, and then mounting the bare chip on one surface of the wiring substrate with the one surface and the second portion of the wiring line facing the back surface of the bare chip, When the semiconductor device is operated, the characteristic impedance value of the first portion of the wiring line is substantially equal to the characteristic impedance value of the second portion of the wiring line, and the occurrence of reflection noise in the wiring line can be prevented. The semiconductor device can be easily manufactured by substantially the same manufacturing method as the conventional semiconductor device manufacturing method, and thus the semiconductor device capable of easily improving the electrical characteristics can be easily manufactured. It is possible to realize a manufacturing method of the conductor arrangement.

Further, one surface has a predetermined first line width, and a first portion located around a chip mounted on the one surface and a first line width smaller than the first line width of the first portion. By providing a wiring line having a second line width and including a second portion located opposite to the back surface of the bear chip, the wiring line is provided when the bare chip actually mounted on one surface operates. The characteristic impedance value of the first portion of the line and the characteristic impedance value of the second portion can be made substantially equal to prevent the occurrence of reflection noise in the wiring line 30. Thus, the electrical characteristics can be easily improved. A wiring board that can be improved can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is a top view for explaining a wiring line formed on one surface of a multilayer wiring board;

FIG. 3 is a schematic top view for explaining a wiring line;

FIG. 4 is a schematic sectional view showing a procedure for manufacturing a BGA package.

FIG. 5 is a schematic sectional view showing a procedure for manufacturing a BGA package.

FIG. 6 is a schematic top view for explaining a wiring line formed on a first prepreg;

FIG. 7 is a schematic top view for explaining a wiring line;

FIG. 8 is a schematic sectional view showing a procedure for manufacturing a BGA package.

FIG. 9 is a schematic sectional view showing a procedure for manufacturing a BGA package.

FIG. 10 is a schematic sectional view showing a manufacturing procedure of the BGA package.

FIG. 11 is a schematic top view for explaining the shape of a wiring line according to another embodiment.

FIG. 12 is a partially cutaway perspective view showing a configuration of a conventional BGA package.

FIG. 13 is a schematic sectional view showing a configuration of a conventional BGA package.

FIG. 14 is a schematic cross-sectional view for explaining generation of reflection noise in a wiring line;

FIG. 15 is a schematic top view for explaining a wiring line formed on one surface of a conventional multilayer wiring board.

FIG. 16 is a schematic top view for explaining wiring lines formed on one surface of a multilayer wiring board of a BGA package when the integration ratio of a circuit of a bare chip is improved.

[Explanation of symbols]

20 BGA package, 21 Multi-layer wiring board, 2
1 ... one side, 22 ... bee chip, 22A ... circuit side,
22B ... back surface, 23 ... die pad, 30 ... wiring line, 30A, 60A, 61A, 62A ... first part, 30B, 60B, 61B, 62B ... second part.

Claims (6)

[Claims] 1. A printed circuit board having a wiring line formed on one surface thereof, a back surface facing a circuit surface of the bare chip facing the one surface of the wiring substrate, and the back surface is grounded to mount the bare chip. In the semiconductor device, the wiring line has a predetermined first line width, a first portion located around the bare chip, and a first portion narrower than the first line width of the first portion. A second portion having a line width of 2 and comprising a second portion located opposite to the back surface of the bare chip. 2. The wiring line according to claim 1, wherein when the bare chip mounted on the one surface of the wiring board operates, a characteristic impedance value of the first portion and a characteristic impedance value of the second portion have 2. The semiconductor device according to claim 1, wherein the second line width of the second portion with respect to the first line width of the first portion is selected so as to be substantially equal to the value. 3. . 3. A surface of the wiring substrate on which the wiring lines are formed, a back surface facing the circuit surface of the bare chip facing the one surface of the wiring substrate, and the back surface is grounded to mount the bare chip. A method for manufacturing a semiconductor device, comprising: a first portion having a predetermined first line width;
A first step of manufacturing the wiring board on which a wiring line including a second part having a second line width smaller than the first line width of the part is formed on the one surface; A second step of mounting the bare chip on the one surface of the wiring substrate with the back surface facing the one surface of the wiring substrate and the second portion of the wiring line. Device manufacturing method. 4. The first step comprises: when the bare chip mounted on the one surface of the wiring board operates, the characteristic impedance value of the first portion of the wiring line and the second impedance of the second portion. The second line width of the second portion with respect to the first line width of the first portion is selected so that the characteristic impedance value of the portion has substantially the same value. 4. The method for manufacturing a semiconductor device according to item 3. 5. A wiring board on a surface on which a wiring line is formed, the back surface facing the circuit surface of the bare chip facing the one surface, and the back surface is grounded and the bare chip is mounted. The line has a predetermined first line width, a first portion located around a chip mounted on the one surface, and a second portion narrower than the first line width of the first portion. A wiring portion having a line width of? And a second portion located opposite to the back surface of the bare chip. 6. The wiring line has a characteristic impedance value of the first portion when the bare chip mounted on the one side operates, and
The second line width of the second part with respect to the first line width of the first part is selected so that the characteristic impedance value of the second part is substantially equal. The wiring board according to claim 5, wherein