JPH10214911A - Substrate for mounting semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the height unevenness of solder bumps and improve the peeling strength of lands and, at the same time, to shorten the mutual distance between the lands. SOLUTION: Insulating layers 13 are provided on a substrate 1 on which rectangular lands 11 are provided and openings 12 which have the same shape as those the lands 11 have are formed through the layers 13 so that the longer sides of the openings 12 can become perpendicular to those of the lands 11 and the central parts of the lands 11 can be exposed. Therefore, the machining accuracy of the lands 11 and openings 12 can be improved and the height unevenness of solder bumps can be suppressed. In addition, the mutual distance between the lands 11 can be shortened. Moreover, since the insulating layers 13 retain both end sections of the lands 11 in the longitudinal directions of the lands 11, the peeling strengths of the lands 11 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate on which a semiconductor device is mounted, for example, a ball grid array (Ball grid array).
The present invention relates to a substrate applied to a Grid Array (hereinafter, referred to as BGA) package and a mounting substrate on which the BGA package is mounted.

[0002]

2. Description of the Related Art In a BGA package, solder bumps are two-dimensionally arranged on the bottom surface of the package. FIG.
The back surface of the GA package is shown, and FIG. 9 is a sectional view thereof. A plurality of wirings 2 and pads 4 are formed on one surface of the circuit board 1, and bumps 5 are formed on the pads 4. The wiring 2 and the pads 4 other than the solder bumps 5 are covered with the insulating layer 3. The insulating layer 3 is formed to protect the wiring. When the substrate 1 is made of a resin, for example, an epoxy resin is used. When the substrate 1 is made of a ceramic material, the insulating layer 3 is formed of alumina or the like. The solder bump 5 is made of a lead-tin alloy.
An IC chip 6 connected to the wiring 2 and the pad 4 is disposed on the other surface of the circuit board 1, and the IC chip 6 is sealed with a resin 7.

FIGS. 10 to 12 show steps for forming the solder bumps 5. FIG.
4 shows a step of applying the flux 8 to the substrate. In FIG. 10, an opening 3a for exposing the pad 4 is formed in the insulating layer 3, and a flux 8 is applied to each pad 4 exposed from the opening 3a. The flux 8 removes an oxide film on the surface of the pad 4 and the solder ball 9 described later, and improves the wettability of the solder on the pad. The flux 8 is transferred onto the pad by a method such as dispensing, printing, or transferring.

FIG. 11 shows a process of arranging the solder balls 9 on the pads. In FIG. 11, the solder balls 9
Are arranged on an arrangement jig (not shown), and are transferred onto the flux 8 in this state.

FIG. 12 shows a process of melting the solder balls 9 and forming the solder bumps 5. In FIG. 12, the solder ball 9 is heated to a temperature higher than the melting point and melted to fix the solder ball 9 to the pad 4. At this time, the solder bump 5 becomes spherical due to the surface tension of the solder.

FIG. 13 shows a state in which a BGA package is mounted on a mounting board. The mounting board 80 has a plurality of pads 8 corresponding to the pads 4 arranged on the circuit board 1.
1 are arranged, and these pads 81 are covered with the insulating layer 3. The insulating layer 3 has an opening 82 exposing the surface of the pad 81. The circuit board 1
The solder bumps 5 mounted on the mounting board 80
After that, the solder bumps 5 are melted and fixed to the pads 81.

In a BGA package, more terminals can be arranged at a wider pitch than a QFP (Quad Flat Package) in which terminals can be arranged only around the package.
Moreover, it has a feature that the mounting yield is high. Conventionally, the pitch of BGA has been mainly 1.27 mm.
However, at present, the pitch is getting finer,
A 0.5 mm pitch BGA has also been reported.

[0008] The height of the solder bump is determined by the volume of the solder bump 5 and the area of the pad 4. Solder bump 5
Is formed by melting the solder bumps 9 on the pads as described above. At this time, if the area of the pad 4 increases, the solder ball 9 melts and spreads, so that the final height of the solder bump 5 decreases. In addition, when the volume of the solder ball 9 increases, the final height of the solder bump 5 increases.

[0009] In the BGA, variations in the height of the solder bumps 5 greatly affect the mounting yield. Further, after connection to the mounting board 11, the variation in the height of the solder bumps 5 affects long-term reliability. Also in this case, the variation in the volume of the solder ball 9 and the variation in the area of the pad 4 affect the variation in the height of the solder bump after connection.

The size variation of the solder balls 9 is about ± 10 μm. The variation in the area of the pad 4 differs depending on the structure. 14 to 17 show the structure of a conventionally used pad.

In FIG. 14 and FIG. 15, an opening 91 is formed in the insulating layer 3, and the entire land 92 is exposed from the opening 91. In this configuration, the area of the pad 93 is defined by the area of the land 92 (here, the size of the land 92), and the variation is affected by the dimensional variation of the land 92. That is, if the size of the pad 93 is D, the variation Δ
S is represented by equation (1).

ΔS = 2D · ΔD ₁ (1) where ΔD ₁ is the processing accuracy of the land 92 and is usually ±
20 μm. 16 and 17 show another example of the conventional pad structure, and the same parts as those in FIGS. 14 and 15 are denoted by the same reference numerals. In the case of this example, only a part of the surface of the land 92 is exposed from the opening 91, and the substrate 1 is not exposed at all from the opening 91. In the case of such a configuration, the area of the pad 93 is defined by the area of the opening 91, and its variation is affected by the processing accuracy of the opening 91.
That is, the size of the pad 93 (here, the opening 91
Is equal to D), the variation ΔS of the area of the pad is represented by the equation (2).

ΔS = 2D · ΔD ₂ (2) where ΔD ₂ is the processing accuracy of the opening 91 and is usually ±
50 μm. Normally, the processing accuracy of the land 92 is smaller than the processing accuracy of the opening 91. Therefore, when the pad structure is configured as shown in FIG. 14, variation in the height of the solder bumps 5 can be reduced. In the above description, the pad 93 and the opening 91 have been described as circular, but the same applies to a case where the pad 93 and the opening 91 are square.

[0014]

As described above, the BG
The pitch of the solder bumps of A is becoming finer, and the shape of the lands is becoming smaller. As the land becomes smaller, the adhesion strength between the land and the substrate decreases, and the reliability of the solder bump decreases. Therefore, when the size of the pad is, for example, 250 μm or less, the structure of the pad needs to be as shown in FIG. In this case, the size of the pad 93 indicates the size of the opening 91. In such a case, the size of the land 92 is represented by Expression (3).

D _L = D _P + ΔD ₁ + 2Δx (3) where D _L is the size of the land 92 and D _P is the opening 91.
ΔD ₁ is the processing accuracy of the opening 91, and Δx is the deviation between the center of the opening 91 and the center of the land 92. When the above values are used, ΔD ₁ = 50 μm. Also,
Usually, Δx = 50 μm. Therefore, the above equation (3) can be expressed as shown in equation (4).

D _L = D _P +150 (μm) (4) For example, when D _P = 200 μm, D _L = 350 μm
Becomes By the way, the width of the wiring 94 is miniaturized. However, the larger the width of the wiring 94 is, the easier it is to process, so that there are few defects and the substrate can be manufactured at low cost. The same applies to the minimum distance between the wiring 94 and the land 92. Wiring width 100μ which is currently mainstream
m, when the design rule of 100 μm wiring interval is applied,
The distance between the lands 92 must be at least 300 μm. Therefore, the minimum pad pitch in the case of D _P = 200 [mu] m described above becomes 650 .mu.m. If this dimension is to be set to 500 μm, the interval between the lands 92 is 150 μm, and this is possible only with a design rule of a wiring width of 50 μm and a wiring interval of 50 μm.

In the case of the above structure, as described above,
Variations in the height of the solder bumps increase. In order to suppress the variation in the height of the solder bump, the structure shown in FIG. 14 should be adopted. However, in this case, the peel strength of the land is reduced, and the land is easily peeled.

Further, in the above description, the pad structure of the BGA has been described. However, the same can be said for the pad structure of the mounting board on which the BGA is mounted. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to suppress variations in the height of solder bumps, and furthermore, the land has a high peel strength and a land-to-land space. It is an object of the present invention to provide a circuit board for mounting a semiconductor device capable of reducing the pitch of the semiconductor device.

[0019]

In order to solve the above-mentioned problems, the present invention provides a substrate, a land provided on the substrate and comprising a conductor having a surface including a major axis and a minor axis orthogonal to each other;
The lands are provided on the substrate, have the same shape as the lands, and a major axis is disposed orthogonal to the major axes of the lands, and have openings that expose central portions of the lands. And an insulating layer for holding the portion.

A plurality of lands are arranged on the substrate with their major axes parallel to each other, and wiring is arranged between the major axes of these adjacent lands. Furthermore, the present invention provides a substrate, a land provided on the substrate, having a surface having orthogonal axes having the same length, and a land made of a conductor having a plurality of protrusions around the substrate, and a land provided on the substrate. And an insulating layer that has the same shape as the surface of the land, has an opening exposing the surface, and presses the protrusion of the land. In addition, a plurality of lands are arranged on the substrate, and a pair of adjacent lands are opposed to each other in each adjacent land, and wiring is provided between the pair of adjacent lands.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a first embodiment of the present invention, and show a case where the present invention is applied to a circuit board. On one surface of the circuit board 1, a plurality of lands 11 having a shape in which the major axis and the minor axis are orthogonal to each other, for example, a rectangular parallelepiped are provided. These lands 11 are arranged with their long sides parallel to each other. For example, a wiring 11a is provided at one end of the lands 11 in the longitudinal direction. Between the long sides of the lands 11, wirings 11b connected to other lands (not shown) are arranged. The widths of these wirings 11a and 11b can be arbitrarily set as long as they can be manufactured by etching, and need not be the same.

One surface, for example, the surface of the circuit board 1 is covered with an insulating layer 13. The insulating layer 13 has a plurality of openings 12 exposing a part of the land 11. These openings 12 have a rectangular shape of the same size as the lands 11, and the long sides thereof are arranged in a direction orthogonal to the long sides of the lands 11. Therefore, the central portion of the land 11 and one surface of the substrate 11 located on both sides of the central portion are exposed from the opening 12.
The portion of the land 11 exposed from the opening 12 functions as the pad 4.

Specifically, assuming that the surface of the pad 4 is a square having a side length La of 200 μm, the length Lb of the long side of the land 11 is 350 μm according to the above equation (2).
Becomes Further, the length of the long side of the opening 12 is also 350 μm from the equation (2). In FIG. 1, the land 11 is 500
They are arranged in a grid at a pitch of μm. The shortest distance Lc between the lands 11 is 300 μm in the x direction and 150 μm in the y direction in FIG. The width of the wiring 11b is set to 10
In the case of 0 μm, the shortest distance Ld between the wiring 11b and the land 11 is 100 μm.

As described above, according to this embodiment, the pitch between the lands can be narrowed as compared with the conventional case, and the wiring width and the wiring interval can be doubled as compared with the conventional case. it can. Therefore, it can be easily manufactured by etching, and a short circuit due to an etching residue can be prevented.

Both ends of the land 11 in the longitudinal direction are covered with the insulating layer 3. Therefore, land 11
The peel strength of the land 11 can be prevented. Further, the area of the pad 4 depends on the processing accuracy of the land 11 in the x direction, and depends on the processing accuracy of the opening 12 in the y direction. Therefore, the variation ΔS of the area of the pad 4 is expressed by the equation (5).

ΔS = D (ΔD ₁ + ΔD ₂ ) (5) When the expressions (5) and (2) are compared, ΔD ₁ <ΔD ₂ . Therefore, in this embodiment, the pad 4
Can be reduced. Therefore, when the solder bump is melted and fixed to the pad 4, variation in the height of the solder bump can be suppressed. still,
The solder bumps are attached to the top and side surfaces of the pad 4 as shown by the broken lines in FIG.

FIG. 3 shows a second embodiment of the present invention, and the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals. In this embodiment, an oblong (elliptical) land 31 is provided on a circuit board, and an oblong opening 3 is formed in an insulating layer 3.
2 are provided. The land 31 and the opening 32 are disposed such that their long axes are orthogonal to each other.

In this embodiment, the land 31 and the opening 3
When the lengths of the major axis and the minor axis are the same as those of the first embodiment, the area of the pad 4 can be smaller than that of the first embodiment. Therefore, when the solder bump 5 is melted and fixed to the pad 4, the height of the solder bump can be increased.

FIG. 4 shows a third embodiment of the present invention, and the same parts as those in FIG. 1 and FIG. In this embodiment, a circular land 41 is provided on the circuit board, and a circular opening 42 is provided in the insulating layer 3. The land 41 is exposed from the opening 42. The circular land 41 is provided with protrusions 43 in a plurality of directions. These projections 43 extend in a direction of 45 degrees with respect to the wiring 11b. The tip of each projection 43 is covered with the insulating layer 3. Therefore, the peel strength of the land 41 is ensured by the tip of the projection 43. Land 41
The length Le from the center of the projection to the tip of the projection 43 is (6)
Given by the expression.

Le = (Do−D _L ) / 2 + Δx (6) where Do is the diameter of the opening 42, D _L is the diameter of the land 41, and Δx is the deviation between the center of the opening 42 and the land 41. . When D _L = 200 μm, Do =
It becomes 350 μm. When Δx = 50 μm,
Le = 225 μm. In this case, the minimum distance between the protrusions 43 is as follows.

Since the minimum distance between the projections 43 is 500-225 × 2 ^1/2 = 180 μm as described above, in this embodiment, compared to the first and second embodiments, the wiring 11 b
And the distance between the wiring 11b and the tip of the protrusion 43 need to be reduced. In this case, the width of the wiring 11b and the wiring 11b
And the width of the tip of the projection 43 may be, for example, 60 μm. In the prior art, each of these widths is 50
μm was required. Therefore, as compared with the prior art, this embodiment is easier to manufacture.

In the third embodiment, the land is circular. However, the present invention is not limited to this. For example, the land may be square, for example, in which axes perpendicular to each other have the same length, and protrusions are formed on each side of the square. May be.

FIG. 5 shows a fourth embodiment of the present invention. The shapes of the land and the opening are the same as in the first embodiment. Therefore, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals.

On the circuit board 1, a plurality of lands 11 are arranged at a predetermined pitch. The wirings 11a connected to the lands 11 are arranged between the adjacent openings 12. In the figure, the arranging directions of the lands and the openings in the range surrounded by the dashed lines 51 and 52 are 90
Has been rotated degrees. With such an arrangement,
Wiring can be easily arranged between lands.

When the circuit board 1 is applied to a BGA package, as shown in FIG. 6, a solder ball 61 is placed on each land 11 to form a solder bump. For electrical connection between the IC chip 62 disposed on the other surface of the circuit board 1 and each land, for example, a through hole 63 is formed on the circuit board 11 corresponding to the wiring of each land. The wiring and the electrodes of the IC chip are connected via the conductor plating 64 of FIG. Reference numeral 65 denotes a resin that covers the IC chip 62.

Further, when the circuit board 1 is applied to a mounting board of a BGA package, the solder bumps provided on the package are aligned with each land 11, and the solder bumps are melted to mount the BGA.

FIG. 7 shows a modification of FIG.
In the configuration shown in FIG. 5, the lands are arranged in a full matrix. On the other hand, in the configuration shown in FIG. 6, a plurality of lands located at the center are removed from the configuration shown in FIG.
With such a configuration, the present invention can be applied to a BGA other than a full matrix. It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made.

[0038]

As described above, according to the present invention, the variation in the height of the solder bumps can be suppressed,
In addition, it is possible to provide a circuit board for mounting a semiconductor device, in which the peel strength of the lands is high and the pitch between the lands can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line 2-2 in FIG. 1;

FIG. 3 is a plan view showing a second embodiment of the present invention.

FIG. 4 is a plan view showing a third embodiment of the present invention.

FIG. 5 is a plan view showing a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing a case where FIG. 5 is applied to a BGA mounting board;

FIG. 7 is a plan view showing a modification of FIG. 5;

FIG. 8 is a plan view showing the back surface of the BGA package.

FIG. 9 is a sectional view taken along line 9-9 in FIG. 8;

FIG. 10 is a sectional view showing a step of forming a solder bump.

FIG. 11 is a sectional view showing a step following FIG. 10;

FIG. 12 is a sectional view showing a step following FIG. 11;

FIG. 13 is a sectional view showing a state in which the BGA package is mounted on a mounting board.

FIG. 14 is a plan view showing the structure of a conventional pad.

FIG. 15 is a sectional view taken along the line 15-15 in FIG. 14;

FIG. 16 is a plan view showing another example of the structure of a conventional pad.

FIG. 17 is a sectional view taken along the line 17-17 in FIG. 16;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Circuit board, 11, 31, 41 ... Land, 12, 32, 42 ... Opening, 11a, 11b ... Wiring, 43 ... Projection, Ball 61 ... Solder, 62 ... IC chip, 63 ... Through hole.

Claims (10)

[Claims] A land provided on the substrate and having a surface including an orthogonal major axis and a minor axis; and a land provided on the substrate and having the same shape as the land and having a major axis. And an insulating layer disposed perpendicular to the major axis of the land, having an opening exposing a central part of the land, and pressing both ends in the major axis direction of the land. Mounting substrate. 2. The substrate for mounting a semiconductor device according to claim 1, wherein the land has a wiring in a part thereof. 3. The land according to claim 1, wherein a plurality of the lands are arranged on the substrate such that their major axes are parallel to each other, and the wiring is arranged between the major axes of the adjacent lands. 3. The substrate for mounting a semiconductor device according to item 2. 4. The semiconductor device mounting substrate according to claim 3, wherein said lands are rectangular or oval. 5. A substrate, a land provided on the substrate, having a surface having orthogonal axes having the same length, and a land made of a conductor having a plurality of protrusions around the substrate; and a land provided on the substrate; With the same shape as the surface of the land,
A substrate for mounting a semiconductor device, comprising: an opening that exposes the surface; and an insulating layer that presses the protrusion of the land. 6. The substrate for mounting a semiconductor device according to claim 5, wherein one of the protrusions is connected to a wiring. 7. A plurality of lands are arranged on the substrate, and each adjacent land has a pair of adjacent protrusions opposed to each other, and the wiring is arranged between the pair of adjacent protrusions. 6. The substrate for mounting a semiconductor device according to claim 5, wherein: 8. The semiconductor device mounting substrate according to claim 7, wherein said lands are circular or square. 9. The substrate for mounting a semiconductor device according to claim 1, wherein the substrate is a substrate on which a ball grid array is arranged. 10. The substrate for mounting a semiconductor device according to claim 1, wherein the substrate is a mounting substrate on which a ball grid array package is mounted.