JPH10209295A - Method for manufacturing semiconductor device having triple well - Google Patents

Abstract

[PROBLEMS] To manufacture a semiconductor device having a triple well and form a triple well (Well) with two masks at the time of forming a transistor of a memory device, thereby simplifying the process and stabilizing the process. It is intended to have the following characteristics. SOLUTION: After forming an element isolation mask on a silicon substrate 1, an N-type impurity is ion-implanted into the substrate using an N-well mask, the N-well mask is removed, and then a thermal oxidation step is performed. A field oxide film 7 is formed, and the N-type impurity is diffused into the substrate to form an N-well 8. That is, the N-well is formed without separately performing the drive-in process for forming the N-well.
After the P-well mask 18 is formed, a P-type impurity is implanted into the substrate at different concentrations and ion implantation energies, and the P-well and the N-
A triple well in which a P-well is provided inside the well region is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to forming a transistor of a memory device, forming a triple well by using two masks to simplify the process and have a stabilized characteristic. The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated, the need for a semiconductor device that operates separately from the potential of a semiconductor substrate has emerged. Triple wells with other types of wells were required.

[0003] Such a triple well utilizes an ion implanter having high energy. On the other hand, when a triple well is formed, all N-wells and P-wells have reverse well properties,
It has been difficult to stabilize the PMOS characteristics formed in the N-well. In addition, the diffused triple well (Diffused Tripl
e well) process is complicated because a drive-in process is required for both the N-well and the P-well.
Profile control of P-well (hereinafter referred to as R-well) formed inside the well region
Is not easy.

Further, conventionally, three masks are used to form a triple well. That is, there is a trouble that a separate mask is used to form the P-well inside the N-well.

[0005]

According to the present invention, to solve the above-mentioned problems, a separate drive-in process is not performed when forming an N-well, and a high-temperature oxidation process is performed when forming a field oxide film. It is an object of the present invention to provide a triple well forming method that simplifies a process so that an N-type impurity drives into a substrate.

Further, the present invention provides a triple well, ie, a triple well in which P-well, N-well and R-well are sequentially implanted with an appropriate doping concentration and ion implantation energy so as to have a doping profile having the most optimal characteristics. Another object is to provide a forming method.

[0007]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a triple well, comprising: forming an element isolation mask on a P-type silicon substrate; Forming an N-well mask, and implanting an N-type impurity into the exposed silicon substrate to form an N-well implant region;
After removing the N-well mask, the silicon substrate in the field region is oxidized by a thermal oxidation process to form a field oxide film, and N-type impurities in the N-well implant region are driven into the substrate and diffused. Forming an N-well; forming a P-well mask on the silicon substrate including the device isolation mask; and forming a P-well mask on the exposed silicon substrate and the N-well region.
The method may further include the step of implanting ions while changing the concentration of the type impurity and the ion implantation energy to form an independent P-well inside the P-well and the N-well.

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of: forming an element isolation mask on a P-type silicon substrate; and forming an N-well mask on the element isolation mask. Forming an N-well implant region by implanting N-type impurities into the exposed silicon substrate, forming a P-channel stop implant region by ion-implanting P-type impurities, and removing the N-well mask. Forming a field oxide film by oxidizing a silicon substrate in a field region by a thermal oxidation process, and forming an N-well diffused by driving the N-well ions into the substrate;
Forming a P-well mask on the silicon substrate, forming a P-well region and an R-well region by ion-implanting a P-type impurity into the exposed silicon substrate and the N-well region; Implanting into the substrate exposed with the P-type impurity to form an internal well implant region at a depth lower than the P-well region and the R-well region; and implanting into the substrate exposed with the P-type impurity, Forming an N-channel deep implant region at a depth lower than the region, and forming an N-channel threshold implant region at a depth lower than the N-channel deep implant by implanting into the substrate exposed with P-type impurities. It is characterized by including.

In the present invention, after an element isolation mask is formed on a silicon substrate, an N-type impurity is ion-implanted into the silicon substrate using an N-well mask, and then a field oxide film is grown to form a separate N-well. An advantage is that the drive-in process has unnecessary but diffused N-well characteristics. Furthermore, the NMOS has the advantage of having the characteristics of the high energy well forming process by simultaneously ion implanting the P-well and the R-well with high energy using the P-well mask.

That is, three types of wells by the high energy ion implantation method, ie, N-well, P-well, and R-well
The N-well process is performed before the field oxidation while forming the wells on the two masks at the same time so that the N-well has a diffused well characteristic after the field oxidation process. A P-well and an R-well are simultaneously formed using a mask.

At this time, since there is no separate drive-in step, the P-well and the R-well have high energy well characteristics.
The well has diffused well properties; P-well, R
The wells can be made to have high energy well properties;

The advantages, such as the objects and features set forth above, will become more apparent through the following detailed description, taken in conjunction with the accompanying drawings.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIGS. 1 to 4 are cross-sectional views showing a step of forming a triple well in a semiconductor substrate according to the present invention.

FIG. 1 shows that a pad oxide film (2) and a nitride film (3) are polymerized on a P-type silicon substrate (1), and a nitride film (3) in a field region is formed by a lithography process using a mask and an etching process. FIG. 9 is a cross-sectional view showing a device isolation mask (30) manufactured by removing the pad oxide film (2).

FIG. 2 shows that after a photosensitive film is applied as a whole, N
-Exposure is performed using a well forming mask, and the entire photosensitive film is developed to form an N-well mask having a photosensitive film pattern (4).
Is formed to penetrate the element isolation mask (30), and the N-well mask (4) implants an N-type impurity into the silicon substrate (1) with ion implantation energy that is not penetrated.
Forming a well implant region (5) and subsequently applying P with energy that cannot penetrate the device isolation mask (30);
FIG. 4 is a cross-sectional view in which a P-channel stop implant region (6) is formed by ion-implanting a silicon substrate (1) with an exposed type impurity, and conditions for forming the N-well implant region (5) are, for example, phosphorus. (P31) is 1
The implantation is performed at a dose of -2E13 cm ^-2 and an energy of 1.5-2 MeV. Then, when forming the P channel stop implant region (6), phosphorus is added to 4.5-5.5E.
The implantation is performed at a dose of 12 cm ^-2 and an energy of 200 to 400 KeV.

FIG. 3 illustrates a method of manufacturing a field oxide film after removing the photosensitive film used for the N-well mask (4) at a temperature of, for example, 1000-1200.degree.
Field oxidation film (7) by performing thermal oxidation process for about 50 minutes
To form In the step of forming the field oxide film (7), the N-type impurities in the N-well implant region (5) are diffused into the substrate to have a diffused N-well (8) profile. After the device isolation mask (30) is removed, after the above-described process, a photosensitive film is entirely coated and exposed using a P-well forming mask, and then an exposed photosensitive film is formed. - 2-3E13cm P-type impurities into the silicon substrate exposed after forming the removed photoresist areas which is scheduled to the well region P- well mask (18) (1), for example, boron (B11) ^-2
The P-well implant region (9) and the R-well implant region (10) are simultaneously formed by ion implantation at a dose of 400 to 500 KeV energy.

Then, boron is implanted at a dose of 1-2E13 cm.sup.- ^{2 at a} dose of 200-300 KeV to form an internal well implant region (11).
An N-channel deep implant region (1) was implanted with a dose of 2 cm ^-2 and an energy of 80-200 KeV.
FIG. 3C is a cross-sectional view showing the formation of the N-channel threshold implant region (14) by implanting boron with a dose of 1.5-2E12 cm ^-2 and an energy of 20-30 KeV.

The inner well implant area (11)
Is formed to improve the well characteristics between the P-well and the N-channel field stop implant region (14).

For reference, after the P impurity is implanted for forming the P-well, the P-well is not formed in the drive-in step but the P-type implant region or the like is formed while reducing the impurity concentration and the ion implantation energy. Is N-
It is formed in the well (8) and the substrate (1). As a result, it has a high energy implant well characteristic without a diffused P-well profile. On the other hand, the drive-in process cannot be performed in the subsequent process, and the profile of the N-well (8) is maintained as it is.

FIG. 4 is a sectional view showing a silicon substrate (1) having a triple well formed by removing the P-well mask (18).
The well 16 has high energy implant well characteristics, whereas the N-well 8 has well characteristics diffused through the field oxide film 7 forming process.

For reference, after removing the P-well mask (18), an annealing step is performed at 900-1000 ° C. for 20-40 minutes to perform ion implantation with the P-well (15) and the R-well (16). Defects and the like generated are removed, and boron is implanted with a blanket threshold implant at a dose of 1 to 2E12 cm ^-2 and an energy of 20 to 30 KeV to improve the doping profile.

On the other hand, when the N-channel threshold implant and the overall threshold implant are not advanced in separate processes and boron is implanted at a dose of 2 to 4E13 cm- ² at 20-30 KeV energy, the same characteristics can be obtained. As a result, the characteristics of PMOS and NMOS could be adjusted at once.

When the P-well implant process is performed without separately performing the P-well implant and the inner well implant, the dose of boron is 2 to 4 times.
The same characteristics can be obtained by implanting with E13 cm ⁻² and 200-400 KeV energy, and the process can be simplified.

FIG. 5 shows the doping profile expected with the depth of the silicon substrate after the triple well is formed according to the present invention.
-Represents the profiles of the well implant area (10), the internal well implant area (11), the N-channel deep implant area (13) and the N-channel threshold implant area (14).

FIG. 6 shows that the P-well implant and the inner well implant are not separated according to another embodiment of the present invention, and the dose of boron is 2 to 4E13 cm ^-2 and 200 to 400 KeV. FIG. 4 shows a doping profile implanted with energy, and shows a profile of an R-well implant region (10), an N-channel deep implant region (13), and an N-channel threshold implant region (14) from inside the silicon substrate.

[0027]

According to the present invention, when ion implantation with high energy is performed in the process of forming a triple well with a mask at the same time, a field oxidation process is performed after the N-well implant to improve the PMOS characteristics of the N-well. Get the drive-in effect at the same time.

Furthermore, in the entire process, three types of wells, namely, N-well, P-well, and R-well can obtain a doping profile having the most appropriate characteristics, thereby stabilizing overall transistor characteristics and improving yield. The rate can be expected to improve.

The preferred embodiments of the present invention have been disclosed for the purpose of illustration, and those skilled in the art can make various modifications, changes, additions, etc. within the spirit and scope of the present invention. Such modifications, changes and the like should be considered as belonging to the following claims.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a step of forming a triple well in a silicon substrate according to the present invention.

FIG. 2 is a cross-sectional view illustrating a step of forming a triple well in a silicon substrate according to the present invention.

FIG. 3 is a cross-sectional view illustrating a step of forming a triple well in a silicon substrate according to the present invention.

FIG. 4 is a cross-sectional view illustrating a step of forming a triple well in a silicon substrate according to the present invention.

FIG. 5 illustrates an expected doping profile with depth of a silicon substrate after forming a triple well according to the present invention.

FIG. 6 illustrates a doping profile expected according to the depth of a silicon substrate in which a well implant process is performed by adjusting a phosphorus concentration and an ion implantation energy without separately performing a P-well implant process and an inner well implant process. It is a thing.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 pad oxide film 3 nitride film 4 N-well mask 5 N-well implant region 6 P-type channel stop implant region 7 field oxide film 8 N-well 9 P-well implant region 10 R-well implant region 11 inside Well implant area 13 N-channel deep implant area 14 N-channel threshold implant area 15 N-well 16 R-well 18 P-well mask 30 Element isolation mask

Claims (14)

[Claims] 1. A method of manufacturing a semiconductor device having a triple well, comprising: forming an element isolation mask on a P-type silicon substrate; forming an N-well mask on the element isolation mask; Implanting the exposed silicon substrate to form an N-well implant region; removing the N-well mask, oxidizing a silicon substrate in a field region by a thermal oxidation process to form a field oxide film; Forming an N-well in which an N-type impurity present in the well implant region is driven into the substrate and diffused; forming a P-well mask on a silicon substrate including the device isolation mask; Several times while changing the concentration of the P-type impurity and the ion implantation energy in the silicon substrate and the N-well region. A method of manufacturing a semiconductor device having a triple well, comprising the steps of implanting ions to form an independent P-well inside a P-well and the N-well. 2. The method according to claim 1, wherein the P-well formed inside the P-well and the N-well is firstly implanted with a P-type impurity at a dose of 2-3E13 cm ^-2 and 400-500 KeV energy. Impurities are 1-2E13cm ^-2 dose and 200-30
A second implantation at an energy of 0 KeV; a P-type impurity at a dose of 4-5E12 cm- ² ;
2. The method according to claim 1, wherein the third implantation is performed at an energy of 0 KeV. 3. A method of manufacturing a semiconductor device, comprising: forming an element isolation mask on a P-type silicon substrate; forming an N-well mask on the element isolation mask; and exposing an N-type impurity to the silicon substrate. Forming an N-well implant region by ion implantation, forming a P-channel impurity implant region by ion-implanting a P-type impurity, and removing the N-well mask. Oxidizing the substrate to form a field oxide film, driving the N-well ions into the substrate to form a diffused N-well; and forming a P-well mask on the silicon substrate. P-type impurities are ion-implanted into the exposed silicon substrate and the N-well region, and the P-well region Forming a well region; implanting into the substrate exposed with the P-type impurity to form an internal well implant region at a depth lower than the P-well region and the R-well region; Forming an N-channel deep implant region at a depth lower than the inner well implant region, and implanting the N-channel deep implant region at a depth lower than the N-channel deep implant. A method of manufacturing a semiconductor device having a triple well including a step of forming a channel threshold implant region. 4. The method according to claim 1, wherein the device isolation mask has a laminated structure of a pad oxide film and a nitride film. 5. The condition for forming the N-well implant region is as follows: phosphorous is added at a dose of 1 to 2E13 cm ^{−2 and a} dose of 1.5.
4. The method for manufacturing a semiconductor device having a triple well according to claim 1, wherein the implantation is performed at an energy of -2 MeV. 6. The fabrication of a semiconductor device having a triple well according to claim 3, wherein the conditions for forming the P-channel stop implant region include implanting at a dose of 4 to 6E12 cm ⁻² and an energy of 200 to 300 KeV. Method. 7. The conditions for forming the internal well implant region are as follows: boron is 4 to 5E12 cm ⁻² dose;
4. The method of claim 3, wherein the implantation is performed at 0-300 KeV energy. 8. The semiconductor having a triple well according to claim 3, wherein the condition for forming the N-channel deep implant region is that boron is implanted at a dose of 4 to 5E12 cm ⁻² and an energy of 80 to 200 KeV. Element manufacturing method. 9. The condition for forming the N-channel threshold implant region is that boron is 1.0 to 2E1.
4. The method of claim 3, wherein the implantation is performed at a dose of ² cm.sup.- ² and an energy of 20-30 KeV. 10. After forming the N-channel threshold implant region, forming the N-channel threshold implant region at 900-1000 ° C.
4. The method according to claim 3, wherein an annealing process is performed for up to 40 minutes to remove defects generated at the time of implanting. 11. After the N-channel threshold implant is implanted, the P-well mask is removed, and boron is applied to the entire surface using a threshold implant.
4. The method of claim 3, wherein the implantation is performed at a dose of 0E12 cm ^<-2 > and an energy of 20-30 KeV. 12. A method of manufacturing a semiconductor device, comprising: forming an element isolation film mask on a P-type silicon substrate; forming an N-well mask on the element isolation mask; Implanting into the substrate to form an N-well implant region; ion-implanting P-type impurities to form a P-channel stop implant region; removing the N-well mask and performing a thermal oxidation process. Oxidizing a silicon substrate in the field region to form a field oxide film, and driving an N-type impurity present in the N-well implant region into the substrate to form an diffused N-well; Forming a P-well mask on the exposed silicon substrate and the N-well region. Ion-implanting a material to form a P-well region inside the P-well region and the N-well; implanting the N-channel into the substrate exposed by the P-type impurity to a depth lower than the P-well region; Forming a deep implant region; removing the P-well mask and implanting the P-type impurity into a substrate exposed to a P-type impurity to form an entire threshold implant region at a depth lower than that of the N-channel deep implant region. A method for manufacturing a semiconductor device having a triple well. 13. The method according to claim 13, wherein said P-type impurities are ion-implanted.
When forming the P-well inside the well and the N-well, the dose of boron is ² to 4.0E13 cm ^-2 and 200 to 40.
2. The method according to claim 1, wherein the implantation is performed at 0 KeV energy.
3. The method for manufacturing a semiconductor device according to item 2. 14. The method according to claim 12, wherein the condition for forming the threshold implant region is that boron having a dose of 2 to 4E12 cm ⁻² is implanted at a energy of 20 to 30 KeV.