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JPH10199882A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH10199882A
JPH10199882A JP354297A JP354297A JPH10199882A JP H10199882 A JPH10199882 A JP H10199882A JP 354297 A JP354297 A JP 354297A JP 354297 A JP354297 A JP 354297A JP H10199882 A JPH10199882 A JP H10199882A
Authority
JP
Japan
Prior art keywords
wiring
dummy
heat
film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP354297A
Other languages
Japanese (ja)
Inventor
Shigehiko Tsukamoto
滋彦 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP354297A priority Critical patent/JPH10199882A/en
Publication of JPH10199882A publication Critical patent/JPH10199882A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To avoid deteriorating the characteristics of a semiconductor device, due to the heat by effectively radiating the heat stored in layer insulation films of a multilayer wiring structure. SOLUTION: Dummy wiring films 3A, 5A, 7A, 9A are provided to form wiring layers of a multilayer structure and are interconnected through dummy through-holes 4b, 6b, 8b. The heat generated in a semiconductor substrate 1 is transmitted through the dummy wiring films and dummy through-holes to an upper wiring layer, thereby efficiently radiating from the surface of a multilayer structure. A heat sink 12 is provided on the topmost layer, and the dummy wiring 9A is connected through the dummy through-holes 19b to this heat sink to effectively radiate heat. When a low-thermal conductivity and low-dielectric const. layer insulation film is used for each wiring layer for the purpose of realizing a highly integrated semiconductor device, the temp. rise of the device is suppressed to avoid causing troubles of the device, due to heat.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に微細な多層配線構造を有する半導体装置における放
熱特性を改善した半導体装置に関する。
The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having improved heat radiation characteristics in a semiconductor device having a fine multilayer wiring structure.

【0002】[0002]

【従来の技術】近年、半導体デバイスの高集積化に伴っ
て多層配線化が進められている。この多層配線構造で
は、多層に積層配置された配線膜を層間絶縁膜によって
相互に絶縁する構成がとられるため、この層間絶縁膜の
低熱伝導性によって半導体素子で発生した熱がこれら層
間絶縁膜に蓄積され、これがデバイスの誤動作の原因に
なったり、特性が低下されるという問題となっている。
特に、最近では多層構造の配線間容量の増加を抑えるた
めに、層間絶縁膜として誘電率の低い膜が使用されてき
ているが、このような誘電率の低い膜は熱伝導率が低い
ために、熱の放出効率が悪く、熱が溜りやすいものとな
っている。この場合、配線層上にヒートシンクを配設し
て放熱効果を高めることが考えられるが、多層配線構造
の層間絶縁膜内部での熱伝導性を高めることはできず、
特に下層の配線層における熱の蓄積が著しいものとな
り、結果として有効な解決策とはなり得ない。
2. Description of the Related Art In recent years, multilayer wiring has been promoted along with the high integration of semiconductor devices. In this multi-layer wiring structure, since the wiring films arranged in multiple layers are insulated from each other by an interlayer insulating film, the heat generated in the semiconductor element due to the low thermal conductivity of the interlayer insulating film is applied to these interlayer insulating films. It accumulates, and this causes a malfunction of the device and causes a problem that characteristics are deteriorated.
In particular, recently, a film having a low dielectric constant has been used as an interlayer insulating film in order to suppress an increase in capacitance between wirings in a multilayer structure. However, such a film having a low dielectric constant has a low thermal conductivity. However, the heat release efficiency is poor, and the heat tends to accumulate. In this case, it is conceivable to arrange a heat sink on the wiring layer to enhance the heat radiation effect, but it is not possible to increase the thermal conductivity inside the interlayer insulating film of the multilayer wiring structure,
Particularly, heat accumulation in the lower wiring layer becomes significant, and as a result, it cannot be an effective solution.

【0003】一方、特開平5−267295号公報に
は、多層配線構造にダミー配線膜を設けた構造が提案さ
れている。このダミー配線膜は多層配線構造の平坦化を
目的としたものであるが、ダミー配線膜を形成した部分
が低熱伝導性の層間絶縁膜から熱伝導性の高い金属に置
き替えられることで、層間絶縁膜での熱伝導性を改善
し、半導体装置全体としての放熱性を改善する上では有
効となる。しかしながら、このダミー配線膜の配置面積
にも限界があるため、期待したほどの改善効果を得るこ
とは困難である。
On the other hand, Japanese Patent Laying-Open No. 5-267295 proposes a structure in which a dummy wiring film is provided in a multilayer wiring structure. The purpose of this dummy wiring film is to flatten the multilayer wiring structure. However, the portion where the dummy wiring film is formed is replaced with a metal having a high thermal conductivity from an interlayer insulating film having a low thermal conductivity. This is effective in improving the thermal conductivity of the insulating film and improving the heat dissipation of the semiconductor device as a whole. However, since there is a limit in the arrangement area of the dummy wiring film, it is difficult to obtain an expected improvement effect.

【0004】[0004]

【発明が解決しようとする課題】このように、従来の多
層配線構造では、配線間を絶縁するための層間絶縁膜の
低熱伝導性によって半導体素子で発生した熱の放熱性が
低く、半導体デバイスの特性を劣化させるという問題が
ある。また、ダミー配線膜を有する半導体装置では、ダ
ミー配線膜によって層間絶縁膜の体積が低減されるた
め、放熱特性を改善する上では有利ではあるが、根本的
な解決策とはならない。
As described above, in the conventional multilayer wiring structure, the heat dissipation of the heat generated in the semiconductor element is low due to the low thermal conductivity of the interlayer insulating film for insulating between the wirings. There is a problem of deteriorating characteristics. In a semiconductor device having a dummy wiring film, the volume of the interlayer insulating film is reduced by the dummy wiring film, which is advantageous in improving heat radiation characteristics, but is not a fundamental solution.

【0005】本発明の目的は、多層配線構造の層間絶縁
膜に蓄積される熱を有効に放熱して半導体デバイスの熱
による特性劣化を防止することを可能とした半導体装置
を提供することにある。
An object of the present invention is to provide a semiconductor device capable of effectively radiating heat accumulated in an interlayer insulating film of a multilayer wiring structure and preventing deterioration of characteristics due to heat of a semiconductor device. .

【0006】[0006]

【課題を解決するための手段】本発明は、複数の配線層
が積層配置された多層配線構造を有する半導体装置にお
いて、前記配線層にはそれぞれ配線膜と共にダミーの配
線膜が形成され、これらダミーの配線膜が前記各配線層
を絶縁するための各層間絶縁膜に設けられたダミーのス
ルーホールを介して上下の配線層間で相互に接続されて
いることを特徴とする。また、本発明は、最上層の配線
層上にヒートシンクが設けられ、前記最上層のダミー配
線膜がダミースルーホールを介して前記ヒートシンクに
接続されることが好ましい。本発明においては、配線膜
及びダミー配線膜は熱伝導率の高い金属で形成され、層
間絶縁膜は低誘電率の絶縁材で形成される。
According to the present invention, in a semiconductor device having a multilayer wiring structure in which a plurality of wiring layers are stacked and arranged, a dummy wiring film is formed on each of the wiring layers together with a wiring film. Are interconnected between upper and lower wiring layers via dummy through holes provided in each interlayer insulating film for insulating each wiring layer. In the present invention, it is preferable that a heat sink is provided on an uppermost wiring layer, and the uppermost dummy wiring film is connected to the heat sink through a dummy through hole. In the present invention, the wiring film and the dummy wiring film are formed of a metal having a high thermal conductivity, and the interlayer insulating film is formed of an insulating material having a low dielectric constant.

【0007】[0007]

【発明の実施の形態】次に本発明について図面を参照し
て説明する。図1は本発明の第1の実施形態を示す断面
図であり、ここでは4層構造の多層配線構造に本発明を
適用した例を示している。半導体基板1には図外の素子
が形成されており、この半導体基板1上に下地絶縁膜2
が形成され、この下地絶縁膜2の上に第1配線金属膜3
が所要のパターンに形成されている。この第1配線金属
膜3としては、例えば10000Åの厚さのアルミニウ
ム合金が用いられる。そして、この第1配線金属膜3を
覆うように第1層間絶縁膜4が形成されている。この第
1層間絶縁膜4としては、例えば、フツ素含有酸化シリ
コン膜を10000Åの厚さに形成したものが用いられ
る。また、この第1層間絶縁膜4の所要箇所にはスルー
ホール4aが開設され、このスルーホール4aを含む前
記第1層間絶縁膜3上に第2配線金属膜5が形成され
る。以下、同様に、第2層間絶縁膜6、第3配線金属膜
7、第3層間絶縁膜8、第4配線金属膜9、第4層間絶
縁膜10が形成され、最上にパッシベーション膜11が
形成されて4層構造の多層配線構造が構成される。この
パッシベーション膜11としては、例えば酸化シリコン
膜を500Åの厚さに形成した構成とされる。なお、各
層の配線金属膜と層間絶縁膜はそれぞれ前記した材料の
ものが用いられる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a first embodiment of the present invention. Here, an example in which the present invention is applied to a multilayer wiring structure having a four-layer structure is shown. An element (not shown) is formed on the semiconductor substrate 1, and a base insulating film 2 is formed on the semiconductor substrate 1.
Is formed, and a first wiring metal film 3 is formed on the underlying insulating film 2.
Are formed in a required pattern. As the first wiring metal film 3, for example, an aluminum alloy having a thickness of 10000 ° is used. Then, a first interlayer insulating film 4 is formed so as to cover the first wiring metal film 3. As the first interlayer insulating film 4, for example, a film obtained by forming a fluorine-containing silicon oxide film to a thickness of 10,000 ° is used. A through hole 4a is formed at a required portion of the first interlayer insulating film 4, and a second wiring metal film 5 is formed on the first interlayer insulating film 3 including the through hole 4a. Hereinafter, similarly, the second interlayer insulating film 6, the third wiring metal film 7, the third interlayer insulating film 8, the fourth wiring metal film 9, and the fourth interlayer insulating film 10 are formed, and the passivation film 11 is formed at the top. Thus, a multilayer wiring structure having a four-layer structure is formed. The passivation film 11 has a configuration in which, for example, a silicon oxide film is formed to a thickness of 500 °. The wiring metal film and the interlayer insulating film of each layer are made of the materials described above.

【0008】ここで、前記第1ないし第4の各配線金属
膜3,5,7,9には、本来の配線金属膜が形成されて
いない領域にそれぞれダミー配線金属膜3A,5A,7
A,9Aが形成されている。これらのダミー配線金属膜
3A,5A,7A,9Aは、各配線金属膜3,5,7,
9と同一材料で同一厚さに形成されている。例えば、本
来の配線金属膜は、全面に金属材料を形成した後、これ
をフォトリソグラフィ技術でエッチングして形成してい
るが、その際にダミー配線金属膜を同時に形成すればよ
い。また、第1ないし第3の配線層の各層間絶縁膜4,
6,8には、各配線金属膜間における本来のスルーホー
ル4a,6a,8aとは別にダミースルーホール4b,
6b,8bが形成されており、このダミースルーホール
4b,6b,8bによって上下のダミー配線金属膜3
a,5a,7a,9aが相互に接続された構成とされて
いる。
Here, the first to fourth wiring metal films 3, 5, 7 and 9 are respectively provided with dummy wiring metal films 3A, 5A and 7 in regions where the original wiring metal film is not formed.
A and 9A are formed. These dummy wiring metal films 3A, 5A, 7A, 9A are made of respective wiring metal films 3, 5, 7,.
9 and the same thickness. For example, the original wiring metal film is formed by forming a metal material on the entire surface and then etching the metal material by photolithography technology. At this time, a dummy wiring metal film may be formed at the same time. Further, each of the interlayer insulating films 4 of the first to third wiring layers 4,
6 and 8, dummy through holes 4b, 4a, 6a, 8a are provided separately from the original through holes 4a, 6a, 8a between the wiring metal films.
6b, 8b are formed, and the upper and lower dummy wiring metal films 3 are formed by the dummy through holes 4b, 6b, 8b.
a, 5a, 7a, 9a are connected to each other.

【0009】したがって、この第1の実施形態の構成で
は、半導体基板1の素子で発生した熱は、第1の配線層
においては、配線金属膜3、層間絶縁膜4及びダミー配
線金属膜3Aにそれぞれ伝達される。層間絶縁膜4は、
熱伝導率の悪い低誘電率膜であるフツ素含有酸化シリコ
ン膜で構成されているため、熱が蓄積され易い状態であ
るが、配線金属膜3及びダミー配線金属膜3Aに伝達さ
れた熱は、それぞれスルーホール4a、ダミースルーホ
ール4bを介して上層(第2の配線層)の配線金属膜5
とダミー配線金属膜5Aにそれぞれ伝達される。これに
より、本来の配線金属膜のみが存在する場合よりも、ダ
ミー配線金属膜が設けられている分、上層への熱の伝達
効果を高めることができる。第2の配線層に伝達された
熱は、同様にして配線金属膜5、ダミー配線金属膜5A
からスルーホール6a、ダミースルーホール6bを介し
て第3の配線層に伝達され、さらに同様にして第4の配
線層に伝達される。このため、半導体基板1の熱は、配
線金属膜3,5,7,9及びダミー配線金属膜3A,5
A,7A,9Aを介して効率良く最上層の第4の配線層
まで伝達され、最上層面から放熱されることになる。こ
れらより、熱の溜まりやすい低誘電率の層間絶縁膜の多
層配線構造を有する半導体装置においても、高温による
半導体装置の特性劣化を防止することが可能となる。
Therefore, in the configuration of the first embodiment, the heat generated by the elements of the semiconductor substrate 1 is transmitted to the wiring metal film 3, the interlayer insulating film 4, and the dummy wiring metal film 3A in the first wiring layer. Each is transmitted. The interlayer insulating film 4
Since it is composed of a fluorine-containing silicon oxide film which is a low dielectric constant film having a low thermal conductivity, heat is easily accumulated. However, the heat transmitted to the wiring metal film 3 and the dummy wiring metal film 3A is low. Wiring metal film 5 in the upper layer (second wiring layer) via through hole 4a and dummy through hole 4b, respectively.
To the dummy wiring metal film 5A. Thereby, the effect of transferring heat to the upper layer can be enhanced by the provision of the dummy wiring metal film, as compared with the case where only the original wiring metal film exists. The heat transferred to the second wiring layer is similarly transferred to the wiring metal film 5, the dummy wiring metal film 5A.
Through the through hole 6a and the dummy through hole 6b to the third wiring layer, and further similarly to the fourth wiring layer. Therefore, the heat of the semiconductor substrate 1 is reduced by the wiring metal films 3, 5, 7, 9 and the dummy wiring metal films 3A, 5A.
The light is efficiently transmitted to the uppermost fourth wiring layer through A, 7A, and 9A, and is radiated from the uppermost layer surface. Thus, even in a semiconductor device having a multilayer wiring structure of a low dielectric constant interlayer insulating film in which heat easily accumulates, it is possible to prevent the characteristics of the semiconductor device from deteriorating due to high temperatures.

【0010】図2は本発明の第2の実施形態の断面図で
ある。この実施形態においても第1の実施形態と同様に
4層の多層配線構造に本発明を適用した例を示してお
り、半導体基板1上に下地絶縁膜2を形成し、その上に
第1ないし第4の配線層を形成している。なお、第1の
実施形態と等価な部分には同一符号を付しており、その
詳細な説明は省略している。この第2の実施形態では、
最上のパッシベーション層は形成されておらず、その代
わりに金属板で構成されたヒートシンク12が配置さ
れ、かつ第4配線層の層間絶縁膜10に形成されたダミ
ースルーホール10bによってこのヒートシンク12と
第4配線層のダミー配線金属膜9Aとが接続されてい
る。
FIG. 2 is a sectional view of a second embodiment of the present invention. This embodiment also shows an example in which the present invention is applied to a four-layer multi-layer wiring structure as in the first embodiment, in which a base insulating film 2 is formed on a semiconductor substrate 1 and first to A fourth wiring layer is formed. Note that the same reference numerals are given to portions equivalent to those in the first embodiment, and detailed description thereof is omitted. In this second embodiment,
The uppermost passivation layer is not formed. Instead, a heat sink 12 made of a metal plate is arranged, and the heat sink 12 and the second heat sink 12 are formed by a dummy through hole 10b formed in the interlayer insulating film 10 of the fourth wiring layer. The dummy wiring metal films 9A of the four wiring layers are connected.

【0011】この第2の実施形態においても、半導体基
板1の素子で発生した熱は、第1配線層から第4配線層
に向けて、各配線層の配線金属膜3,5,7,9とダミ
ー配線金属膜3A,5A,7A,9Aおよびスルーホー
ル4a,6a,8aとダミースルーホール4b,6b,
8bを介して順次伝達される。そして、最終的に第4配
線層まで伝達された熱のうち、配線金属膜9に伝達され
た熱は層間絶縁膜10を通してヒートシンク12に伝達
され、ダミー配線金属膜9Aに伝達された熱はダミース
ルーホール10bを介して直接的にヒートシンク12に
伝達され、それぞれヒートシンク12の全面から放熱さ
れる。これにより、各配線層の層間絶縁膜の熱伝導率が
低い場合でも、効率良く放熱を行うことが可能となる。
なお、この実施形態ではヒートシンク12からの放熱を
行うことで、第4配線層にまで伝達された熱を第1の実
施形態よりも高い効率で放熱することが可能となる。
Also in the second embodiment, the heat generated in the elements of the semiconductor substrate 1 is transferred from the first wiring layer to the fourth wiring layer by the wiring metal films 3, 5, 7, 9 of the respective wiring layers. And dummy wiring metal films 3A, 5A, 7A, 9A and through holes 4a, 6a, 8a and dummy through holes 4b, 6b,
8b. Then, of the heat finally transmitted to the fourth wiring layer, the heat transmitted to the wiring metal film 9 is transmitted to the heat sink 12 through the interlayer insulating film 10, and the heat transmitted to the dummy wiring metal film 9A is the dummy heat. The heat is directly transmitted to the heat sink 12 through the through hole 10b, and is radiated from the entire surface of the heat sink 12, respectively. This makes it possible to efficiently radiate heat even when the thermal conductivity of the interlayer insulating film of each wiring layer is low.
In this embodiment, by radiating the heat from the heat sink 12, it is possible to radiate the heat transmitted to the fourth wiring layer with higher efficiency than in the first embodiment.

【0012】なお、図3に示すように、前記第1の実施
形態においても、最上層のパッシベーション膜11の上
側にヒートシンク12を配置した構成としても、第4配
線層のダミー配線金属膜9Aまで伝達された熱がパッシ
ベーション膜11を介してヒートシンク12に伝達さ
れ、ここから放熱されることになる。これにより、図1
の構成に比較して放熱効果を高めることは可能である。
As shown in FIG. 3, even in the first embodiment, even if the heat sink 12 is arranged above the uppermost passivation film 11, the structure up to the dummy wiring metal film 9A in the fourth wiring layer can be obtained. The transmitted heat is transmitted to the heat sink 12 via the passivation film 11, and is radiated from here. As a result, FIG.
It is possible to enhance the heat radiation effect as compared with the configuration of the above.

【0013】[0013]

【発明の効果】以上説明したように本発明は、多層構造
の配線層のそれぞれにダミー配線膜を設け、各ダミー配
線膜をダミースルーホールを通して相互に接続している
ので、半導体装置で発生した熱をダミー配線膜及びダミ
ースルーホールを介して上層の配線層にまで伝達でき、
配線構造の表面から効率的に放熱することができる。ま
た、最上層にヒートシンクを設け、このヒートシンクに
ダミースルーホールを介してダミー配線を接続すること
で、放熱をより効果的に行うことができる。これによ
り、半導体装置の高集積化を目的として各配線層に熱伝
導率の低い低誘電率の層間絶縁膜を使用した場合にもデ
バイスの温度上昇を抑制することができ、熱による半導
体装置の故障を防止することができる効果がある。
As described above, according to the present invention, a dummy wiring film is provided in each of the wiring layers having a multilayer structure, and the respective dummy wiring films are connected to each other through dummy through holes. Heat can be transferred to the upper wiring layer via the dummy wiring film and dummy through hole,
Heat can be efficiently radiated from the surface of the wiring structure. Further, by providing a heat sink on the uppermost layer and connecting a dummy wiring to the heat sink through a dummy through hole, heat radiation can be more effectively performed. Thus, even when an interlayer insulating film having a low thermal conductivity and a low dielectric constant is used for each wiring layer for the purpose of high integration of the semiconductor device, the temperature rise of the device can be suppressed, and the semiconductor device due to heat can be suppressed. There is an effect that a failure can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.

【図2】本発明の第2の実施形態の断面図である。FIG. 2 is a cross-sectional view of a second embodiment of the present invention.

【図3】本発明の第1の実施形態の変形例を示す図であ
る。
FIG. 3 is a diagram showing a modification of the first embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 下地絶縁膜 3,5,7,9 配線金属膜 3A,5A,7A,9A ダミー配線金属膜 4,6,8,10 層間絶縁膜 4a,6a,8a スルーホール 4b,6b,8b,10b ダミースルーホール 11 パッシベーション膜 12 ヒートシンク DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Base insulating film 3,5,7,9 Wiring metal film 3A, 5A, 7A, 9A Dummy wiring metal film 4,6,8,10 Interlayer insulating film 4a, 6a, 8a Through hole 4b, 6b, 8b , 10b Dummy through hole 11 Passivation film 12 Heat sink

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数の配線層が積層配置された多層配線
構造を有する半導体装置において、前記配線層にはそれ
ぞれ配線膜と共にダミーの配線膜が形成され、これらダ
ミーの配線膜が前記各配線層を絶縁するための各層間絶
縁膜に設けられたダミーのスルーホールを介して上下の
配線層間で相互に接続されていることを特徴とする半導
体装置。
In a semiconductor device having a multilayer wiring structure in which a plurality of wiring layers are stacked and arranged, a dummy wiring film is formed on each of the wiring layers together with a wiring film, and these dummy wiring films are formed on the respective wiring layers. A semiconductor device which is interconnected between upper and lower wiring layers via dummy through holes provided in respective interlayer insulating films for insulating the same.
【請求項2】 最上層の配線層上にヒートシンクが設け
られ、前記最上層のダミー配線膜がダミースルーホール
を介して前記ヒートシンクに接続される請求項1の半導
体装置。
2. The semiconductor device according to claim 1, wherein a heat sink is provided on an uppermost wiring layer, and the uppermost dummy wiring film is connected to the heat sink via a dummy through hole.
【請求項3】 配線膜及びダミー配線膜は熱伝導率の高
い金属で形成され、層間絶縁膜は低誘電率の絶縁材で形
成される請求項1または2の半導体装置。
3. The semiconductor device according to claim 1, wherein the wiring film and the dummy wiring film are formed of a metal having a high thermal conductivity, and the interlayer insulating film is formed of an insulating material having a low dielectric constant.
JP354297A 1997-01-13 1997-01-13 Semiconductor device Pending JPH10199882A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP354297A JPH10199882A (en) 1997-01-13 1997-01-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP354297A JPH10199882A (en) 1997-01-13 1997-01-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH10199882A true JPH10199882A (en) 1998-07-31

Family

ID=11560311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP354297A Pending JPH10199882A (en) 1997-01-13 1997-01-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH10199882A (en)

Cited By (14)

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KR100347082B1 (en) * 1998-11-17 2002-08-03 닛본 덴기 가부시끼가이샤 Interconnect structure of semiconductor device
KR100351597B1 (en) * 2000-01-13 2002-09-05 미쓰비시덴키 가부시키가이샤 Semiconductor device
US6610592B1 (en) * 2000-04-24 2003-08-26 Taiwan Semiconductor Manufacturing Company Method for integrating low-K materials in semiconductor fabrication
US6642622B2 (en) 2002-02-28 2003-11-04 Kabushiki Kaisha Toshiba Semiconductor device with protective layer
US6768061B2 (en) * 2001-07-06 2004-07-27 Denso Corporation Multilayer circuit board
WO2006061871A1 (en) * 2004-12-06 2006-06-15 Fujitsu Limited Semiconductor device
US7112883B2 (en) 2004-09-10 2006-09-26 Kabushiki Kaisha Toshiba Semiconductor device with temperature control mechanism
KR100655427B1 (en) 2004-07-14 2006-12-08 삼성전자주식회사 Wiring structure that can be easily changed, designing and changing method of the wiring structure
JP2007235157A (en) * 2007-04-23 2007-09-13 Ricoh Co Ltd Semiconductor integrated circuit device and its manufacturing method
JP2007335855A (en) * 2006-05-18 2007-12-27 Nec Electronics Corp Wiring program, wiring method, wiring apparatus, and semiconductor device
US7446417B2 (en) 2002-08-09 2008-11-04 Ricoh Company, Ltd. Semiconductor integrated circuit device and fabrication method thereof
US7605085B2 (en) 2003-08-12 2009-10-20 Renesas Technology Corp. Method of manufacturing interconnecting structure with vias
US7804357B2 (en) 2005-06-08 2010-09-28 Fujitsu Limited Distributed amplifier
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100347082B1 (en) * 1998-11-17 2002-08-03 닛본 덴기 가부시끼가이샤 Interconnect structure of semiconductor device
KR100351597B1 (en) * 2000-01-13 2002-09-05 미쓰비시덴키 가부시키가이샤 Semiconductor device
US6717267B1 (en) 2000-01-13 2004-04-06 Renesas Technology Corp. Semiconductor device having multilayer interconnection structure
US6956289B2 (en) 2000-01-13 2005-10-18 Renesas Technology Corporation Semiconductor device
US6610592B1 (en) * 2000-04-24 2003-08-26 Taiwan Semiconductor Manufacturing Company Method for integrating low-K materials in semiconductor fabrication
US7328505B2 (en) 2001-07-06 2008-02-12 Denso Corporation Method for manufacturing multilayer circuit board
US6768061B2 (en) * 2001-07-06 2004-07-27 Denso Corporation Multilayer circuit board
US6642622B2 (en) 2002-02-28 2003-11-04 Kabushiki Kaisha Toshiba Semiconductor device with protective layer
US7446417B2 (en) 2002-08-09 2008-11-04 Ricoh Company, Ltd. Semiconductor integrated circuit device and fabrication method thereof
US7930658B2 (en) 2002-08-09 2011-04-19 Ricoh Company, Ltd. Semiconductor integrated circuit device and fabrication method thereof
US7605085B2 (en) 2003-08-12 2009-10-20 Renesas Technology Corp. Method of manufacturing interconnecting structure with vias
KR100655427B1 (en) 2004-07-14 2006-12-08 삼성전자주식회사 Wiring structure that can be easily changed, designing and changing method of the wiring structure
US7112883B2 (en) 2004-09-10 2006-09-26 Kabushiki Kaisha Toshiba Semiconductor device with temperature control mechanism
CN100383958C (en) * 2004-09-10 2008-04-23 株式会社东芝 Semiconductor device
JPWO2006061871A1 (en) * 2004-12-06 2008-06-05 富士通株式会社 Semiconductor device
WO2006061871A1 (en) * 2004-12-06 2006-06-15 Fujitsu Limited Semiconductor device
US7804357B2 (en) 2005-06-08 2010-09-28 Fujitsu Limited Distributed amplifier
JP2007335855A (en) * 2006-05-18 2007-12-27 Nec Electronics Corp Wiring program, wiring method, wiring apparatus, and semiconductor device
JP2007235157A (en) * 2007-04-23 2007-09-13 Ricoh Co Ltd Semiconductor integrated circuit device and its manufacturing method
US9059269B2 (en) 2013-01-10 2015-06-16 International Business Machines Corporation Silicon-on-insulator heat sink
US9530711B2 (en) 2013-01-10 2016-12-27 Globalfoundries Inc. Silicon-on-insulator heat sink

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