JPH10197603A - Semiconductor integrated circuit and inspection method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a scan design semiconductor integrated circuit in which power consumption is reduced at the time of scan test. SOLUTION: A sequential circuit 41 comprises scan chain groups 31, 32 each comprising one or more scan chain. At the time of inspection, a scan control section 51 supplies the scan chain groups 31, 32 selectively with clocks of shift operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan-designed semiconductor integrated circuit and an inspection method for this circuit, and more particularly to power saving at the time of inspection.

[0002]

2. Description of the Related Art Factors that increase the power consumption of a semiconductor integrated circuit include the clock and flip-flop operation in the circuit. For this reason, the power supply of the semiconductor integrated circuit is reduced by stopping the clock supply to the unused function blocks and reducing the number of blocks operating at the same time.

On the other hand, as a method of inspecting a manufactured semiconductor integrated circuit for a failure, there is widely used a method of determining whether a predetermined output is obtained when inputting test data prepared in advance. Are known. At this time, so-called scan design is performed in which a part or all of the flip-flops are replaced with scan flip-flops in order to easily set or observe the values of the flip-flops in the circuit from the outside.

FIG. 6 shows an example of a conventional semiconductor integrated circuit using a scan chain. The scan flip-flops 11 to 14 constitute a scan chain 33, and test data is scanned in from a scan-in 10 by a clock 91 generated from a clock generation unit 90,
Scan out is performed from scan out 30.

Also, scan flip-flops 21 to 2
4 constitutes the scan chain 34, and the test data is scanned in from the scan-in 20 and scanned out from the scan-out 40 by the clock 92 generated from the clock generator 90.

For example, when test data 1010 is provided from scan-in 10 and test data 0011 is provided from scan-in 20, the values of these test data are simultaneously applied to the scan flip-flops constituting each scan chain. Is set. Scan flip-flop 11 constituting scan chain 33
14, the values of 1, 0, 1, and 0 are sequentially set in the scan flip-flops 11 to 14, respectively. At the same time, the scan flip-flops 21 to 24 forming the scan chain 34 are set to the scan flip-flops 21 to 24, respectively. The values of 0, 0, 1, and 1 are set in order, respectively.

[0007] The values stored in the scan flip-flops before the test data is supplied are sequentially output from the scan-out.

As described above, in a conventional semiconductor integrated circuit using a scan chain, a clock is simultaneously operated for each scan chain at the time of inspection, and scan-in and scan-out of test data are performed.

[0009]

In a semiconductor integrated circuit with a scan design, clocks in the circuit move at the same time at the time of inspection and all the scan flip-flops operate simultaneously, so that the power consumption of the circuit at the time of inspection is reduced. growing.

When the above-described scan test method is applied to a semiconductor integrated circuit whose power is saved by stopping the clock of an unused functional block, power more than normal operation is consumed. Thus, there is a problem that the circuit may malfunction or the circuit may be damaged in the worst case.

Although it is possible to operate all at once by making the power supply line thicker, there is a problem that the circuit area becomes large.

In view of the above problems, it is an object of the present invention to reduce power consumption during inspection in a scan-designed semiconductor integrated circuit.

[0013]

In order to solve this problem, the present invention groups scan chains in a circuit into a plurality of scan chain groups.
By selectively supplying a shift operation clock for each scan chain group, the number of scan flip-flops that operate simultaneously can be reduced.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. As shown in the figure, a scan chain group 31 and a scan chain group 32 are defined in the sequential circuit unit 41.

The scan chain group 31 includes a scan chain 35 and a scan chain 36, and the scan chain group 32 includes a scan chain 37 and a scan chain 38.

The scan chain 35 includes scan flip-flops 13 and 14. Similarly, the scan chain 36 includes the scan flip-flops 11 and 12
The scan chain 37 is connected to the scan flips 23 and 2
At 4, the scan chain 38 is composed of scan flip-flops 21 and 22.

At the time of inspection, the scan control unit 51
A clock for a shift operation is selectively supplied to each of the scan chain groups 31 and 32.

An inspection procedure in the semiconductor integrated circuit of the present embodiment configured as described above will be described with reference to a flowchart shown in FIG.

First, in step ST11, it is determined whether or not a scan chain in which scan-in processing of test data has not been completed exists in the circuit.

If there is, the process proceeds to step ST12. If not, the process proceeds to step ST14.

Here, since one scan chain has not been processed yet, the process proceeds to step ST12.

In step ST12, a test clock is applied to one of the scan chain groups in the circuit, and scan-in processing of test data is performed.

Here, the scan chain group 31
It is assumed that has been selected. The scan control unit 51 scans the scan chains 3 forming the scan chain group 31.
A clock for the shift operation is supplied only to 5 and 36.

Thus, the scan chains 35, 3
6, test data are scanned in from scan-in 1 and scan-in 2 respectively, and scan flip-flop 1
Values are set to 1 to 14.

Next, in step ST13, by stopping the test clock for the scan chain group for which the scan-in processing has been completed in step ST12,
Holds the values of all the scan flip-flops constituting the scan chains included in the scan chain group.

In this embodiment, when the setting of the values of the scan flip-flops 11 to 14 is completed, the supply of the clock of the shift operation to the scan chain group 31 from the scan control unit 51 is stopped, and the scan flip-flops 11 to 14 are stopped. Are held.

Steps ST11 to ST13 of FIG. 2 are repeated until test data is scanned in for all scan chain groups in the circuit.

In step ST11, it is determined whether there is any scan chain group for which the scan-in processing of the test data has not been completed. In the present embodiment, since the scan-in process for the scan chain group 32 has not been completed, the process proceeds to step ST12.

In step ST12, only the scan chains 37 and 38 constituting the scan chain group 32 are supplied with a shift operation clock from the scan control unit 51. Thus, scan-in 3, 4
Are subjected to scan-in processing, and values are set in the scan flip-flops 21 to 24.

Next, in step ST13, by stopping the clock supply of the shift operation to the scan chain group 32, the value set in the scan flips constituting the scan chains 37 and 38 is held.

This means that the test data has been scanned in for all the scan chain groups in the circuit.
Proceed to 4.

In step ST14, for all scan chain groups for which scan-in processing has been completed,
Scan-out processing is sequentially performed for each scan chain group.

First, a scan operation clock is supplied from the scan control unit 51 to the scan chain group 31 to perform a scan-out process, and the test result data is observed from the scan-outs 5 and 6. Next, a scan-out process is similarly performed on the scan group 32, and data of test results is observed in scan-outs 7 and 8.

Next, in step ST15, it is determined whether the inspection is to be ended as it is or to return to step ST11. If it is determined that the test has been completed, the inspection ends.

As described above, according to the present embodiment, the scan-in process and the scan-out process of the test data are sequentially performed for each scan chain group, so that the scan flip-flops in the circuit operating at the same time. The number and clocks can be reduced, and power consumption during inspection can be suppressed.

Further, since it is not necessary to make the power supply line thicker in accordance with the power consumption at the time of inspection, it is possible to suppress an increase in circuit area.

In this embodiment, the inspection method in which the scan-in process and the scan-out process of the test data are performed for all the scan chain groups has been described.
Even when the scan-in process and the scan-out process of the test data are performed only on the scan chain group necessary for detecting the fault assumed in the semiconductor circuit, the same effect as the present embodiment can be obtained.

(Embodiment 2) FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit according to Embodiment 2 of the present invention. 3, the same parts as those of the semiconductor integrated circuit of FIG. 1 according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The data control unit 52 includes the scan chain 3
5 and the scan chain 37 are logically connected to a scan-in 61, which is an external input pin, and a scan-out pin, to a scan-out 63, which is an external input pin.

The data control unit 52 logically connects the scan-in pins of the scan chains 36 and 38 to the scan-in 62, which is an external input pin, and the scan-out pin, to the scan-out 64, which is an external input pin. .

In the semiconductor integrated circuit configured as described above, scan-in processing and scan-out processing are performed in accordance with the flowchart shown in FIG. 2 as in the first embodiment.

Since scan-in and scan-out of test data are performed sequentially for each scan group, scan-in and scan-out of the scan chains 35 and 37 in different scan groups are not performed simultaneously.

Therefore, the scan-in pin and the scan-out pin of these scan chains can be shared and the scan-in 61 and the scan-out 63 can be used, respectively.

Similarly, since the scan chains of the scan chains 36 and 38 are not simultaneously scanned in and scanned out, the scan in pins and the scan out pins of these scan chains are shared, respectively. Scan-in 62 and scan-out 64 can be used.

As described above, the number of external input / output pins of the circuit can be reduced by sharing the scan-in pins of different scan chain groups and the scan-out pins of different scan chain groups. .

In this embodiment, the data control unit 52
Uses the branching of the net, but as shown in FIG.
2, the same effect as in the present embodiment can be obtained.

(Embodiment 3) FIG. 5 is a diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention. In the figure, the same parts as those in FIG.

The data control unit 52 is provided with the scan chain 3
5, the scan-in pin of the scan chain 37 is connected to the common scan-in / out 81, the scan-out pin of the scan chain 36 and the scan-in pin of the scan chain 38 are connected to the common scan-in / out 82, and the scan-in pin of the scan chain 35 and the scan-in The input / output switching circuits 55, 56, 57, and 58 respectively connect the scan-out pin of the chain 37 to the common scan-in / out 83, and the scan-in pin of the scan chain 36 and the scan-out-pin of the scan chain 38 to the common scan-in / out 84. Are logically connected via.

Since scan-in and scan-out of test data are sequentially performed for each scan group,
Scan-out of the scan chains 35 of different scan groups and scan-in of the scan chain 37 do not occur simultaneously.

Therefore, by appropriately switching these outputs and inputs through the input / output switching circuit 55, one input / output pin scan-in / out 81 can be shared.

Similarly, the scan-out of the scan chain 36 and the scan-in of the scan chain 38,
The scan-in of the scan chain 35 and the scan-out of the scan chain 37, and the scan-in of the scan chain 36 and the scan-out of the scan chain 38 can be shared by one input / output pin.

As described above, the number of external input / output pins of the circuit can be reduced by using the scan-in pins and the scan-out pins of different scan chain groups in common.

[0054]

As described above, according to the present invention, scan-in of test data is sequentially performed for each scan chain group.
By performing scan-out, the number of scan flip-flops in the circuit that operates simultaneously and the clock are reduced,
It is possible to suppress power consumption during inspection. Also, power consumption during inspection can be kept low,
The power supply line can be made thinner, and the circuit area can be reduced.

Furthermore, when scan-in and scan-out are sequentially performed for each scan chain group, the number of external pins can be prevented by sharing external input / output pins of scan chains that are not used at the same time.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment;

FIG. 2 is a flowchart showing an inspection procedure according to the first embodiment;

FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment.

FIG. 4 is a diagram illustrating another configuration example of a data control unit according to the second embodiment;

FIG. 5 is a configuration diagram of a semiconductor integrated circuit according to a third embodiment;

FIG. 6 is a configuration diagram of a semiconductor integrated circuit using a conventional scan chain.

[Explanation of symbols]

 1 scan-in 2 scan-in 3 scan-in 4 scan-in 5 scan-out 6 scan-out 7 scan-out 8 scan-out 11 scan flip-flop 12 scan flip-flop 13 scan flip-flop 14 scan flip-flop 21 scan flip-flop 22 scan flip-flop 23 scan Flip-flop 24 Scan flip-flop 31 Scan chain group 32 Scan chain group 35 Scan chain 36 Scan chain 37 Scan chain 38 Scan chain 41 Sequential circuit unit 51 Scan control unit

Claims (5)

[Claims] 1. A semiconductor integrated circuit having a plurality of scan chains, wherein a clock for a shift operation is selectively supplied to each scan chain. 2. The apparatus according to claim 1, further comprising a sequential circuit unit and a scan control unit, wherein the sequential circuit unit has a plurality of scan chain groups, and each of the scan chain groups includes one or more scan chains. A semiconductor integrated circuit, wherein the scan control unit is configured to be capable of selectively supplying a shift operation clock to each of the scan chain groups. 3. The method for inspecting a circuit in a semiconductor integrated circuit according to claim 2, wherein at the time of inspection, a clock for a shift operation is selectively supplied to each scan chain group and a scan chain is formed. A method for testing a semiconductor integrated circuit, comprising setting a value to a scan flip-flop or reading a value of a scan flip-flop. 4. An external pin corresponding to a scan-in pin or a scan-out pin of a plurality of scan chains belonging to different scan chain groups, and a clock of a shift operation selectively selected by a current scan control unit among the plurality of scan chains. 3. The semiconductor integrated circuit according to claim 2, further comprising a data control unit that logically connects the scan-out pin of the supplied scan chain and the external pin. 5. The semiconductor integrated circuit according to claim 1, wherein scan chains to which a clock for a shift operation is not simultaneously supplied share external pins for scan-in or scan-out.