JPH10191168A - Ccd image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a CCD image pickup element with high image quality capable of sampling while a period of correlation double sampling is sufficiently secured and in which a horizontal scanning period is shortened, a speed of feedback of automatic control and a speed of a monitor output are fast and the number of pixels is increased. SOLUTION: Common wiring is applied to each N-bit in a horizontal CCD register so that transfer parts 7W, 7X, 7Y, 7Z for each half-bit of the transfer part consisting N (N=2, 3, 4,... neural number) bits are driven independently. In a usual operation, same drive pulses (ϕH1), (ϕH2) are inputted to the transfer parts 7W and 7X, 7Y and 7Z at an interval of a half bit to actuate them through bi-phase complementary drive. In the case of operation at an N-fold speed, N sets of complementary drive pulses ϕH1a, ϕH2a, ϕH1b, ϕH2b are inputted to N-bit transfer parts 7W, 7X, 7Y, 7Z to actuate them through 2N phase complementary drive in the constitution of the CCD image pickup element 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD image sensor.

[0002]

2. Description of the Related Art In recent years, there has been a demand for increasingly high quality cameras for moving images and still images. To improve the image quality, it is sufficient to increase the number of pixels of the image sensor.
When the number of pixels is increased, the transfer rate at the time of frame transfer of the signal charges of the pixels, the so-called frame rate, becomes slow. For example, AF (auto focus; auto focus control), AE (auto iris; Feedback such as automatic exposure control) and AWB (auto white balance) becomes slow, and it becomes difficult to follow the movement of a camera or the movement of a subject when deciding a composition while watching a moving image output in an electronic still camera. Or

FIG. 9 shows a camera used in such a camera.
1 shows a plan view of an example of a CCD image sensor. The CCD image pickup device 51 transfers signal charges by a so-called interline transfer method. A plurality of light receiving sections 52 of photo sensors are arranged in a matrix.
The read gate unit 53 is provided for each column of each light receiving unit 52.
, A vertical CCD register 54 is connected to the horizontal CCD register 55, and the electric charge from the horizontal CCD register 55 is supplied to the amplifier 5.
6 and output voltage V
It is output as _out.

A vertical drive pulse φV1, φV2, φV3, φV4 is applied to a transfer electrode of the vertical CCD register 54, and signal charges are transferred by four-phase driving. On the other hand, in the horizontal CCD register 55, horizontal drive pulses φH1 and φH2 are alternately applied to transfer electrodes arranged corresponding to each light receiving section row, and signal charges are transferred by two-phase driving as described later. .

In order to increase the frame rate for the above-mentioned problem, it is conceivable to increase the driving frequency of the CCD register of the CCD image pickup device or the system. However, when the driving frequency is increased, the power consumption increases as a result. In the CCD image sensor, CDS (correlated double sampling) is used to cancel reset noise.
It is carried out. When the driving frequency is increased, it becomes necessary to adjust the phase of the sampling hold pulse in this sampling for each set, and the production efficiency is reduced.

[0006]

As a means for halving the horizontal scanning period without increasing the data rate from the CCD image pickup device, the driving frequency of the horizontal CCD register is doubled and the horizontal scanning period is doubled by floating diffusion (FD). There are a method of adding two pixels, and a method of doubling the driving frequency of the horizontal CCD register other than the last stage and adding two pixels at the last stage. The preset period and the data period of the output waveform that can be sampled are shortened.

FIG. 10 is a diagram showing the configuration of a two-phase driving horizontal CCD register of the CCD image pickup device 51 of FIG. 9 and a potential diagram in the transfer direction. FIG. 11 shows the driving pulses φH1 and φH2 and the CCD output waveform in the normal operation of the horizontal CCD register. Show.

As shown in FIG. 10, a horizontal CCD register 55 includes a storage electrode 57s made of, for example, a first layer of polycrystalline silicon and a second
Transfer electrode 57t made of polycrystalline silicon of the layer
Are arranged along the electrode transfer direction to form a plurality of transfer sections. A first-phase drive pulse φH1 is applied to the transfer electrodes 57 of every other transfer section, and a second-phase drive pulse φH2 is applied to the transfer electrodes 57 of the other alternate transfer sections. The signal charges are transferred by the complementary driving of the phases.

That is, as shown in FIG. 10, at time T1, the first-phase driving pulse φH1 is at a high level, the second-phase driving pulse φH2 is at a low level, and the potential of the transfer section to which φH1 is applied is deep. The signal charge e is transferred here.

Next, at time T2, the driving pulse φH1 of the first phase goes low, the driving pulse φH2 of the second phase goes high, the potential of the transfer electrode portion to which φH2 is applied becomes deep, and φH1 is applied. The signal charge is transferred from the transfer unit to which the signal φH2 is applied. Thus, the signal charges are sequentially transferred in the transfer direction by the two-phase drive pulses φH1 and φH2.

The first-stage transfer pulse φH1 is applied to the transfer unit at the last stage of the horizontal CCD register 55. At time T2, a floating diffusion (FD) (not shown) is supplied from the horizontal CCD register 55, although not shown.
Is transferred to a signal charge and converted into a signal voltage.

Floating diffusion (FD)
, A reset gate pulse φRG is applied to the reset gate portion adjacent to the floating diffusion (FD), and the charge of the floating diffusion (FD) is reset.

Thus, the CCD output waveform shown in FIG. 11 is obtained. The portion of Tp in the CCD output waveform is a preset signal,
The portion of Td is a section indicating a data signal. In order to improve the S / N ratio, the output signal from the CCD image pickup device is usually correlated double sampling, that is, the preset signal Tp is first clamped, and then the data signal Td is sampled.

If the number of pixels is increased in order to improve the image quality, the speed of capturing one screen, that is, the so-called frame rate, becomes slow. As described above, feedback such as AF, AE, and AWB using a CCD output signal is performed. May be slow, or it may be difficult to confirm the composition by displaying it on a liquid crystal screen or the like.

To improve this, for example, horizontal CC
There is a method of increasing the output data rate by doubling the driving frequency of the D register. FIG. 12 shows the horizontal drive clock pulse and the CCD output waveform in this case. Since the drive frequency is doubled, the wavelengths of the horizontal drive pulses φH1 and φH2 and the reset gate pulse φRG are each halved, and the period of the CCD output waveform is also halved.

However, in this case, the widths Tp2 and Td2 of the portions where clamping and sampling are performed are の of those in the normal case, and it is necessary to adjust the phase of the clamp pulse and the sampling pulse one by one. The sex falls. Moreover, since the data rate is doubled,
The speed of signal processing is also doubled, so that power consumption and noise also increase. Further, since the design of the system is restricted, it is disadvantageous in terms of manufacturing cost.

On the other hand, a horizontal CCD without changing the data rate
As a method of doubling the scanning speed of the register, there is a method of adding signal charges of two horizontal pixels by floating diffusion (FD). FIG. 13 shows the horizontal drive pulse and the CCD output waveform in this case.

In this method, the lengths of the preset period Tp3 and the data period Td3 are halved as in the case of Tp2 and Td2, respectively, as in the case of Tp2 and Td2. this is,
This is because Tp3 is limited by the first high-level period of the horizontal drive pulse φH1, and Td3 is limited by the second low-level period of the horizontal drive pulse φH1.

In order to solve the above-mentioned problem, in the present invention, the output waveform from the CCD image pickup device can be made the same in the normal driving and the N-times driving, and the period of the correlated double sampling is sufficiently ensured. Can be done,
An object of the present invention is to provide a CCD image pickup device suitable for high image quality by shortening the horizontal scanning period, providing quick feedback of automatic control and monitor output, and increasing the number of pixels.

[0020]

According to the CCD image pickup device of the present invention, the transfer section for each half bit of the transfer section constituting N (N = 2, 3, 4, ‥‥ natural number) bits of the horizontal CCD register is used. Common wiring every N bits so that they can be driven independently,
In normal operation, the same drive pulse is input to the transfer unit every half bit to operate by two-phase complementary drive. In N-times speed operation, N sets of complementary drive pulses are input to the N-bit transfer unit. And 2N-phase complementary driving.

According to the configuration of the present invention described above, in the N-times speed operation, the horizontal scanning period can be reduced to 1 / N by operating the horizontal CCD register by 2N-phase complementary driving, and the correlation is doubled. The clamp pulse and the sampling hold pulse in the sampling can be the same as those in the normal operation, and the period of both pulses can be secured for a sufficient period as in the normal operation.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a horizontal CCD register in which transfer units for each half bit of transfer units constituting N (N = 2, 3, 4, ‥‥ natural number) bits can be independently driven. In the normal operation, the same drive pulse is input to the transfer unit every half bit to operate by two-phase complementary drive. In the N-times speed operation, N groups are connected to the N-bit transfer unit. Is a CCD image pickup device which receives complementary drive pulses of the above and operates by 2N-phase complementary drive.

Further, in the present invention, in the above-mentioned CCD image pickup device, the phase of the drive pulse applied to the transfer section at the last stage of the horizontal CCD register is the same as the phase of one drive pulse in the normal operation.

According to the present invention, in the CCD image pickup device, readout gates corresponding to the respective light receiving section rows can be driven every other row to every Nth row. In normal operation, all the readout gates are turned on to read out signals. In the N-times operation, only one of the read gates in N columns is turned on to read only 1 / N columns.

According to the present invention, in the CCD image pickup device, a drain region for discharging electric charges via a gate portion is provided below the horizontal CCD register, and the gate portion is turned on during a horizontal blanking period in N-times speed operation. After the signal charges corresponding to the (N-1) th of the N columns of the light receiving section are discarded to the drain region, the charge is transferred by the horizontal CCD register.

Hereinafter, embodiments of the CCD image pickup device of the present invention will be described with reference to the drawings. FIG. 1 shows a CCD according to this embodiment.
The imaging device is shown as a whole. This CCD imaging device 1
A so-called interline transfer method is adopted, in which a plurality of light receiving units 2 formed of photo sensors serving as pixels are arranged in a matrix, and columns of the light receiving units 2 are arranged via readout gate units 3 provided adjacent to each light receiving unit 2. A vertical CCD register 4 is provided for each. Each vertical CCD register 4 is connected to a horizontal CCD register 5, and the signal charge transferred by the horizontal CCD register 5 is converted into an output voltage V _out via an output circuit such as an amplifier 6, and then output.
The vertical CCD register 4 stores, for example, a four-phase vertical drive pulse φ.
Driven by V1, φV2, φV3, φV4.

The present embodiment is characterized by the configuration of the horizontal CCD register 5. That is, as shown in FIG. 2, the horizontal CCD register 5 has an insulating film 1 on a semiconductor substrate 11.
For example, a plurality of transfer electrodes 7 including a storage electrode 7 s made of a first-layer polycrystalline silicon and a transfer electrode 7 t made of a second-layer polycrystalline silicon are arranged along the electrode transfer direction through the second electrode 2. Transfer units 7W, 7
X, 7Y, and 7Z are configured.

For the transfer electrodes 7 of the transfer sections 7W, 7X, 7Y, 7Z, the first drive pulse φH1a, the second drive pulse φH2a, the third drive pulse φH1b, and the fourth drive pulse φH1a are independent of each other by four repetitions. Drive pulse φH2b,
The first drive pulse φ is applied to the transfer electrode 7 of the transfer unit 7W in the last stage.
Wiring is performed to give H1a. That is, the transfer section to which the first drive pulse φH1a is applied is set to 7 W, and the second, third, and fourth drive pulses φH2a, φH
1b and φH2b are given by 7X and 7
Y, 7Z. It should be noted that one bit is constituted by two adjacent transfer units, and these two transfer units correspond to the vertical CCD registers 4 of each column.

A horizontal output gate section 8 is formed adjacent to the final-stage transfer section 7W, and a floating diffusion (FD) region 9 constituting a charge / voltage conversion section.
The reset gate portion 10 to which the reset gate pulse φRG is applied and the reset drain region 13 are formed.

The signal charge transferred to the final transfer section 7W is transferred to the floating diffusion region 9 via the horizontal output gate section 8. After the charge-voltage conversion in the floating diffusion region 9 and the reading of the signal, the floating diffusion region 9
Is reset to the reset drain region 13 via the reset gate section 10.

Next, the CCD image pickup device 1 of the above-described embodiment will be described.
, Especially the operation of the horizontal CCD register 5 will be described. FIG. 2 shows the horizontal CC of the CCD image pickup device 1 of this embodiment.
FIG. 3 shows a potential diagram in the transfer direction of the D register 6, and FIG.
a, φH1b, φH2a, φH2b and CCD output waveform,
FIG. 4 shows a vertical CCD register 5 to a horizontal CCD register 6.
FIG. 5 shows the driving pulses φH1 and φH2 and the CCD output waveform in the normal operation of the horizontal CCD register.

In the case of a so-called normal operation in which data is transferred at a normal speed, as shown in FIG. 5, the first drive pulse φH1a and the third drive pulse φH1b are set to the same clock pulse, and the second drive pulse φH2a is The fourth drive pulse φH2b has the same clock, and the first and third drive pulses φH1a, φH1b and the second and fourth drive pulses φH
2a and φH2b are set to have opposite phases to each other to form a so-called two-phase driving pulse, whereby signal charges are transferred by so-called two-phase complementary driving. This driving is performed according to the aforementioned FIG.
0 and the drive shown in FIG.

Next, in the case of the double speed operation, the driving pulse (φH
1a, φH2a, φH1b, φH2b), as shown in FIG. 3, the first drive pulse φH1a and the third drive pulse φH1b have phases opposite to each other, and the second drive pulse φH
2a and the fourth drive pulse φH2b have opposite phases to each other, and a pair of first and third drive pulses φH1a and φH1b and second and fourth drive pulses φH2a and φH2
The phase of the pulse of the set b is set to be shifted (in this example, shifted by half of the half wavelength of the pulse).
Charge transfer is performed by phase complementary driving.

As shown in FIGS. 2 and 3, first, at time T
1, the first drive pulse is high at φH1a,
Drive pulse φH1b goes low, the second drive pulse φH2a goes high, the fourth drive pulse φH2b goes low, and the potentials of the transfer sections 7W and 7X to which φH1a and φH2a are applied are deepened. Therefore, φH
The signal charges e corresponding to the respective pixels are transferred below the storage electrodes 7s of the transfer units 7W and 7X to which 1a and φH2a are applied. At this time, the reset gate pulse φ
When RG is applied, the potential of the reset gate unit 10 is deepened, and the charge in the floating diffusion region 9 is reset. This reset gate pulse φR
G has the same phase as the reset gate pulse φRG in the normal operation with respect to the drive pulse φH1a of the final stage transfer unit 7W.

Next, at time T2, the second and fourth drive pulses φH2a and φH2b are inverted, φH2a goes low, φH2b goes high, and the potential of the transfer section 7X to which φH2a is applied becomes shallow, The potential of the transfer section 7Z to which φH2b is applied becomes deep. Therefore,
The transfer section 7X of φH2a is added to the transfer section 7W of φH1a in the final stage.
And the signal charges for two pixels are added. The intermediate signal charges e are transferred to the transfer units 7 of φH1a and φH2a.
W, 7X are transferred to the transfer units 7Z, 7W of φH2b, φH1a. The reset gate unit 10 is turned off, and signal charges can be stored in the floating diffusion region 9.

Next, at time T3, the first and third drive pulses φH1a and φH1b are inverted, φH1a goes low, φH1b goes high, and the potential of the transfer section 7W to which φH1a is applied becomes shallow, The potential of the transfer section 7Y to which φH1b is applied becomes deep. And
The signal charge e for two pixels added to the transfer unit 7W in the final stage
Is transferred to the floating diffusion region 9. At the same time, the charges in the transfer sections 7Z and 7W of φH2b and φH1a are transferred to the transfer sections 7Y and 7Z of φH1b and φH2b.

At time T4, the second and fourth drive pulses φH2a and φH2b are again inverted, φH2a goes high, φH2b goes low, and the potential of the transfer section 7X to which φH2a is applied becomes deep, The potential of the transfer section 7Z to which φH2b is applied becomes shallower. Then, the signal charges e are transferred to the transfer units 7Y and 7H of φH1b and φH2b.
Z is transferred to the transfer units 7X and 7Y of φH2a and φH1b.

Thereafter, the state becomes the same as that at time T1, the first and third drive pulses φH1a and φH1b are again inverted, φH1a becomes high level, φH1b becomes low level, and the transfer section to which φH1a is applied. The potential of 7W becomes deep, and the potential of the transfer section 7Y to which φH1b is applied becomes shallow. The signal charge e is φH2a, φH
The data is transferred from the 1b transfer units 7X and 7Y to the transfer units 7W and 7X of φH1a and φH2a. When the reset gate pulse φRG is turned on, the signal charges e accumulated in the floating diffusion region 9 are reset.

By repeating the above states T1 to T4, the signal charges e are sequentially transferred in the transfer direction. In the correlated double sampling circuit, the CC shown in FIG.
The preset signal is clamped during the period Tp4 of the D output, and the data signal is sampled during the period Td4.

In the normal operation, it takes one clock of φH1a to move from H1a to H1b, but in the double speed operation of the present example, the transfer can be performed in a time equivalent to a half clock of T2 → T4. That is, the horizontal scanning period can be halved.

FIG. 4 shows the state of charge transfer from the vertical CCD register 4 to the horizontal CCD register 5 to the above-mentioned time point T1. The transfer from the vertical CCD register 4 to the horizontal CCD register 5 is performed during the horizontal blanking period by normal four-phase driving. 4A shows a potential diagram, and FIG. 4B shows a driving clock pulse. Vertical CCD
The driving pulse of the transfer unit at the final stage of the register 4 is φV3, and the signal charge is transferred to the transfer unit 7Y of the horizontal CCD register to which φH1b is applied.

After the horizontal CCD transfer is performed during the horizontal scanning period as described above, the horizontal blanking period starts. And
First, at time T5, the first and third drive pulses φH1
a and φH1b are at a high level, the second and fourth drive pulses φH2a and φH2b are at a low level, and the signal charge is a transfer unit to which the first and third drive pulses φH1a and φH1b are applied. 7W and 7Y. On the other hand, in the vertical CCD register 4, the drive pulse φV2 of the transfer unit immediately before the final stage is at a high level, and the drive pulse φV3 of the transfer unit of the final stage is at a low level. There is a signal charge.

Next, at time T6, the driving pulse φV3 of the final stage transfer unit of the vertical CCD register 4 becomes high level, and the potential of the last stage transfer unit and the potential of the immediately preceding transfer unit are the same depth. become. Subsequently, at time T7, the drive pulse φV2 of the transfer unit immediately before the final stage of the vertical CCD register 4 becomes low level, so that the signal charge is transferred to the φH1b of the horizontal CCD register 5 via the final stage transfer unit. Is transferred to the transfer unit 7Y.

Next, at time T8, the driving pulse φV3 of the last stage of the vertical CCD register 4 also becomes low level, so that the remaining signal charges also become φ of the horizontal CCD register 5.
The data is transferred to the transfer unit 7Y of H1b.

Thereafter, at the time point T1, the horizontal C
When φH1b is at a low level and φH2a is at a high level among the drive pulses of the CD register 5, φH1b
Is transferred to the transfer unit 7X of φH2a. Thereafter, the horizontal scanning period starts again, and transfer by the horizontal CCD register is performed by four-phase complementary driving.

According to the above-described embodiment, in the horizontal CCD register 5, when the double speed operation and the normal operation are compared, the reset gate pulse φRG and the first driving pulse φH1a of the final stage transfer unit are compared. The phase does not change between the double speed operation and the normal operation.

Accordingly, since the CCD output waveform depends on the phase of the drive pulse φH1a at the final stage of the horizontal CCD register 5 and the phase of the reset gate pulse φRG, the phases of φH1a and the reset gate pulse φRG do not differ from normal phases as in this embodiment. In the method, the CCD output waveform also has the same phase waveform, and the clamp pulse and sampling pulse of the interphase double sampling can be used with the same phase. That is, correlation 2
The period Tp5 for clamping the preset signal and the period Td5 for sampling the data signal for performing the multiple sampling are the periods Tp4 and Tp in the case of the above-mentioned double speed operation.
It has the same width as d4. Therefore, even in the double-speed operation, a period for performing the correlated double sampling can be sufficiently secured as in the normal operation.

From the viewpoint of the system configuration, it is desirable that the frequencies used be the same. Thus, the pulses can be used at the same frequency in the normal operation and the double-speed operation, so that the system can be simplified.

In the above example, the double-speed operation is performed by four-phase complementary driving. In principle, however, the number of gates to be separated, that is, the number of transfer sections to which drive pulses are independently applied is increased, and 2N ( (N = 2, 3,..., Natural number), by performing N-times speed operation by complementary driving, the horizontal scanning period can be reduced to 1 / N
Can be For example, when performing 3x speed operation,
Drive pulses φH1a, φH2a, φH are sequentially applied to each transfer electrode.
1b, φH2b, φH1c, φH2c, and φH1
a and φH2b, φH2a and φH1c, φH1b and φH2
Each drive pulse may be set such that c is in opposite phase and each of the pairs of pulses in opposite phase relationship is shifted in phase by ３ of a half wavelength. Also in this case, the clamp pulse and the sampling hold pulse of the interphase double sampling can be used in the same phase in the normal operation and the N-times operation, and also in the N-times operation, the period of the clamp pulse and the sampling hold pulse is the same as in the normal operation. Can be sufficiently secured.

As described above, since the horizontal scanning period can be reduced to 1 / N, feedback such as AE / AWB / AF becomes faster. Further, the monitor output to a liquid crystal screen or the like can be made to follow the movement of the camera.

Next, another embodiment of the CCD image pickup device according to the present invention will be described. In the above-described embodiment, as shown in FIG. 2, in the case of double-speed operation, horizontal two pixels are added in the horizontal CCD register 6, but it is necessary to separate color signals in a single color CCD. is there.
Therefore, for example, a CCD image pickup device is configured as follows.

The CCD image pickup device 21 shown in FIG. 6 is an example of a case where a signal is read from the light receiving unit every other column when reading out signal charges from the light receiving unit 2 composed of a photo sensor to the vertical CCD register 4. For example, taking the case where filters of three colors R, G, and B are arranged as shown in the figure, for example,
(However, various patterns are conceivable for the arrangement of the R, G, and B filters.) For example, the first drive pulse φSG1 is applied to the readout gate unit 3 of the light receiving unit 2 in the odd-numbered row, The second drive pulse φSG is applied to the gate unit 3.
2 can be applied independently.

In the case of the double speed operation, the driving pulse φS
The signal of the light receiving section in the odd-numbered column is read out by G1, and the horizontal CC
After the signal is output through the D register 5, the signals of the light receiving units in the even rows are read out by the drive pulse φSG2 and output through the horizontal CCD register 5, so that the color signals of each light receiving unit row are not mixed. Color signals can be separated in a single CCD. When operating in the normal operation, that is, in the standard mode (so-called two-phase driving), the first and second drive pulses φSG1 and φSG2 are simultaneously applied to turn on all the read gate units 3 to read data.

Similarly, as another configuration for separating color signals in a single-chip color CCD, a configuration in which reading is performed every two columns as shown in FIG. 7 can be employed.

The CCD image pickup device 31 applies a driving pulse applied to the readout gate unit 3 for reading out signal charges from the light receiving unit 2 composed of a photo sensor to the vertical CCD register 4 at every two light receiving unit rows. Different drive pulse φ
This is an example where SG1 and φSG2 are applied. That is,
The read gate unit 3 is configured such that a row to which the first drive pulse φSG1 is applied and a row to which the second-phase drive pulse φSG2 is applied are each formed of two light receiving unit rows as one set of φS
Each set of G1 and φSG2 is arranged alternately.

In the case of the double speed operation, φSG1 and φSG2 are alternately applied to the pair of adjacent two sensor rows with a time difference therebetween, and the read gate unit 3 is driven. Without mixing the signals,
Color signals can be separated in a single CCD. Further, driving may be performed by applying only to one of φSG1 and φSG2. When operating in the standard mode, the drive pulses φSG1 and φSG2 are simultaneously applied to turn on all the read gate units 3 to read data.

It should be noted that the CCD image pickup devices 21 and 31 shown in FIGS. 6 and 7 can be applied to N-times operation. In this case, the read gates can be driven every other row to every Nth row (for example, every 3rd row operation, every 1st row, every 2nd row, or every 3rd row). It is sufficient to turn on only one column of read gates and read only 1 / N columns.

As shown in FIG. 8, it is also possible to adopt a configuration in which the drain region provided below the horizontal CCD register has a function of discarding the signal charges in the horizontal CCD every other row or every two rows. . The example of FIG. 8 is an example of a case where every other row is discarded. This CCD image sensor 41
The signal charges from the vertical CCD registers 4 in, for example, the odd columns are blocked by the channel stop 43 in parallel with the horizontal CCD registers 5, and the vertical CCD registers in the even columns are
The signal charge from the register 4 is provided with a drain region 42 for discharging the charge through a gate portion 44 through which the signal charge passes.
Gate pulse φHDG is applied to gate section 44.

In the case of double-speed driving, the signal charges transferred from the vertical CCD register 4 enter the horizontal CCD register 5 and then are transferred and output by the horizontal CCD register 5. At this time, the light receiving corresponding to the odd columns is performed. Although the signal charges of the section 2 are transferred to the horizontal CCD register 5, the signal charges of the light receiving section 2 corresponding to the even-numbered columns are discarded to the drain region 42 via the gate section 44 by the horizontal CCD register 5. Therefore, in the horizontal CCD register 5, only the signal charges of the light receiving sections 2 in the odd columns are transferred and output.

In this way, by arranging the signal charges of the light receiving section rows every other row to be discarded to the drain region 42 through the horizontal CCD 5, the signals of the light receiving section rows are not mixed, and the single-plate CCD is not mixed. Can separate the color signals. In the case of the standard mode, the gate section 44 is turned off so that all signal charges are transferred to the horizontal CCD register 5. Although not shown, two adjacent rows of the rows of the light receiving sections 2 are collectively discarded every two rows.
Similarly, signal separation can be performed.

Incidentally, the CCD image pickup device 41 shown in FIG.
When applied to the double speed operation, the signal charges in one of N columns of the light receiving unit 2 are transferred to the horizontal CCD register 5, and the signal charges in N−1 of the remaining N columns are discarded to the drain region 42. What is necessary is just to comprise.

The CCD image pickup device of the present invention is not limited to the above-described example, and may take various other configurations without departing from the gist of the present invention.

[0063]

According to the CCD image pickup device of the present invention described above, the horizontal scanning period can be reduced to 1 / N.
Feedback such as AWB / AF becomes faster. In addition, the monitor output to a liquid crystal screen or the like follows the movement of the camera, so that a photograph can be taken without missing a photo opportunity.

Further, according to the present invention, the phase margin of the clamp pulse for clamping the CCD output and the sample and hold pulse for sampling can be sufficiently obtained even at the N-times speed operation, so that the productivity of the set is improved.

Further, the same clamp pulse for clamping the CCD output and the same sampling hold pulse for sampling can be used for the normal operation and the N-times operation, so that the system can be simplified.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram (plan view) of an embodiment of a CCD imaging device of the present invention.

FIG. 2 is a horizontal CCD of an embodiment of the CCD image pickup device of the present invention.
FIG. 4 is a potential diagram of a register in a transfer direction.

FIG. 3 shows a horizontal driving clock pulse and a CCD output waveform in a double speed operation of the embodiment of the CCD image pickup device of the present invention.

FIG. 4 is a diagram for explaining transfer from a vertical CCD register to a horizontal CCD register in a double speed operation of the embodiment of the CCD image pickup device of the present invention. A is a potential diagram of the last stage of the vertical CCD register and the horizontal CCD register. B is a timing chart showing a part of a vertical drive clock pulse and a horizontal drive clock pulse.

FIG. 5 shows a horizontal drive clock pulse and a CCD output waveform in a normal operation of the embodiment of the CCD image pickup device of the present invention.

FIG. 6 is a schematic configuration diagram (plan view) of another embodiment of the CCD image pickup device of the present invention.

FIG. 7 is a schematic configuration diagram (plan view) of still another embodiment of the CCD image pickup device of the present invention.

FIG. 8 is a schematic configuration diagram (plan view) of another embodiment of the CCD image pickup device of the present invention.

FIG. 9 is a schematic configuration diagram (plan view) of an example of a CCD image sensor.
It is.

FIG. 10 is a potential diagram in a transfer direction of a conventional horizontal CCD register of the CCD image sensor.

FIG. 11 shows a conventional horizontal drive clock pulse and a CCD output waveform of a CCD image sensor.

FIG. 12 shows a horizontal drive clock pulse and a CCD output waveform of a double-speed operation CCD image sensor.

FIG. 13 shows a horizontal drive clock pulse and a CCD output waveform of the CCD image sensor in the FD addition operation.

[Explanation of symbols]

1,21,31,41 CCD image sensor, 2 light receiving unit (photo sensor), 3 read gate unit, 4 vertical CC
D register, 5 horizontal CCD register, 6 amplifier (output circuit), 7 transfer electrode, 7s storage electrode, 7t
Transfer electrode, 7W, 7X, 7Y, 7Z transfer section, 8 horizontal output gate section, 9 floating diffusion area, 10 reset gate section, 11 semiconductor substrate, 12 insulating film, 13 reset drain area,
42 drain region, 43 channel stop, 44
Gate unit, 51 CCD image sensor, 52 Light receiving unit (photo sensor), 53 Read gate unit, 54 Vertical CC
D register, 55 horizontal CCD register, 56 amplifier (output circuit), 57 transfer electrode, 57s storage electrode, 57t transfer electrode, e signal charge

Claims (4)

[Claims] In a horizontal CCD register, N (N =
In order to be able to independently drive the transfer unit for each half bit of the transfer unit constituting 2, 3, 4, {natural number) bits, the above N
In the normal operation, the same drive pulse is input to the above-mentioned transfer unit every half bit and operated by two-phase complementary drive. In the N-times speed operation, N sets of the N-bit transfer unit are provided. Wherein the complementary driving pulse is inputted and the CCD is operated by 2N-phase complementary driving. 2. The drive circuit according to claim 1, wherein the phase of the drive pulse applied to the transfer section at the last stage of the horizontal CCD register is the same as the phase of one drive pulse in the normal operation. CCD image sensor. 3. A read gate corresponding to each light receiving section row can be driven every other row to every N rows. In the normal operation, all the read gates are turned on to read a signal.
2. The CCD image pickup device according to claim 1, wherein in the N-times speed operation, only one of the read gates in N columns is turned on and only 1 / N columns are read. 4. A drain region for discharging electric charges via a gate portion below the horizontal CCD register. In the N-times speed operation, the gate portion is turned on during a horizontal blanking period, and an N column of the light receiving portion is turned on. 2. The CCD image pickup device according to claim 1, wherein the charge transfer by the horizontal CCD register is performed after discarding the signal charges corresponding to the (N-1) th column to the drain region.