JPH10190742A - Data transmitting method/device, data receiving method/ device and integrated circuit for link layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To load an ATM(asynchronous transfer mode) on an IEEE 1394 serial bus. SOLUTION: The ATM cell is constituted of the cell header of five bytes and the following payload of 48 bytes. The 'reserved' of three bytes is added in front of the cell header as padding. Thus, the length of the cell is set to 56 bytes (integer-times as much as four bytes). The source packet header of four bytes is given in front of the cell and the CIP(common isochronous packet) header of eight bytes is given in front of the header. Then, the 1394 isochronous packet header of two bytes is given in front of the header. The isochronous packer which is thus constituted is transmitted to the IEEE 1394 serial bus with the timing of a cycle start packet flowing on the IEEE 1394 serial bus at 125μsec as a standard.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a technology for performing communication by placing ATM (asynchronous transfer mode) data on a high-speed serial bus (hereinafter, referred to as a 1394 serial bus) compliant with (hereinafter, abbreviated as 1394).

[0002]

2. Description of the Related Art Electronic devices such as a personal computer (hereinafter referred to as a personal computer), a digital video camera, a digital tuner, and a hard disk drive are connected by a 1394 serial bus, and these electronic devices (hereinafter referred to as "devices").
Among them, a system for communicating digital image signals, digital audio signals, and the like has been considered. In this system,
Cables specified by 1394 (hereinafter referred to as 13)
(Referred to as a 94 cable) makes it possible to communicate digital image signals and digital audio signals among the devices, and to control all the devices in a unified manner.

On the other hand, ATM is used in a network such as a personal computer LAN or B-ISDN (Broadband ISDN). This ATM is based on ITU-T (International
alTelecommunication Uion
-Telecommunication). A packet (usually called a cell) used in ATM has a packet size of 5 as shown in FIG.
It has a fixed length of 53 bytes consisting of a byte length ATM cell header followed by a 48 byte length payload. The 5-byte cell header has the structure shown in FIG. ATM does not require a synchronous relationship between the phase of a frame in the network and the position of a cell or the position of a cell, so that it is suitable for constructing a network in which data of various bit rates coexist.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has as its object to enable communication by placing ATM cells on a 1394 serial bus.

[0005]

SUMMARY OF THE INVENTION A data transmission method according to the present invention is an AT used in an ATM network.
It is characterized in that a predetermined header is added so that the M cell is transmitted using an isochronous packet configuration defined in the 1394 format.

A data transmission apparatus according to the present invention stores an ATM cell used in an ATM network in 1394.
It is characterized in that it has an additional circuit for adding a predetermined header in order to store it in the data field of the isochronous packet defined in the format.

[0007] A data receiving method according to the present invention comprises:
In order to obtain an ATM cell stored in a data field of an isochronous packet defined in a format, a predetermined header is removed.

[0008] The data receiving apparatus according to the present invention comprises:
In order to obtain an ATM cell stored in the data field of the isochronous packet defined in the format, the apparatus has a removing circuit for removing a predetermined header.

[0009] The integrated circuit for link layer according to the present invention comprises:
In order to obtain a basic block for communicating with a serial bus conforming to the H.94 format, an interface for communicating with an ATM network, and an ATM cell received from the serial bus and stored in the data field of the isochronous packet, A removing circuit for removing a header, an adding circuit for adding a predetermined header for storing the ATM cell received from the ATM network in the data field of the isochronous packet, the adding circuit, the removing circuit, A buffer provided between the interface and the interface for adjusting a rate.

According to the data transmission method of the present invention, A
A predetermined header is added to the ATM cells used in the network of the TM system, and the packet is transmitted in the form of an isochronous packet defined in the 1394 format.

According to the data transmission apparatus of the present invention, A
A predetermined header is added to the ATM cell used in the network of the TM system by an adding circuit, and is stored in the data field of the isochronous packet defined in the 1394 format.

According to the data receiving method of the present invention, 1
A predetermined header is removed from the isochronous packet defined in the 394 format, and an ATM cell stored in the data field is obtained.

According to the data receiving apparatus of the present invention, 1
A predetermined header is removed from the isochronous packet defined in the 394 format by a removal circuit,
The ATM cell stored in the data field is obtained.

According to the link layer integrated circuit of the present invention, the basic block communicates with the serial bus conforming to the 1394 format, and the interface communicates with the ATM network. At the time of transmission to the serial bus, the AT received from the ATM network by the interface is used.
A predetermined header is added to the M cell by an additional circuit, and upon reception from the serial bus, the predetermined header is removed from the isochronous packet defined in the 1394 format by the removal circuit, and the ATM cell stored in the data field is removed. Is obtained. Further, the data rate is adjusted by the buffer at the time of transmission / reception to the serial.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a process up to placing ATM cells on a 1394 serial bus. Details of these processes will be described later with reference to FIG. First, as shown in FIG. 6A, an input ATM source packet (FIG. 6A)
(ATM cell) is added with a source packet header at the beginning, as shown in FIG. Next, as shown in FIG. 1 (c), the ATM source packet is transmitted to an Is
o Depending on the timing of arrival at the packet transmission / reception FIFO 13, one or more (ATM cells + source packet headers) may be preceded by a CIP (Common Isochron) depending on the state of permission for transfer to the 1394 cable.
ou.Packet) header. Next, as shown in FIG. 1D, by adding a 1394 isochronous packet header, the ATM cell is stored in the data field of the isochronous packet, and flows over the 1394 serial bus in 125 μsec. The isochronous packet is transmitted to the 1394 serial bus based on the timing of the cycle start packet. Note that the source packet header,
Details of the CIP header and the 1394 isochronous packet header will be described later.

FIG. 2 shows an example of the structure of an isochronous packet put on the 1394 serial bus in FIG. 1, and FIG. 3 shows the contents of 7 bytes from the 1394 isochronous packet header to the cell header in FIG. The numbers in parentheses in FIG. 3 are the number of bits. In the isochronous packet, the left end of the 1394 isochronous packet header at the upper end is transmitted first, and the right end of the data CRC at the lower end is transmitted last. Hereinafter, the isochronous packet will be described with reference to FIGS.

The 1394 isochronous packet header has a length of 8 bytes, a data length (2 bytes) indicating the length of data following the header, a tag (2 bits) indicating the presence or absence of a CIP header, and an isochronous packet. Channel (6) indicating the number of the channel transmitting the packet
Bit), a t code (4 bits) indicating the type of packet, sy (4 bits) indicating the order of the packet, and a header CRC (4 bytes).

6-bit SID in CIP header
(Source node ID) is the node I on the 1394 serial bus of the device that transmits the isochronous packet.
Represents D. 1-byte DBS (data block size)
Is the quadlet length of the data block (= 4 bytes)
It is a number expressed in units. The 2-bit FN (fraction number) indicates the number of data blocks into which the source packet is divided. A 3-bit QPC (Quadlet Padding Counter) is used when FN takes a value other than "0". The 1-bit SPH is set to "1" when the source packet has a unique source packet header. Therefore, it is set to “1” here. The DBC (Data Block Counter) is an 8-bit continuous counter, and is used to detect transmission loss of a source packet. A 6-bit FMT (format ID field) indicates a format of data to be transmitted. Here, A is set to 0x28.
Indicates TM data. The specification of the 3-byte FDF (format-dependent field) is determined by the FMT.

After the CIP header, ATM data in units of 15 quadlets (1 quadlet = 4 bytes) is sent. The 15 quadlets are composed of a source packet header of 1 quadlet, a cell header of 2 quadlets, and a payload of 12 quadlets.

The cycle count and the cycle offset of the source packet header are time stamp information created based on the transmission time of the packet in units of 125 μsec, and are given from the cycle master to the header. The cycle offset is given by a count every 40 ns, and when the cycle offset reaches 125 μsec, the cycle count is carried. The cycle count is a value that is sequentially counted up, such as 125 μsec (8 kHz) as one count and 250 μsec as two counts.

The cycle count and the cycle offset are values of a cycle time register provided in a predetermined device connected to the 1394 serial bus and designated as the cycle master (see FIG. 5).
The value in the cycle time register is stored based on time information generated by the master clock generator. This value is stored in a cycle start packet transmitted by the cycle master onto the 1394 serial bus, and is thereby given to other devices on the 1394 serial bus.
The configuration of the source packet header is the same as that specified in the MPEG-format transport stream (MPEG-TS) as described later. The cell header is as shown in FIG. 6 (b), and its contents are well known and will not be described here. However, in this embodiment, 3 is added before the 5-byte ATM cell header.
By adding "reserved" bytes as padding, the head of the payload starts from the head of the quadlet. This padding process is described in FIG.
At the ATM signal processing interface 12.

The data CRC is a code for error correction of a data field (from the CIP header to the last transmitted cell) of the isochronous packet.

The advantage of the structure shown in FIGS. 2 and 3 is that ATM cells can be placed on the 1394 serial bus. Another advantage is that the source packet header has an MPEG transport stream (MPEG- T
It has the same structure as S). Therefore, circuit blocks such as an iso packet transmitting / receiving FIFO 13, a header, a synchronization information adding circuit 14, a header removing and a synchronization information restoring circuit 15, which will be described later, can be shared by the signal system of the MPEG-TS. Can be shared. This is advantageous in terms of design and cost, and also makes it possible to execute time stamp processing for absorbing jitter, which will be described later.

In FIGS. 2 and 3, 3 bytes of “reserved” are added before the ATM cell header, but 3 bytes of “reserved” are added after the payload, not before the ATM cell header. Thus, the length of the ATM source packet may be an integral multiple of 4 bytes (here, 56 bytes). FIG. 4 shows the structure of the isochronous packet in that case.

Next, the above-described ATM cell is stored in 139.
4 Equipment that performs processing on the serial bus, for example, ATM
A set-top box (STB) connected to a network will be described. FIG. 5 illustrates the internal configuration of this device with a focus on a link layer IC (hereinafter referred to as LINK). This device is a physical layer IC (hereinafter referred to as PHY) 1
LINK 2, a microprocessor 3, an ATM signal processing system 4, and a PLL 5.

The PHY 1 initializes the bus, arbitrates the right to use, and the like. In addition, data (data) such as ATM cells and various control signals (control) are communicated with the LINK 2 and these data and control signals are transmitted to the 1394.
Send to and receive from the cable. Further, a system clock (sysclk) is supplied to LINK2. LINK
Details of 2 will be described later. Microprocessor 3 is a PHY
1 and LINK2, and acquires a band for isochronous communication. The ATM signal processing system 4 receives ATM data from a terminal connected to an ATM network existing outside the STB, and generates and decomposes ATM cells. Or AT
The ATM cells directly input from the M network are transmitted to the ATM signal processing interface 12. Further, the basic frequency clock 8 kHz provided in the ATM network is supplied to an 8 kHz cycle control circuit 16 described later. PLL5 is 13
The clock signal (clk) of the sending device is reproduced from the timing information (time stamp information) from the source packet header attached to the ATM cell received via the 94 cable. This timing information is extracted from the source packet header of the data received from the 1394 cable by the header removal and synchronization information restoration circuit 15. Note that the PLL 5 is configured to generate a clock by itself when timing information is not received via a 1394 cable. Then, this clock signal is supplied to the LINK 2 and the ATM signal processing system 4.

The inside of LINK2 is an isochronous system,
They are roughly divided into asynchronous systems and basic blocks. The isochronous system is a block that performs generation and analysis of an isochronous packet carrying ATM cell data.
The asynchronous system is a block for generating and analyzing an asynchronous packet carrying a control signal such as a command for controlling a device.

The asynchronous system comprises a microprocessor interface 6, a control register 7, an asynchronous packet transmission FIFO 8, an asynchronous packet reception FIFO 9, and a self ID packet processing block 10.

The basic block 11 includes a clock 111, a CR
C, a physical layer interface, a transmission block, a reception block, and the like (not shown except for the clock 111).

The isochronous system includes an ATM signal processing interface 12 and an isochronous packet transmission / reception F
It comprises an IFO 13, a header and synchronization information addition circuit 14, a header removal and synchronization information restoration circuit 15, an 8 kHz cycle control circuit 16, an MPEG-TS processing interface 17, and a switching unit 18.

Microprocessor interface 6
Transmits and receives data to and from the microprocessor 3 in response to a request from an upper layer.

Data is written into the control register 7 at a predetermined position by the microprocessor 3,
The operation of INK2 is controlled. When transmitting and receiving an asynchronous packet, it is performed by reading and writing a predetermined address. Further, a part of the header of the isochronous packet is transmitted and received using the control register 7. For example, the SID in the CIP header described above is supplied from the basic block 11 to the control register 7, and the control register 7 transfers the information of the source node ID to the microprocessor 3 via the microprocessor interface 6. In this way, the information of the source node of the transmission source can be recognized by the device (STB) without being removed by the header removal and synchronization information restoration circuit 15.

A packet created by the microprocessor 3 is temporarily stored in the asynchronous packet transmission FIFO 8. The stored packets are read by the basic block 11 as soon as the bus is free.

The asynchronous packet reception FIFO 9 stores the packet fetched from the bus in the basic block 11.
Is written. The microprocessor 3 uses this FI
After confirming that the FO is not empty, reading is performed.

The self-ID packet processing block 10 processes node information received during the bus initialization process, and determines the number of nodes connected to the bus and which node manages the isochronous channel of the bus. Etc. are detected.

The physical layer interface of the basic block 11 performs parallel / serial conversion of transmission data and serial / parallel conversion of reception data. The transmission block determines the status of the bus and controls transmission of packets. Then, the receiving block determines a write destination according to the type of the received packet (asynchronous or isochronous).

The ATM signal processing interface 12
At the time of transmission, the data of the ATM signal processing system 4 is converted into an isochronous packet format by performing the above-described padding processing, and at the time of reception, the reverse processing, that is, the padded bytes are removed.

Isochronous packet transmission / reception FIFO1
Reference numeral 3 denotes a FIFO that performs both transmission and reception of isochronous packets. At the time of transmission, as described above, the ATM cell (FIG. 1A) received from the ATM network is transmitted to the F through the ATM signal processing system 4 and the ATM signal processing interface 12.
Write to IFO13. 125 on 1394 cable
There is a cycle start packet flowing in a cycle of μs. At this timing and at the stage when the transmission is permitted, the basic block 11 transmits the ATM cell waiting in the FIFO 13 onto the 1394 serial bus. In this case, the process of adding the header in the header and synchronization information adding circuit 14 is performed instantaneously, so that there is no problem in terms of time.

As described above, the buffering of the ATM cell is performed by waiting the ATM cell in the FIFO 13, thereby improving the jitter of the ATM cell. Generally, at the source of the ATM cell, the jitter is about 2 msec, so that the buffering by the FIFO is important. Even if the source of the ATM cell is transmitting the cell at a constant cell rate, the transmission time of the cell is delayed every time it passes through several ATM switches.
The time interval between TM cells fluctuates greatly. For this reason, if it is assumed that a plurality of ATM cells are continuously transmitted, a case may occur in which the cycle cannot be completed. Therefore, a source packet header is added one cell at a time (FIG. 1 (b)).
A CIP header and a 1394 isochronous packet header are appropriately added to cells output according to the cycle on the 1394 serial bus (FIG. 1C,
(D)), and send it to the 1394 serial bus.

When transmitting / receiving a signal of the MPEG-TS system, communication is performed with an external device (not shown) via the MPEG-TS processing interface 17. In this case, the switching unit 18
Choose a route via. When an MPEG-TS signal is input via a 1394 cable, the header removal / synchronization information restoration circuit 15 detects the identification data included in the header, and the switching unit 18 is controlled based on the detection. In the case of the MPEG-TS system, the source is relatively constant (jitter of about 200 μsec) and thus does not have as much jitter as the ATM cell. Since a time lag occurs in the transmission system, the FIFO 13 also serves to absorb the time lag.

As described above, by performing buffering before transmitting the data to the 1394 serial bus and adjusting the cell rate to be constant, jitter can be improved.

PHY received from 1394 serial bus
1. The isochronous packet obtained through the basic block 11 is subjected to header removal and synchronization
After the TM cell configuration, the isochronous packet transmission / reception FIFO 13 is written in a range where the FIFO does not overflow. For the written ATM cell, the timing of output from the LINK 2 to the ATM signal processing system 4 is created by the clock signal reproduced by the PLL 5 based on the timing information in the header separated by the header removal and synchronization information restoration circuit 15 in the header removal. Is done.

The header and synchronization information adding circuit 14 adds the source packet header C shown in FIGS. 2 and 3 to the cell read from the isochronous packet transmission / reception FIFO.
An IP header and a 1394 isochronous packet header are added. At this time, a time stamp is given by referring to the value of the clock 111 in the basic block 11 and setting a cycle count and a cycle offset in the source packet header. The clock 111 is adjusted based on the time information in the cycle start packet from the cycle master, and is counted up by the 8 kHz cycle control circuit 16.

The header removal and synchronization information restoration circuit 15
From the isochronous packet received from the basic block 11, the 1394 isochronous packet header, CI
After removing the P header and the source packet header, only the cell is used for isochronous packet transmission / reception FIFO.
Write 13

8 kHz cycle control circuit 16
Converts the 8 kHz signal provided by the ATM network to 13
8kHz (125μsec) in 94 serial bus
Synchronize with the signal. That is, by obtaining the timing of 8 kHz from the ATM network through the ATM signal processing system 4 and synchronizing the signal of 8 kHz of the cycle start packet obtained through the basic block 11, the ATM cell becomes I / O.
It can be handled on EEE1394.

[0047]

As described above in detail, according to the present invention, it is possible to place an ATM cell on a 1394 serial bus for communication.

[Brief description of the drawings]

FIG. 1 is a diagram showing processing until an ATM cell is placed on a 1394 serial bus.

FIG. 2 is a diagram showing an example of the structure of an isochronous packet placed on a 1394 serial bus in FIG.

FIG. 3 is a diagram showing contents from a 1394 isochronous packet header to a cell header in FIG. 2;

FIG. 4 is a diagram showing another example of the structure of the isochronous packet put on the 1394 serial bus in FIG.

FIG. 5 is a block diagram illustrating a configuration of a device that performs processing for placing ATM cells on a 1394 serial bus.

FIG. 6 is a diagram showing a structure of an ATM cell.

[Explanation of symbols]

1 PHY, 2 LINK, 4 ATM signal processing system, 1
2 ... ATM signal processing interface, 13 ... Isochronous packet transmission / reception FIFO, 14 ... Header, synchronization information adding circuit

Claims (15)

[Claims] 1. A data transmission method for transmitting data over a serial bus conforming to the IEEE 1394 format, wherein an ATM cell used in an ATM network uses an isochronous packet configuration defined in the IEEE 1394 format. A data transmission method characterized in that a predetermined header is added so as to transmit the data. 2. When mapping the ATM cell to a source packet larger than the byte length of the ATM cell,
2. The data transmission method according to claim 1, wherein a difference byte is added as padding to the beginning or end of the TM cell. 3. The ATM cell has a 48-byte-long payload and a 5-byte-length ATM added to the ATM cell.
When mapping this to the source packet having a length of 56 bytes, a 3 byte difference is added as padding at the beginning of the ATM cell header or at the end of the payload to form an ATM source packet. 3. The data transmission method according to claim 2, wherein: 4. The system according to claim 1, wherein the predetermined header added to the ATM cell includes a source packet header, and the structure of the source packet header is similar to a transport stream defined by the MPEG system. Data transmission method. 5. The data transmission method according to claim 4, wherein said source packet header includes cycle count data and cycle offset data. 6. A data transmission apparatus for transmitting data via a serial bus conforming to the IEEE 1394 format, wherein an ATM cell used in an ATM network is stored in a data field of an isochronous packet defined in the IEEE 1394 format. A data transmission device having an additional circuit for adding a predetermined header to store the data in the data transmission device. 7. A buffer for buffering said ATM cells, said buffer comprising said IEEE139
7. The data transmission device according to claim 6, wherein jitter generated when the ATM cell is transmitted to a serial bus conforming to four formats is improved. 8. 8k provided in an ATM system network
7. The data transmission device according to claim 6, further comprising means for synchronizing a signal of Hz with a signal of 8 kHz on a 1394 serial bus. 9. A data receiving method for receiving an ATM cell used for an ATM system network transmitted by a serial bus conforming to the IEEE 1394 format, wherein the data field of an isochronous packet defined in the IEEE 1394 format is included. A data receiving method, wherein a predetermined header is removed in order to obtain the ATM cell stored in the data receiving device. 10. The method according to claim 9, wherein a difference byte added to the beginning or end of said ATM cell is removed in order to obtain an ATM cell mapped to a source packet larger than the byte length of said ATM cell. Data reception method described. 11. The ATM source packet mapped to the 56-byte long source packet is used for the AT
The method of claim 3, wherein a difference of 3 bytes added at the beginning of the M cell header or at the end of the payload is removed to obtain an ATM cell composed of a 48-byte length payload and a 5-byte length ATM cell header. 11. The data receiving method according to item 10. 12. The method according to claim 9, wherein the predetermined header removed from the ATM source packet includes a source packet header, and the structure of the source packet header is similar to a transport stream defined by the MPEG system. Data reception method described. 13. The data receiving method according to claim 12, wherein the source packet header has cycle count data and cycle offset data. 14. A data receiving apparatus for receiving an ATM cell used in an ATM network transmitted by a serial bus conforming to the IEEE 1394 format, comprising: a data field of an isochronous packet defined in the IEEE 1394 format. A data receiving apparatus comprising a removing circuit for removing a predetermined header to obtain the ATM cell stored in the data receiving apparatus. 15. A basic block for communicating with a serial bus conforming to the IEEE 1394 format, an interface for communicating with an ATM network, and an ATM cell received from the serial bus and stored in a data field of an isochronous packet. A removing circuit for removing a predetermined header to obtain an ATM cell received from the ATM network; and an adding circuit for adding a predetermined header to store the ATM cell in the data field of the isochronous packet. An integrated circuit for a link layer, comprising: a circuit, a buffer provided between the interface and the interface for adjusting a rate.