JPH10190159A - Printing substrate, circuit board-connecting material using the substrate, and manufacture of multilayered circuit board using the connection material - Google Patents
Printing substrate, circuit board-connecting material using the substrate, and manufacture of multilayered circuit board using the connection materialInfo
- Publication number
- JPH10190159A JPH10190159A JP34396696A JP34396696A JPH10190159A JP H10190159 A JPH10190159 A JP H10190159A JP 34396696 A JP34396696 A JP 34396696A JP 34396696 A JP34396696 A JP 34396696A JP H10190159 A JPH10190159 A JP H10190159A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printing
- mask film
- film
- composition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 239000000463 material Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000203 mixture Substances 0.000 claims abstract description 73
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 19
- 229920003002 synthetic resin Polymers 0.000 claims abstract description 12
- 239000000057 synthetic resin Substances 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 230000003746 surface roughness Effects 0.000 claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 31
- -1 polyethylene terephthalate Polymers 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229920000647 polyepoxide Polymers 0.000 claims description 7
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 5
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- 239000011888 foil Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 4
- 239000004743 Polypropylene Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 229920001155 polypropylene Polymers 0.000 claims description 3
- 239000000843 powder Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000004925 Acrylic resin Substances 0.000 claims description 2
- 229920000178 Acrylic resin Polymers 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 239000002245 particle Substances 0.000 claims description 2
- 239000005011 phenolic resin Substances 0.000 claims description 2
- 239000009719 polyimide resin Substances 0.000 claims description 2
- 238000012545 processing Methods 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 125000001153 fluoro group Chemical group F* 0.000 claims 1
- 239000006082 mold release agent Substances 0.000 abstract 1
- 238000012360 testing method Methods 0.000 description 28
- 238000000034 method Methods 0.000 description 26
- 239000011889 copper foil Substances 0.000 description 22
- 230000000052 comparative effect Effects 0.000 description 17
- 239000003921 oil Substances 0.000 description 13
- 239000004593 Epoxy Substances 0.000 description 11
- 239000011521 glass Substances 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 10
- 239000004020 conductor Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 238000007790 scraping Methods 0.000 description 5
- 239000004745 nonwoven fabric Substances 0.000 description 4
- 239000004760 aramid Substances 0.000 description 3
- 229920003235 aromatic polyamide Polymers 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 239000000835 fiber Substances 0.000 description 3
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- PXKLMJQFEQBVLD-UHFFFAOYSA-N bisphenol F Chemical compound C1=CC(O)=CC=C1CC1=CC=C(O)C=C1 PXKLMJQFEQBVLD-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000002759 woven fabric Substances 0.000 description 2
- HMUNWXXNJPVALC-UHFFFAOYSA-N 1-[4-[2-(2,3-dihydro-1H-inden-2-ylamino)pyrimidin-5-yl]piperazin-1-yl]-2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethanone Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)N1CCN(CC1)C(CN1CC2=C(CC1)NN=N2)=O HMUNWXXNJPVALC-UHFFFAOYSA-N 0.000 description 1
- LDXJRKWFNNFDSA-UHFFFAOYSA-N 2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)-1-[4-[2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidin-5-yl]piperazin-1-yl]ethanone Chemical compound C1CN(CC2=NNN=C21)CC(=O)N3CCN(CC3)C4=CN=C(N=C4)NCC5=CC(=CC=C5)OC(F)(F)F LDXJRKWFNNFDSA-UHFFFAOYSA-N 0.000 description 1
- WZFUQSJFWNHZHM-UHFFFAOYSA-N 2-[4-[2-(2,3-dihydro-1H-inden-2-ylamino)pyrimidin-5-yl]piperazin-1-yl]-1-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethanone Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)N1CCN(CC1)CC(=O)N1CC2=C(CC1)NN=N2 WZFUQSJFWNHZHM-UHFFFAOYSA-N 0.000 description 1
- 229920002799 BoPET Polymers 0.000 description 1
- 229920000271 Kevlar® Polymers 0.000 description 1
- NIPNSKYNPDTRPC-UHFFFAOYSA-N N-[2-oxo-2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 NIPNSKYNPDTRPC-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000003490 calendering Methods 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 239000011162 core material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000539 dimer Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000004761 kevlar Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000003578 releasing effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000011342 resin composition Substances 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
Landscapes
- Structure Of Printed Boards (AREA)
- Screen Printers (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、貫通孔、即ちバイ
アホール(以下、バイアという)を備えた回路基板(プ
リント配線板)にペースト状組成物を印刷し、又は充填
するための印刷基材に関する。さらに、この印刷基材を
用いた回路基板接続材とこれを用いた多層回路基板の製
造方法にも関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed substrate for printing or filling a paste-like composition on a circuit board (printed wiring board) having through holes, ie, via holes (hereinafter referred to as "vias"). About. Further, the present invention relates to a circuit board connecting material using the printed base material and a method for manufacturing a multilayer circuit board using the same.
【0002】[0002]
【従来の技術】近年、電子機器の高性能化及び小型化に
伴い、回路基板の多層化及び高密度化が求められてい
る。IC等の電子部品間の電気接続を最短距離で行うこ
とができる基板の層間の接続方式としてインナーバイア
ホール接続方式が知られており、これによって多層基板
の高密度化が図れる。2. Description of the Related Art In recent years, as electronic devices have become higher in performance and smaller in size, circuit boards have been required to have more layers and higher densities. An inner via-hole connection method is known as a connection method between layers of a substrate that enables electrical connection between electronic components such as ICs to be performed in the shortest distance, and thereby, it is possible to increase the density of a multilayer substrate.
【0003】インナーバイアホール接続方式を用いた多
層基板は、ペースト状導電性組成物をバイアに充填した
プリプレグ等の回路基板接続材を一対のパターン形成用
の銅箔、又は、予めパターン形成されたコア材により挟
持し、加熱加圧することによって製造される。A multilayer substrate using an inner via-hole connection method is a method in which a circuit board connection material such as a prepreg in which a paste-like conductive composition is filled into vias is formed of a pair of copper foils for pattern formation or a pattern formed in advance. It is manufactured by holding and pressing under a core material.
【0004】ペースト状導電性組成物は、エポキシ樹脂
等の合成樹脂バインダーに銅粉等の導電性フィラーを分
散させたものが用いられる。回路基板接続材に設けられ
たバイアに、印刷等の方法を用いてペースト状導電性組
成物が充填される。この印刷工程において、導電性組成
物は表面にPET等のフィルムを備えた回路基板接続材
に直接印刷され、バイアに充填される。この際、フィル
ムが使い捨てのマスクの役割を担うことになる。As the paste-like conductive composition, a paste in which a conductive filler such as copper powder is dispersed in a synthetic resin binder such as an epoxy resin is used. Vias provided in the circuit board connecting member are filled with the paste-like conductive composition by a method such as printing. In this printing step, the conductive composition is directly printed on a circuit board connecting member provided with a film such as PET on the surface, and is filled in a via. At this time, the film plays a role of a disposable mask.
【0005】印刷による充填の後、印刷基材のマスクフ
ィルム上に残った組成物はスキージによって掻き取ら
れ、次の印刷基材の印刷・充填に用いられる。このと
き、通常のPETフィルムをマスクフィルムとして用い
ると、樹脂成分の多い組成物の掻き取り残しが発生す
る。After filling by printing, the composition remaining on the mask film of the printing substrate is scraped off by a squeegee and used for printing and filling the next printing substrate. At this time, if a normal PET film is used as the mask film, the composition containing a large amount of the resin component is left unscrewed.
【0006】印刷工程において、組成物の粘度は重要な
パラメータであり、最適な値にコントロールする必要が
ある。しかし、組成物の粘度が最初は適切な値にコント
ロールされていても、マスクフィルム上に樹脂成分の多
い組成物の掻き取り残しが発生すると、印刷回数を重ね
る度に組成物の粘度が高くなり、ついには印刷できなく
なってしまう。In the printing process, the viscosity of the composition is an important parameter and needs to be controlled to an optimum value. However, even if the viscosity of the composition is initially controlled to an appropriate value, if a scraping residue of the composition with a high resin component occurs on the mask film, the viscosity of the composition increases each time the printing is repeated, Eventually you will not be able to print.
【0007】[0007]
【発明が解決しようとする課題】上記のように、マスク
フィルム上の組成物の掻き取り残しが多くなると、すぐ
に組成物の粘度が高くなるので、頻繁に組成物を新しい
ものに交換する必要がある。このことは、製造コスト上
昇の一因となる。また、印刷できない程度に粘度が高く
なった組成物は廃棄されるが、この廃棄量が増えること
は地球環境の面から好ましくない。As described above, when the composition is left unscrewed on the mask film, the viscosity of the composition immediately increases, so that it is necessary to frequently replace the composition with a new composition. is there. This contributes to an increase in manufacturing cost. Further, the composition whose viscosity has been increased to such an extent that it cannot be printed is discarded. However, it is not preferable from the viewpoint of the global environment that the discarded amount increases.
【0008】以上のような理由から、マスクフィルム上
の組成物の掻き取り性を向上して連続印刷時の組成物の
粘度上昇を抑えること、すなわち、ペースト状組成物の
印刷可能回数を向上することが望まれている。For the reasons described above, the scraping property of the composition on the mask film is improved to suppress the increase in the viscosity of the composition during continuous printing, that is, the number of times the paste composition can be printed is improved. It is desired.
【0009】そこで、本発明の目的は、ペースト状組成
物の印刷可能回数を向上させることができる印刷基材を
提供することにある。また、その印刷基材を用いた回路
基板接続材と、これを用いた多層回路基板の製造方法を
提供することも本発明の目的である。Accordingly, an object of the present invention is to provide a printing substrate capable of improving the number of printable times of the paste composition. It is also an object of the present invention to provide a circuit board connecting material using the printed base material and a method for manufacturing a multilayer circuit board using the same.
【0010】[0010]
【課題を解決するための手段】本発明による印刷基材の
第1の構成は、ペースト状組成物を充填し、又は印刷す
る工程に用いられる多層構造の印刷基材であって、最外
層のうちの少なくとも一方がマスクフィルムの役割を担
い、前記マスクフィルムの外側が離型性を有しているこ
とを特徴とする。According to a first aspect of the present invention, there is provided a printing base material having a multilayer structure used in a step of filling or printing a paste-like composition, wherein the printing base material has an outermost layer. At least one of them plays a role of a mask film, and the outside of the mask film has a releasing property.
【0011】マスクフィルムの外面が離型性を有するこ
とにより、ペースト状組成物が付着しにくく、スキージ
によって容易に掻き取られる。したがって、ペースト状
組成物の樹脂成分が印刷基材上に残らず、ペースト状組
成物の繰返し使用可能回数(印刷可能回数)が向上す
る。Since the outer surface of the mask film has a releasability, the paste-like composition hardly adheres and is easily scraped off by a squeegee. Therefore, the resin component of the paste composition does not remain on the printing substrate, and the number of times the paste composition can be used repeatedly (the number of times that the paste composition can be printed) is improved.
【0012】マスクフィルムの外面に離型性を持たせる
には、例えば、マスクフィルムを合成樹脂フィルムとそ
の上に塗布された離型剤とで構成すればよい。この合成
樹脂製マスクフィルムの上に塗布する離型剤として、一
般に使用されているシリコン系又はフッ素系の離型剤を
用いることができる。In order to make the outer surface of the mask film have releasability, for example, the mask film may be composed of a synthetic resin film and a release agent applied thereon. As the release agent applied on the synthetic resin mask film, a generally used silicon-based or fluorine-based release agent can be used.
【0013】また、本発明による印刷基材の第2の構成
は、ペースト状組成物を充填し、又は印刷する工程に用
いられる多層構造の印刷基材であって、最外層のうちの
少なくとも一方がマスクフィルムの役割を担い、前記マ
スクフィルムの外側の表面粗さが100nm以下である
ことを特徴とする。表面粗さが100nm以下のフィル
ムをマスクフィルムとして用いることにより、ペースト
状組成物を掻き取る際にスキージと表面との隙間が小さ
くなり、ペースト組成物の掻き取り残しがほとんど無く
なる。A second configuration of the printing substrate according to the present invention is a multi-layered printing substrate used in the step of filling or printing the paste-like composition, wherein at least one of the outermost layers is used. Plays the role of a mask film, and the outer surface roughness of the mask film is 100 nm or less. By using a film having a surface roughness of 100 nm or less as a mask film, a gap between the squeegee and the surface is reduced when the paste-like composition is scraped off, and almost no scraping residue of the paste composition is left.
【0014】さらに、本発明による印刷基材の第3の構
成は、ペースト状組成物を充填し、又は印刷する工程に
用いられる多層構造の印刷基材であって、最外層のうち
の少なくとも一方がマスクフィルムの役割を担い、前記
マスクフィルムの弾性率が300kgf/mm2以上で
あることを特徴とする。弾性率が300kgf/mm2
以上であるフィルムをマスクフィルムとして用いること
により、表面が多少粗い印刷基材であっても、マスクフ
ィルムの表面は比較的平坦になり、スキージによるペー
スト組成物の掻き取り性が良好になる。Further, a third configuration of the printing base material according to the present invention is a multi-layered printing base material used in a step of filling or printing the paste-like composition, wherein at least one of the outermost layers is used. Plays a role of a mask film, and the elastic modulus of the mask film is 300 kgf / mm 2 or more. The elastic modulus is 300 kgf / mm 2
By using the above film as a mask film, the surface of the mask film becomes relatively flat even if the printing substrate has a somewhat rough surface, and the paste composition can be scraped off with a squeegee.
【0015】上記の各構成において、マスクフィルムが
合成樹脂フィルムからなることが好ましい。例えば、ポ
リエチレンテレフタレートフィルム又はポリプロピレン
フィルムを用いることができる。In each of the above structures, the mask film is preferably made of a synthetic resin film. For example, a polyethylene terephthalate film or a polypropylene film can be used.
【0016】また、本発明による回路基板接続材は、上
記のような印刷基材の所定位置に貫通孔が設けられ、前
記貫通孔に導電性組成物が充填されたものである。つま
り、印刷基材そのものが多層基板を構成する回路基板接
続材(絶縁層)として用いられる。これによって多層基
板の導体層間の良好な電気接続を得ながら、多層基板を
効率的に製造することができる。Further, the circuit board connecting material according to the present invention is such that a through-hole is provided at a predetermined position of the above-mentioned printing substrate, and the through-hole is filled with a conductive composition. That is, the printing base material itself is used as a circuit board connecting material (insulating layer) constituting the multilayer board. Thus, the multilayer board can be efficiently manufactured while obtaining good electrical connection between the conductor layers of the multilayer board.
【0017】この導電性組成物は、平均粒径が0.5〜
20μmの金、銀、ニッケル、銅、パラジウム、及びこ
れらの合金から選ばれる少なくとも1つの金属粉末80
〜92重量%と、エポキシ樹脂、フェノール樹脂、ポリ
イミド樹脂及びアクリル樹脂から選ばれる少なくとも1
つの合成樹脂4.5〜20重量%を含んでいることが好
ましい。The conductive composition has an average particle size of 0.5 to 0.5.
20 μm of at least one metal powder 80 selected from gold, silver, nickel, copper, palladium and alloys thereof
To 92% by weight and at least one selected from an epoxy resin, a phenol resin, a polyimide resin and an acrylic resin.
It preferably contains 4.5 to 20% by weight of one synthetic resin.
【0018】本発明による多層回路基板の製造方法の一
つは、少なくとも2層以上の回路パターンを有する回路
基板と、少なくとも1層以上の回路パターンを有する回
路基板との間に、上記の回路基板接続材からマスクフィ
ルムを取り除いたものを挟み、得られた積層体を加熱加
圧する工程を備えている。また、本発明による多層回路
基板の別の製造方法は、少なくとも2層以上の回路パタ
ーンを有する回路基板の両面に、上記の回路基板接続材
のマスクフィルムを取り除いたものを重ね、さらにその
両面に金属箔を張り付け、得られた積層体を加熱加圧し
た後、前記金属箔を加工して回路パターンを形成する工
程を備えている。このような製造方法によって、導電層
間の電気接続の信頼性が高い多層回路基板を効率的に製
造することができる。One of the methods for manufacturing a multilayer circuit board according to the present invention is a method for manufacturing a multilayer circuit board, comprising the steps of: providing a circuit board having at least two circuit patterns and a circuit board having at least one circuit pattern; The method includes a step of sandwiching the connection material from which the mask film has been removed, and heating and pressing the obtained laminate. Further, another method for manufacturing a multilayer circuit board according to the present invention is a method of manufacturing a multilayer circuit board, wherein the circuit board having at least two layers or more of circuit patterns is overlapped on both sides of the circuit board with the mask film of the circuit board connecting material removed, and further on both sides. After attaching a metal foil, heating and pressing the obtained laminated body, the method includes processing the metal foil to form a circuit pattern. With such a manufacturing method, a multilayer circuit board having high reliability of electrical connection between conductive layers can be efficiently manufactured.
【0019】[0019]
【発明の実施の形態】以下、本発明の実施形態をいくつ
かの実施例に従って具体的に説明する。まず、各実施例
で用いたペースト状組成物、プリプレグ、銅箔、及びマ
スクフィルムについて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be specifically described below with reference to some examples. First, the paste composition, prepreg, copper foil, and mask film used in each example will be described.
【0020】(A)ペースト状組成物 各実施例において、銅粉87.5重量%、ビスフェノー
ルF3.0重量%、ダイマー酸をグリシジルエステル化
したエポキシ樹脂7.0重量%およびアミンアダクト型
硬化剤2.5重量%からなるペースト状導電性組成物を
用いた。もっとも、本発明の印刷基材に用いられるペー
スト状組成物は、このような特定のペースト状導電性組
成物に限られず、ペースト状抵抗体組成物、ペースト状
絶縁性組成物、ペースト状熱伝導性組成物等、アプリケ
ーションに応じて種々のペースト状組成物を用いること
ができる。又、本発明の回路基板接続材と、これを用い
た多層回路基板の製造方法に用いられるペースト状導電
性組成物についても、上記のような特定のペースト状導
電性樹脂組成物に限られず、導電性粉末をフィラーとし
て含有し、有機又は無機材料をバインダーとして用いた
所望の電気特性を有するペースト状組成物を用いること
ができる。(A) Paste composition In each of the examples, 87.5% by weight of copper powder, 3.0% by weight of bisphenol F, 7.0% by weight of glycidyl-esterified epoxy resin of dimer acid and 7.0% by weight of amine adduct type curing agent A paste-like conductive composition consisting of 2.5% by weight was used. However, the paste-like composition used for the printing substrate of the present invention is not limited to such a specific paste-like conductive composition, but also includes a paste-like resistor composition, a paste-like insulating composition, and a paste-like heat conductive composition. Various paste compositions can be used depending on the application, such as a volatile composition. Further, the circuit board connecting material of the present invention, the paste-like conductive composition used in the method for manufacturing a multilayer circuit board using the same is not limited to the specific paste-like conductive resin composition as described above, A paste composition containing conductive powder as a filler and using organic or inorganic materials as a binder and having desired electric characteristics can be used.
【0021】(B)プリプレグ 各実施例において、デュポン社製の「ケブラー」を用い
た不織布にエポキシ樹脂を含浸させたアラミド(芳香族
アラミド)エポキシ不織布シートを用いた。上記の不織
布は、繊維強度2.2デニール、繊維長6mmの繊維を
用いて湿式法により作製される。抄紙後、温度300
℃、圧力200kg/cm2の条件でカレンダ処理を行
った後、250℃で10分間加熱処理し、目付70g/
m2、厚さ100μmの不織布を得る。もっとも、本発
明は、このような特定のプリプレグだけでなく、ガラス
エポキシプリプレグ等の一般のプリプレグ、ポリイミド
シート等の合成樹脂シート、又はセラミック基板といっ
た種々の基材にペースト状組成物を充填し又は印刷する
工程に適用することができる。(B) Prepreg In each of the examples, an aramid (aromatic aramid) epoxy nonwoven fabric sheet was used in which a nonwoven fabric made of “Kevlar” manufactured by DuPont was impregnated with an epoxy resin. The above nonwoven fabric is produced by a wet method using fibers having a fiber strength of 2.2 denier and a fiber length of 6 mm. After paper making, temperature 300
After performing a calendaring process under the conditions of a temperature of 200 ° C. and a pressure of 200 kg / cm 2, a heating process was performed at 250 ° C. for 10 minutes to obtain a basis weight of 70 g / cm 2.
A nonwoven fabric having a thickness of m 2 and a thickness of 100 μm is obtained. However, the present invention is not limited to such a specific prepreg, a general prepreg such as a glass epoxy prepreg, a synthetic resin sheet such as a polyimide sheet, or a base material such as a ceramic substrate filled with the paste composition or It can be applied to a printing process.
【0022】(C)銅箔 各実施例で作製した多層回路基板の導体層として銅箔を
用いた。厚さ9〜70μmの電解銅箔が一般的である
が、これに限定されるわけではない。(C) Copper Foil Copper foil was used as the conductor layer of the multilayer circuit board produced in each of the examples. An electrolytic copper foil having a thickness of 9 to 70 μm is generally used, but is not limited to this.
【0023】(D)マスクフィルム 各実施例において、マスクフィルムとしてポリエチレン
テレフタレート(PET)フィルム及びポリプロピレン
フィルムを用いた。但し、本発明の実施に際して、これ
らの特定のマスクフィルムに限らず、例えば、ポリイミ
ド、ポリエチレン等の一般の合成樹脂フィルム、又はス
テンレス等の金属フィルムを用いることもできる。又、
マスクフィルムの表面に塗布する離型剤として、シリコ
ン系離型剤及びフッ素系離型剤を用いた。但し、本発明
の実施に際し、これらの特定の離型剤に限らず、他の種
類の離型剤をマスクフィルムの表面に塗布してもよい。
これらの複数種類のマスクフィルム及び離型剤の組み合
わせ、さらに複数段階の表面粗さの組み合わせによっ
て、各実施例において、例えば表1に示すように、比較
例を含む複数のサブ実施例の組み合わせができる。(D) Mask Film In each of the examples, a polyethylene terephthalate (PET) film and a polypropylene film were used as mask films. However, the present invention is not limited to these specific mask films and may be, for example, a general synthetic resin film such as polyimide or polyethylene, or a metal film such as stainless steel. or,
As the release agent applied to the surface of the mask film, a silicon release agent and a fluorine release agent were used. However, in practicing the present invention, not only these specific release agents but also other types of release agents may be applied to the surface of the mask film.
In each of the examples, a combination of a plurality of sub-examples including a comparative example, as shown in Table 1, for example, by a combination of these plural types of mask films and release agents, and a combination of a plurality of levels of surface roughness it can.
【0024】(実施例1)本発明の第1の実施例とし
て、図1に示すように、縦240mm、横240mmの
プリプレグ102の両面に、表1に示すような各種のマ
スクフィルム101を熱圧着により張り付け、炭酸ガス
レーザーで直径150μmのバイア(貫通孔)103を
あけて印刷基材を作製した。導電性組成物は粘度200
Pa・sのものを100gずつ投入した。印刷基材を印
刷機のテーブル上に設置し、導電性組成物をマスクフィ
ルム上に印刷してバイアに充填した。図1中、104が
バイアに充填された導電性組成物である。Embodiment 1 As a first embodiment of the present invention, as shown in FIG. 1, various mask films 101 as shown in Table 1 are thermally applied on both sides of a prepreg 102 having a length of 240 mm and a width of 240 mm. The printed substrate was produced by bonding by press bonding and opening a via (through hole) 103 having a diameter of 150 μm with a carbon dioxide laser. The conductive composition has a viscosity of 200
100 g of Pa · s were charged. The printing substrate was placed on a table of a printing machine, and the conductive composition was printed on a mask film and filled into vias. In FIG. 1, reference numeral 104 denotes a conductive composition filled in vias.
【0025】繰返し印刷可能回数を評価するために、マ
スクフィルム上の導電性組成物の掻き取り残しの状態、
導電性組成物のバイアへの充填状態をチェックすると共
に、E型粘度計を用いて印刷前と印刷後の粘度を25
℃、0.5rpmで測定した。前述のマスクフィルム、
その表面粗さ、及び離型剤の組み合わせによる複数の実
施例と比較例との評価結果を表1に示す。In order to evaluate the number of times of repetitive printing, the conductive composition on the mask film was left unscrewed,
The filled state of the conductive composition into the via was checked, and the viscosity before printing and the viscosity after printing were measured using an E-type viscometer.
It measured at 0.5 degreeC and 0.5 degreeC. The aforementioned mask film,
Table 1 shows the results of the evaluation of a plurality of examples and comparative examples based on the combination of the surface roughness and the release agent.
【0026】[0026]
【表1】 [Table 1]
【0027】表1は、300枚の印刷基材に導電性組成
物を繰返し印刷・充填した際の300枚目の印刷基材に
関するデータを示している。但し、比較例1−1及び比
較例1−3については、50枚印刷した時点て導電性組
成物の粘度が相当高くなり(比較例1−1は粘度300
0Pa・s以上)、組成物の掻き取り残しが多く発生す
ると共にバイアに充填できなくなってしまった。Table 1 shows data on the 300th printing substrate when the conductive composition was repeatedly printed and filled on 300 printing substrates. However, in Comparative Example 1-1 and Comparative Example 1-3, the viscosity of the conductive composition became considerably high after printing 50 sheets (Comparative Example 1-1 had a viscosity of 300).
0 Pa · s or more), a large amount of unscraped composition was generated, and the vias could not be filled.
【0028】実施例1−1から1−4は2種類のマスク
フィルムと2種類の離型剤との組み合わせによる4通り
の例であり、フィルムは表面粗さRa=200μm、弾
性率E=100kgf/cm2のものを用いた。いずれ
も300枚印刷後も粘度上昇が少なく、組成物の掻き取
り性、バイアへの充填性共に良好であった。Examples 1-1 to 1-4 are four examples by combining two types of mask films and two types of release agents. The films have a surface roughness Ra = 200 μm and an elastic modulus E = 100 kgf. / Cm 2 . In all cases, the increase in viscosity was small even after printing 300 sheets, and both the scraping property of the composition and the filling property into the via were good.
【0029】比較例1−1から1−4、及び実施例1−
5から1−13は、いずれも離型剤は塗布せずに、マス
クフィルムの表面粗さRa又は弾性率Eの一方を変化さ
せたものである。変化させない方の値は、Ra=200
μm、又はE=100kgf/cm2である。マスクフ
ィルムの表面粗さRaを小さくする(100μm以下)
か、マスクフィルムの弾性率Eを大きくする(300k
gf/cm2以上)ことにより、300枚印刷後も粘度
上昇が比較的少なく、組成物の掻き取り性、バイアへの
充填性共に良好になった。Comparative Examples 1-1 to 1-4 and Example 1
In Nos. 5 to 1-13, one of the surface roughness Ra and the elastic modulus E of the mask film was changed without applying any release agent. The value not changed is Ra = 200.
μm or E = 100 kgf / cm 2 . Reduce surface roughness Ra of mask film (100 μm or less)
Alternatively, the elastic modulus E of the mask film is increased (300 k
gf / cm 2 or more), the increase in viscosity was relatively small even after printing 300 sheets, and both the scraping property of the composition and the filling property of the via were improved.
【0030】(実施例2)本発明の第2の実施例とし
て、図2に示すように、実施例1で作製した印刷基材に
導電性組成物を充填した回路基板接続材203を用いて
両面回路基板を作製した。マスクフィルムを剥離した回
路基板接続材203を厚さ35μmの2枚の銅箔205
で挟み(図2(a))、真空中で温度200℃、圧力5
0kg/cm 2の条件で約1時間、加熱加圧した。この
結果、回路基板接続材が硬化すると共に、銅箔が回路基
板接続材に接着された(図2(b))。(Embodiment 2) As a second embodiment of the present invention,
Then, as shown in FIG. 2, the printing base material prepared in Example 1 was used.
Using the circuit board connecting material 203 filled with the conductive composition
A double-sided circuit board was manufactured. Time when the mask film is peeled off
The circuit board connecting member 203 is made of two copper foils 205 having a thickness of 35 μm.
(FIG. 2 (a)), temperature 200 ° C., pressure 5 in vacuum
0kg / cm TwoUnder the conditions described above, heating and pressurization were performed for about 1 hour. this
As a result, the circuit board connection material hardens and the copper foil
It was bonded to the plate connecting material (FIG. 2 (b)).
【0031】次に、公知のフォトリソグラフィー法によ
って両面の銅箔に回路パターン206を形成した(図2
(c))。具体的には、図2(b)の積層板の両面にド
ライフィルムを熱ロールにて張り合わせ、パターンを紫
外線露光して銅箔を残す部分だけ硬化させる。次に未硬
化部分を現像処理で取り除き、塩化銅溶液中でエッチン
グを行う。最後に余分なドライフィルムを剥離して回路
パターン206が形成される。Next, a circuit pattern 206 was formed on the copper foil on both sides by a known photolithography method.
(C)). Specifically, a dry film is stuck on both sides of the laminate of FIG. 2B with a hot roll, and the pattern is exposed to ultraviolet light to cure only the portion where the copper foil remains. Next, the uncured portion is removed by a development process, and etching is performed in a copper chloride solution. Finally, the excess dry film is peeled off to form the circuit pattern 206.
【0032】このようにして、作製された両面回路基板
を、電気導通試験、信頼性試験によって評価した。電気
導通は、バイア1個当たりの接続抵抗を4端子法で測定
した。信頼性試験として、半田リフロー試験とオイルデ
ィップ試験を行い、各試験後に500個のバイアの接続
抵抗と回路パターンの抵抗との総和を4端子法で測定し
た。そして、試験後の測定値から初期抵抗を引いたも
の、つまり、500個分のバイアの抵抗値の変化量を求
めて評価した。The double-sided circuit board thus manufactured was evaluated by an electrical continuity test and a reliability test. The electrical continuity was determined by measuring the connection resistance per via by a four-terminal method. As a reliability test, a solder reflow test and an oil dip test were performed, and after each test, the sum of the connection resistance of 500 vias and the resistance of the circuit pattern was measured by a four-terminal method. Then, the value obtained by subtracting the initial resistance from the measured value after the test, that is, the amount of change in the resistance value of 500 vias was obtained and evaluated.
【0033】半田リフロー試験は、サンプルの両面回路
基板を、温度260℃に加熱した半田リフロー炉中に1
0秒間投入したのち大気中に10分間放置するサイクル
を10回繰り返すことによって実施した。このときの5
00個分のバイアの抵抗値の変化量が250mΩ以下で
あれば良好と判断した。これは、バイア1個当たり0.
5mΩ以下の変化に相当する。In the solder reflow test, the sample double-sided circuit board was placed in a solder reflow furnace heated to a temperature of 260 ° C.
The cycle of charging for 0 seconds and then leaving in the atmosphere for 10 minutes was repeated 10 times. 5 at this time
It was determined to be good if the amount of change in the resistance value of the 00 vias was 250 mΩ or less. This is equivalent to 0 .0 per via.
This corresponds to a change of 5 mΩ or less.
【0034】オイルディップ試験は、サンプルの両面回
路基板を、温度260℃に加熱したオイル中に10秒間
浸したのち、室温での10秒間を経て温度20℃のオイ
ル中に10秒間浸す温度サイクルを200回繰り返すこ
とによって行った。そして、高温側オイルおよび低温側
オイルに浸している時の抵抗を測定し、200回の温度
サイクルの間に断線が発生しないことをチェックすると
共に、試験前後での抵抗変化量を測定した。抵抗変化量
の良否の判断基準は半田リフロー試験と同じである。評
価結果を表2に示す。The oil dip test is a temperature cycle in which a double-sided circuit board of a sample is immersed in oil heated to a temperature of 260 ° C. for 10 seconds, and then immersed in oil at a temperature of 20 ° C. for 10 seconds at room temperature. Performed by repeating 200 times. Then, the resistance when immersed in the high-temperature oil and the low-temperature oil was measured, it was checked that no disconnection occurred during 200 temperature cycles, and the resistance change before and after the test was measured. The criterion for determining the quality of the resistance change is the same as that of the solder reflow test. Table 2 shows the evaluation results.
【0035】[0035]
【表2】 [Table 2]
【0036】表2は、表1(実施例1)に示した各実施
例及び比較例の300枚目の印刷基材(比較例2−1及
び比較例2−3については、50枚目の印刷基材)を用
いて作製した両面回路基板に関するデータを示してい
る。この表から分かるように、比較例2−1から2−4
の基板はいずれもバイア1個当たりの抵抗値が比較的大
きく、半田リフロー試験又はオイルディップ試験後の5
00個分のバイアの抵抗値の変化量が250mΩを越え
ている。中にはオイルディップ試験後に断線に至ったも
のもある。これに対して、実施例2−1から2−13の
基板はいずれもバイア1個当たりの抵抗値が小さく(約
0.37mΩ〜0.48mΩ)、半田リフロー試験又は
オイルディップ試験後の500個分のバイアの抵抗値の
変化量が250mΩ未満であり、良好な結果を示した。Table 2 shows the 300th printing substrate of each of Examples and Comparative Examples shown in Table 1 (Example 1) (for Comparative Example 2-1 and Comparative Example 2-3, the 50th printing substrate). 2 shows data on a double-sided circuit board manufactured using a printed substrate. As can be seen from this table, Comparative Examples 2-1 to 2-4
Each substrate has a relatively large resistance value per via, and has a resistance value of 5% after a solder reflow test or an oil dip test.
The amount of change in the resistance value of the 00 vias exceeds 250 mΩ. Some of them were broken after the oil dip test. On the other hand, the substrates of Examples 2-1 to 2-13 each have a small resistance value per via (about 0.37 mΩ to 0.48 mΩ), and 500 pieces after the solder reflow test or the oil dip test. The change amount of the resistance value of the via per minute was less than 250 mΩ, indicating a good result.
【0037】(実施例3)次に本発明の第3の実施例と
して、実施例1で作製した印刷基材に導電性組成物を充
填した回路基板接続材を用いて多層基板を作製した。本
実施例では、図3に示すように、回路基板接続材303
を二枚の両面回路基板309で挟むことによって多層基
板を作製した。両面回路基板として、ガラスエポキシ基
材のものを用いた。(Example 3) Next, as a third example of the present invention, a multilayer substrate was manufactured using a circuit board connecting material in which the conductive composition was filled into the printing base material manufactured in Example 1. In this embodiment, as shown in FIG.
Was sandwiched between two double-sided circuit boards 309 to produce a multilayer board. A glass epoxy substrate was used as the double-sided circuit board.
【0038】このガラスエポキシ両面基板は次のように
して作製した。まず、ガラス織布にFR−4相当の熱硬
化性樹脂を含浸させたプリプレグ(厚さ約100μm)
を4枚重ね、その両面に厚さ35μmの両面粗化処理し
た銅箔を重ね合わせた。この積層体を真空中で温度17
0℃、圧力40Kg/cm2の条件で約1時間加熱加圧
して基材の硬化と銅箔の接着を行った。このようにして
作製された基板の所定の位置にドリル加工機によって直
径0.6mmの貫通孔(バイア)307をあけ、さらに
銅メッキによってバイア内壁308と表面導体層に銅メ
ッキ皮膜を形成した。この後、フォトリソグラフィー法
によって表面導体層に回路パターン306を形成した。The glass epoxy double-sided board was manufactured as follows. First, a prepreg (about 100 μm thick) in which a glass woven fabric is impregnated with a thermosetting resin equivalent to FR-4.
Were superposed on each other, and a copper foil having a thickness of 35 μm and subjected to a roughening treatment on both surfaces was superposed on both surfaces thereof. The laminated body is heated at a temperature of 17 in vacuum.
Heating and pressurizing was performed for about 1 hour at 0 ° C. and a pressure of 40 kg / cm 2 to cure the substrate and bond the copper foil. A through-hole (via) 307 having a diameter of 0.6 mm was drilled at a predetermined position on the substrate thus manufactured by a drilling machine, and a copper plating film was formed on the inner wall 308 of the via and the surface conductor layer by copper plating. Thereafter, a circuit pattern 306 was formed on the surface conductor layer by photolithography.
【0039】以上のようにして作製された2枚のガラス
エポキシ両面基板309の間に、マスクフィルムを剥離
した回路基板接続材303を位置合わせして挟み、この
積層体を上記と同じ条件で加熱加圧した。このとき、両
面基板の回路パターンの他層と電気接続すべき箇所には
ランドが設けられており、このランドに回路基板接続材
303の導電性組成物304が接触する。そして、両面
基板309のドリル加工によって形成されたバイア部3
07の位置と回路基板接続材の導電性組成物304の位
置とが重ならないようにしている。The circuit board connecting member 303 from which the mask film has been peeled off is positioned and sandwiched between the two glass epoxy double-sided substrates 309 produced as described above, and this laminate is heated under the same conditions as described above. Pressurized. At this time, a land is provided in a portion of the double-sided board to be electrically connected to another layer of the circuit pattern, and the conductive composition 304 of the circuit board connecting member 303 comes into contact with the land. Then, via portion 3 formed by drilling of double-sided substrate 309
07 and the position of the conductive composition 304 of the circuit board connecting member are not overlapped.
【0040】以上のようにして、4層の導体回路層を有
する多層回路基板が作製された。両面基板のバイア部分
307は、回路基板接続材のエポキシ樹脂が流入し、完
全に塞がっていた。この多層回路基板の電気導通試験及
び信頼性試験の結果を表3に示す。As described above, a multilayer circuit board having four conductive circuit layers was manufactured. The via portion 307 of the double-sided board was completely covered by the epoxy resin of the circuit board connecting material. Table 3 shows the results of the electrical continuity test and the reliability test of this multilayer circuit board.
【0041】[0041]
【表3】 [Table 3]
【0042】表3は、表1(実施例1)に示した各実施
例及び比較例の299枚目の印刷基材(比較例3−1及
び比較例3−2については、49枚目の印刷基材)を用
いて作製した多層回路基板に関するデータを示してい
る。この表から分かるように、比較例3−1から3−4
の基板はいずれもバイア1個当たりの抵抗値が比較的大
きく、半田リフロー試験又はオイルディップ試験後の5
00個分のバイアの抵抗値の変化量が250mΩを越え
ているが、実施例3−1から3−13の基板はいずれも
バイア1個当たりの抵抗値が小さく(約0.39mΩ〜
0.50mΩ)、半田リフロー試験又はオイルディップ
試験後の500個分のバイアの抵抗値の変化量も250
mΩ未満であり、良好な結果を示している。Table 3 shows the 299th printing substrate of each of Examples and Comparative Examples shown in Table 1 (Example 1) (for Comparative Example 3-1 and Comparative Example 3-2, the 49th printing substrate). 2 shows data on a multilayer circuit board manufactured using a printed base material. As can be seen from this table, Comparative Examples 3-1 to 3-4
Each substrate has a relatively large resistance value per via, and has a resistance value of 5% after a solder reflow test or an oil dip test.
Although the change in the resistance value of the 00 vias exceeded 250 mΩ, the substrates of Examples 3-1 to 3-13 all had a small resistance value per via (about 0.39 mΩ to
0.50 mΩ), and the change in the resistance value of the 500 vias after the solder reflow test or the oil dip test is also 250.
less than mΩ, indicating good results.
【0043】(実施例4)次に本発明の第4の実施例と
して、実施例1で作製した印刷基材に導電性組成物を充
填した回路基板接続材を用いて、実施例3とは異なる方
法で多層基板を作製した。本実施例では、図4に示すよ
うに、四層回路基板410を二枚の回路基板接続材40
3で挟み、さらのその両面に銅箔405を重ねることに
よって多層基板を製造した。(Example 4) Next, as a fourth example of the present invention, a circuit board connecting material in which the conductive material was filled into the printed base material prepared in Example 1 was used. Multilayer substrates were made by different methods. In this embodiment, as shown in FIG. 4, the four-layer circuit board 410 is
3, and a copper foil 405 was further laminated on both sides to produce a multilayer substrate.
【0044】四層回路基板410はガラスエポキシ基材
を用いて次のように作製した。まず、ガラス織布に熱硬
化性樹脂を含浸させたプリプレグ(厚さ約100μm)
を4枚重ね、さらに厚さ35μmの片面を粗化処理した
銅箔を両面に重ね合わせ、真空中で温度170℃、圧力
40kg/cm2の条件で約1時間加熱加圧して基材の
硬化と銅箔の接着を行った。銅箔の接着の後、フォトリ
ソグラフィー法で回路パターンの形成を行った。具体的
には、ドライフィルムをラミネータを用いて両面に張り
合わせ、パターン露光後、現像、エッチング、ドライフ
ィルム剥離を行う。The four-layer circuit board 410 was manufactured using a glass epoxy substrate as follows. First, a prepreg (thickness: about 100 μm) in which a thermosetting resin is impregnated in a glass woven fabric
Are laminated, and a copper foil having a thickness of 35 μm, which has been roughened on one side, is further laminated on both sides, and is heated and pressed in a vacuum at a temperature of 170 ° C. and a pressure of 40 kg / cm 2 for about 1 hour to cure the substrate. And copper foil were bonded. After bonding the copper foil, a circuit pattern was formed by photolithography. Specifically, a dry film is stuck on both sides using a laminator, and after pattern exposure, development, etching, and dry film peeling are performed.
【0045】次に、回路パターンを形成した基板の銅箔
表面を黒化処理し、さらにその両面にプリプレグを2枚
ずつ重ね、片面粗化銅箔を粗化面を内側にして両面に重
ね、再度加熱加圧処理を行った。この基板の所望の位置
にドリル加工機で直径0.6mmのバイア407を形成
し、さらに銅メッキによってバイア内壁408と外層表
面に銅メッキ皮膜を形成した。この後、フォトリソグラ
フィー法によって外層表面に回路パターンを形成した。Next, the copper foil surface of the substrate on which the circuit pattern was formed was subjected to blackening treatment, and two prepregs were further laminated on both surfaces thereof, and a single-side roughened copper foil was laminated on both surfaces with the roughened surface inside. The heat and pressure treatment was performed again. A via 407 having a diameter of 0.6 mm was formed at a desired position on the substrate by a drilling machine, and a copper plating film was formed on the inner wall 408 of the via and the outer layer surface by copper plating. Thereafter, a circuit pattern was formed on the outer layer surface by photolithography.
【0046】以上のようにして作製されたガラスエポキ
シ4層基板410を中間層として、その両面にマスクフ
ィルムを剥離した回路基板接続材403を位置合わせし
て重ね、さらに、その両外側に片面粗化銅箔405を重
ね、上記と同じ条件で加熱加圧した。このようにして作
製された多層基板の表層銅箔に、上記と同様のフォトリ
ソグラフィー法を用いて回路パターンを形成した。この
とき、4層基板410と表層銅箔405とは導電性組成
物404によって接続され、この導電性組成物404に
対応する回路基板接続材403の位置には電気接続のた
めのランド412が設けられている。そして、4層基板
410のバイア部407の位置と回路基板接続材403
の導電性組成物404の位置部分とが重ならないように
している。Using the glass epoxy four-layer substrate 410 manufactured as described above as an intermediate layer, the circuit board connecting material 403 from which the mask film has been peeled off is aligned and superposed on both surfaces thereof. The copper foil 405 was overlaid and heated and pressed under the same conditions as above. A circuit pattern was formed on the surface copper foil of the multilayer substrate thus manufactured by using the same photolithography method as described above. At this time, the four-layer substrate 410 and the surface copper foil 405 are connected by the conductive composition 404, and a land 412 for electrical connection is provided at a position of the circuit board connecting member 403 corresponding to the conductive composition 404. Have been. Then, the position of the via portion 407 of the four-layer board 410 and the circuit board connecting material 403
Of the conductive composition 404 is not overlapped.
【0047】以上のようにして、6層の導体回路層を有
する多層回路基板が作製された。両面基板のバイア部分
407は、回路基板接続材のエポキシ樹脂が流入して完
全に塞がっている。この多層回路基板の電気導通試験及
び信頼性試験の結果を表4に示す。As described above, a multilayer circuit board having six conductive circuit layers was manufactured. The via portion 407 of the double-sided board is completely closed by the epoxy resin of the circuit board connecting material flowing therein. Table 4 shows the results of the electrical continuity test and the reliability test of this multilayer circuit board.
【0048】[0048]
【表4】 [Table 4]
【0049】表4は、表1(実施例1)に示した各実施
例及び比較例の298枚目及び297枚目の印刷基材
(比較例3−1及び比較例3−2については、48枚目
及び47枚目の印刷基材)を用いた基板に関するデータ
を示している。この表から分かるように、比較例4−1
から4−4の基板はいずれもバイア1個当たりの抵抗値
が比較的大きく、半田リフロー試験又はオイルディップ
試験後の500個分のバイアの抵抗値の変化量が250
mΩを越えているが、実施例4−1から4−13の基板
はいずれもバイア1個当たりの抵抗値が小さく(約0.
44mΩ〜0.55mΩ)、半田リフロー試験又はオイ
ルディップ試験後の500個分のバイアの抵抗値の変化
量も250mΩ未満であり、良好な結果を示している。Table 4 shows the 298-th and 297-th printing substrates (Comparative Examples 3-1 and 3-2 for each of Examples and Comparative Examples shown in Table 1 (Example 1)). The data on the substrates using the 48th and 47th printing substrates) are shown. As can be seen from this table, Comparative Example 4-1
Each of the substrates 4 to 4-4 has a relatively large resistance value per via, and the resistance change amount of the 500 vias after the solder reflow test or the oil dip test is 250.
Although it exceeds mΩ, the substrates of Examples 4-1 to 4-13 all have a small resistance value per via (about 0.
44 mΩ to 0.55 mΩ), and the amount of change in the resistance value of the 500 vias after the solder reflow test or the oil dip test is less than 250 mΩ, indicating a good result.
【0050】この実施例では6層の多層回路基板を作製
したが、前述の工程を必要な回数だけ繰り返すことによ
り、さらに積層数の多い多層基板を作製することができ
る。この実施例の多層回路基板の製造方法は、検査済み
の完成した多層回路基板と回路基板接続材を積層するの
で、高い製造歩留まりが得られ、コスト上昇が抑えられ
るといった効果を奏する。また、本実施例の製造方法で
は、積層数の多い多層基板を比較的容易に作製すること
ができる。In this embodiment, a multilayer circuit board having six layers is manufactured. However, by repeating the above-described steps as many times as necessary, a multilayer board having a larger number of layers can be manufactured. In the method for manufacturing a multilayer circuit board according to this embodiment, a completed multilayer circuit board that has been inspected and a circuit board connecting member are laminated, so that a high manufacturing yield can be obtained and an increase in cost can be suppressed. Further, according to the manufacturing method of this embodiment, a multilayer substrate having a large number of stacked layers can be relatively easily manufactured.
【0051】なお、中間層として、完成した多層基板で
はなく加熱加圧前の積層体を用い、その両側に回路基板
接続材や銅箔を重ねた後、一度に加熱加圧を行うことよ
って多層回路基板を作製してもよい。また、ガラスエポ
キシ4層回路基板の代わりに、実施例2で回路基板接続
材を用いて作製したアラミドエポキシ両面基板を中間層
として使用した場合も、同様に良好な評価結果が得られ
た。It is to be noted that the intermediate layer is not a completed multi-layer substrate but a laminated body before heating and pressurizing, and a circuit board connecting material and a copper foil are laminated on both sides thereof, and then heated and pressurized at once to perform multi-layering. A circuit board may be manufactured. Similarly, when an aramid epoxy double-sided board manufactured by using the circuit board connecting material in Example 2 was used as the intermediate layer instead of the glass epoxy four-layer circuit board, similarly good evaluation results were obtained.
【0052】[0052]
【発明の効果】以上説明した通り、本発明の印刷基材に
よれば、印刷・充填するペースト状組成物の繰返し使用
可能回数が大幅に向上する。また、この印刷基材を用い
て信頼性の高い回路基板接続材を作製し、さらに、この
回路基板接続材を用いて多層基板を容易かつ合理的に製
造することがができる。As described above, according to the printing substrate of the present invention, the number of times the paste composition to be printed / filled can be used repeatedly is greatly improved. In addition, a highly reliable circuit board connecting material can be manufactured using the printed base material, and a multilayer board can be easily and rationally manufactured using the circuit board connecting material.
【図1】本発明の実施例1に係る印刷基材の断面図FIG. 1 is a cross-sectional view of a printing base material according to a first embodiment of the present invention.
【図2】本発明の実施例2に係る両面回路基板の製造工
程を示す図FIG. 2 is a diagram showing a manufacturing process of a double-sided circuit board according to Embodiment 2 of the present invention.
【図3】本発明の実施例3に係る多層回路基板の製造方
法を示す断面図FIG. 3 is a cross-sectional view illustrating a method for manufacturing a multilayer circuit board according to Embodiment 3 of the present invention.
【図4】本発明の実施例4に係る多層回路基板の製造方
法を示す断面図FIG. 4 is a sectional view showing a method for manufacturing a multilayer circuit board according to Embodiment 4 of the present invention.
101 マスクフィルム 102 プリプレグ 103 バイア 104,204,304,404 導電性組成物 203,303,403 回路基板接続材 205,405 銅箔 206 外層回路パターン 306,406 回路パターン 307,407 ドリル加工孔 308,408 銅メッキスルー 309 ガラスエポキシ両面板 410 ガラスエポキシ4層基板 412 ランド Reference Signs List 101 mask film 102 prepreg 103 via 104, 204, 304, 404 conductive composition 203, 303, 403 circuit board connection material 205, 405 copper foil 206 outer layer circuit pattern 306, 406 circuit pattern 307, 407 drilled hole 308, 408 Copper plating through 309 Glass epoxy double-sided board 410 Glass epoxy 4-layer board 412 Land
───────────────────────────────────────────────────── フロントページの続き (72)発明者 上田 洋二 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoji Ueda 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.
Claims (12)
る工程に用いられる多層構造の印刷基材であって、最外
層のうちの少なくとも一方がマスクフィルムの役割を担
い、前記マスクフィルムの外面が離型性を有しているこ
とを特徴とする印刷基材。1. A printing substrate having a multilayer structure used in a step of filling or printing a paste-like composition, wherein at least one of an outermost layer plays a role of a mask film, and an outer surface of the mask film. Has a mold release property.
ムと、その上に塗布された離型剤とからなる請求項1記
載の印刷基材。2. The printing substrate according to claim 1, wherein the mask film comprises a synthetic resin film and a release agent applied thereon.
求項2記載の印刷基材。3. The printing substrate according to claim 2, wherein the release agent is a silicon-based release agent.
項2記載の印刷基材。4. The printing substrate according to claim 2, wherein the release agent is a fluorine-based release agent.
る工程に用いられる多層構造の印刷基材であって、最外
層のうちの少なくとも一方がマスクフィルムの役割を担
い、前記マスクフィルムの外面の表面粗さが100nm
以下であることを特徴とする印刷基材。5. A multi-layered printing substrate used in a step of filling or printing a paste-like composition, wherein at least one of an outermost layer plays a role of a mask film, and an outer surface of the mask film. Has a surface roughness of 100 nm
A printing substrate characterized by the following.
る工程に用いられる多層構造の印刷基材であって、最外
層のうちの少なくとも一方がマスクフィルムの役割を担
い、前記マスクフィルムの弾性率が300kgf/mm
2以上であることを特徴とする印刷基材。6. A printing substrate having a multilayer structure used in a step of filling or printing a paste-like composition, wherein at least one of an outermost layer plays a role of a mask film, and has an elasticity of the mask film. Rate is 300kgf / mm
A printing base material characterized by being 2 or more.
である請求項5又は6記載の印刷基材。7. The printing substrate according to claim 5, wherein the mask film is a synthetic resin film.
レフタレートフィルムまたはポリプロピレンフィルムで
ある請求項2、3、4又は7記載の印刷基材。8. The printing substrate according to claim 2, wherein the synthetic resin film is a polyethylene terephthalate film or a polypropylene film.
刷基材の所定位置に貫通孔が設けられ、前記貫通孔に導
電性組成物が充填されている回路基板接続材。9. A circuit board connecting material, wherein a through-hole is provided in a predetermined position of the printing base material according to claim 1, and the through-hole is filled with a conductive composition.
5〜20μmの金、銀、ニッケル、銅、パラジウム、及
びこれらの合金から選ばれる少なくとも1つの金属粉末
80〜92重量%と、エポキシ樹脂、フェノール樹脂、
ポリイミド樹脂及びアクリル樹脂から選ばれる少なくと
も1つの合成樹脂4.5〜20重量%を含んでいる請求
項9記載の回路基板接続材。10. The conductive composition has an average particle size of 0.1.
5 to 20 μm of 80 to 92% by weight of at least one metal powder selected from gold, silver, nickel, copper, palladium and alloys thereof, an epoxy resin, a phenol resin,
10. The circuit board connecting material according to claim 9, comprising 4.5 to 20% by weight of at least one synthetic resin selected from a polyimide resin and an acrylic resin.
有する回路基板と、少なくとも1層以上の回路パターン
を有する回路基板との間に、請求項9又は10記載の回
路基板接続材からマスクフィルムを取り除いたものを挟
み、得られた積層体を加熱加圧する工程を備えた多層回
路基板の製造方法。11. The circuit board connecting material according to claim 9, wherein a mask film is removed between a circuit board having at least two or more circuit patterns and a circuit board having at least one or more circuit patterns. A method for producing a multilayer circuit board, comprising a step of heating and pressing the obtained laminate while sandwiching the laminated body.
有する回路基板の両面に、請求項9又は10記載の回路
基板接続材からマスクフィルムを取り除いたものを重
ね、さらにその両外側に金属箔を張り付け、得られた積
層体を加熱加圧した後、前記金属箔を加工して回路パタ
ーンを形成する工程を備えた多層回路基板の製造方法。12. A circuit board having at least two layers of circuit patterns, on both sides of which a mask film is removed from the circuit board connecting material according to claim 9, and a metal foil is attached on both outer sides. And a method of manufacturing a multilayer circuit board, comprising a step of heating and pressurizing the obtained laminate, and processing the metal foil to form a circuit pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34396696A JPH10190159A (en) | 1996-12-24 | 1996-12-24 | Printing substrate, circuit board-connecting material using the substrate, and manufacture of multilayered circuit board using the connection material |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34396696A JPH10190159A (en) | 1996-12-24 | 1996-12-24 | Printing substrate, circuit board-connecting material using the substrate, and manufacture of multilayered circuit board using the connection material |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10190159A true JPH10190159A (en) | 1998-07-21 |
Family
ID=18365619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34396696A Pending JPH10190159A (en) | 1996-12-24 | 1996-12-24 | Printing substrate, circuit board-connecting material using the substrate, and manufacture of multilayered circuit board using the connection material |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10190159A (en) |
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